Page 1
PI90LV14/PI90LVT14
EN
CLK
GND
SEL
GND
CLK
SCLK
GND
V
CC
V
CC
12
11
13
14
15
16
19
20
17
18
CLK5
OUT–
CLK5
OUT+
10
9
CLK4
OUT–
CLK4
OUT+
8
7
CLK3
OUT–
CLK3
OUT+
6
5
CLK2
OUT–
CLK2
OUT+
4
3
CLK1
OUT–
CLK1
OUT+
2
1
D
Q
V
1
0
110
Ω
PI90LVT14
Only
1:5 Clock Distribution
Features
• Meets and Exceeds the Requirements of ANSI
TIA/EIA-644-1995
• Designed for clocking rates up to 320MHz
• Operates from a single 3.3V Supply
• Low Voltage Differential Signaling (LVDS) with Output
Voltages of ±350mV into a 100Ω load
• Choice between LVDS or TTL clock input
• Synchronous Enable/Disable
• Clock outputs default LOW when inputs open
• Multiplexed clock input
- Internal 300kΩ pullup resistor on input pins
- CLK and CLK have 110Ω internal termination (PI90LVT14)
• 50ps Output-to-Output Skew
• 475ps typical propagation delay
• Bus Pins are high impedance when disabled or with
VCC less than 1.5V
• TTL inputs are 5V Tolerant
• Power Dissipation at 400Mbits/s of 150mW
• Function compatible to Motorola (PECL)
MC100EL14 and Micrel/Synergy (PECL)
SY100EL14V
• >9kV ESD Protection
• 20-pin TSSOP (L) and QSOP (Q) packages
Description
The PI90LV14 implements low voltage differential signaling (LVDS)
to achieve clocking rates as high as 320MHz with low skew.
The PI90LV14 is a low-skew 1:5 clock distribution chip which
incorporates multiplexed clock inputs to allow for distribution of a
lower-speed, single-ended clock or a high-speed system clock.
When LOWthe SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will
only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. Because the internal flip-flop is clocked on the falling edge
of the input clock, all associated specification limits are referenced
to the negative edge of the clock input.
The intended application of these devices and signaling technique
is for high-speed clock distribution between boards.
PI90LV14 Block Diagram
Pin Descriptions
niPnoitnuF
KLC,KLCstuptuOkcolClaitnereffiD
Function Table
LXLL L
HXLL H
XLHL L
XHHL H
↓↓
* On next negative transition of CLK, or SCLK
KLCStupnIkcolCLTTVL
NEelbanEsuonorhcnyS
LEStupnItceleSkcolC
5-1KLC
±TUO
KLCKLCSLES*NE+TUOKLC
XH *Z
stupnIkcolClaitnereffiD
1
PS8538 04/25/01
Page 2
PI90LV14/PI90LVT14
1:5 Clock Distribution
Electrical Characteristics over Recommended Operating Conditions (unless otherwise noted).
lobmySretemaraPsnoitidnoCtseT.niM.pyT
V
∆ V
DO
DO
edutingamegatlovtuptuolaitnereffiD
R
egatlovtuptuolaitnereffidniegnahC
001= Ω
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2dna1serugiFeeS
setatscigolneewtebedutingam
742043454
05– 05
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.xaMstinU
Vm
V
∆V
V
I
)SS(CO
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egatlov
tuptuoedom-nommocetats-ydaetS
edom-nommocetats-ydaetsniegnahC
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3erugiFeeS
521.104.17.1V
05– 05
Vm
)PP(CO
I
CC
I
HI
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edom-nommockaep-ot-kaeP
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NI
001= Ω VNIV=
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Aµ
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ZO
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V
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V0=
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tnerructuptuotiucric-trohS
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V0=
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CC
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2
PS8538 04/25/01
Ω
Page 3
PI90LV14/PI90LVT14
1:5 Clock Distribution
Switching Characteristics over Recommended Operating Conditions (unless otherwise noted)
citsiretcarahClobmyS.niM.pyT.xaMstinUnoitidnoC
tuptuOotyaleDnoitagaporP
S±TUOKLCotKLC
xNEKLCot
±TUOKLCotKLC
±TUOKLCotKLCS
t
HLP
t
LHP
±TUOKLCotLES
0.3
5.2
6.2
emiTelbasiD
±TUOKLCotKLCSroKLCt
ZHP
t
ZLP
t
HZP
t
LZP
7.2
7.2
7.4
7.3
wekStraP-ot-traP
Qot)ffiD(KLC
QotKLCS,)ES(KLC
wekSeciveDhtiW
t
weks
t
weks
t
weks
emiTputeS
t
s
KLCotNEC
t
s
001
001
001–
001–
emiTdloH
otNEC,xNEKLCS
xKLCotNEC,xNE
)KLC(gniwStupnImuminiM V
)KLC(egnaRedoM.moC V
t
h
t
h
PP
RMC
02.0008.0
521.05.1VCC02.0-
055
005
(semiTllaF/esiR )%08–02
t
r
±TUOKLCotKLCS
t-
wekSesluPnoitrotsiDelcyCytuD t(
HLP
)t
LHP
egdeemas,wekSlennahC-ot-lennahC t
t
f
R1KS
R2KS
051
051
0020035
070916
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0.4
5.3
6.3
5.3
5.3
0.6
0.6
DBT
DBT
DBT
027
027
0021
0021
V
(8,9)
sn
sn
sp
sp
.
2
1
2
2
3
4
Notes:
1. Within-Device skew is defined for identical transitions on similar paths through a device.
2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK.
3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated
with only 50mV input swings.
4. The range in which the high level of the input swing must fall while meeting the VPP spec.
5. t
is the difference in receiver propagation delay (t
SKIR
PLH-tPHL
) of one device, and is the duty cycle distortion of
the output at any given temperature and VCC. The propagation delay specification is a device-to-device worst
case over process, voltage, and temperature.
6. t
is the difference in receiver propagation delay between channels in the same device of any outputs
SK2R
switching in the same direction. This parameter is guaranteed by design and characterization.
7. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak).
Output Criteria: 60%/40% duty cycle, V
(max) 0-4V, V
OL
(min) 2.7V, Load - 7pF (stray plus probes).
OH
8. CL includes probe and fixture capacitance.
9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr = 1ns, tf = 1ns (35%-65%). To
ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V;
control signals not slower than 3ns/V.
3
PS8538 04/25/01
Page 4
Parameter Measurement Information
D
I
I
D
IN
OUT+
I
I
OY
OZ
V
PI90LV14/PI90LVT14
1:5 Clock Distribution
OD
V
I
Input
D
OUT–
GND
V
ODOUT–
V
ODOUT+
V
OC
(V
Figure 1. Voltage and Current Definitions
D
D
OUT+
OUT–
V
OD
3.75kΩ
100Ω
3.75kΩ
Figure 2. VOD Test Circuit
ODOUT++VODOUT–
±
0V ≤ V
TEST
≤ 2.4V
)/2
D
Input
D
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Pulse Repetition Rate
(PRR) = 50 Mpps, Pulse width = 10 ±0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
The measurement of V
49.9Ω ±1% (2 places)
OUT+
OUT–
is made on test equipment with a –3dB bandwidth of at least 300MHz.
OC(PP)
V
I
V
OC
V
OC(PP)
V
OC(SS)
Figure 3. Test Circuit & Definitions for the Driver Common-Mode Output Voltage
4
PS8538 04/25/01
3V
0V
Page 5
Parameter Measurement Information (continued)
PI90LV14/PI90LVT14
1:5 Clock Distribution
Input
32V
1.4V
0.8V
100%
80%
Input
D
D
OUT+
OUT–
V
OD
CL= 10pF
(2 places)
100Ω ±1%
Output
t
PLH
0V
V
OD(H)
t
PHL
V
OD(L)
20%
0%
t
f
t
r
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Pulse Repetition Rate
(PRR) = 15 Mpps, Pulse width = 10 ±0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
Figure 4. Test Circuit, Timing, & Voltage Definitions for the Differential Output Signal
49.9Ω ±1% (2 places)
+
1.2V
–
0.8V or 2V
Input
D
D
OUT+
OUT–
V
ODOUT+VODOUT–
2V
1.4V
Input
V
ODOUT+
V
ODOUT–
t
PZH
or
t
PHZ
0.8V
≅1.4V
1.3V
1.2V
t
PZL
t
PLZ
1.2V
V
ODOUT–
V
ODOUT+
or
1.1V
≅1V
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Pulse Repetition Rate
(PRR) = 0.5 Mpps, Pulse width = 500 ±10ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
Figure 5. Enable & Disable Time Circuit & Definitions
5
PS8538 04/25/01
Page 6
20-Pin QSOP (Q) Package
20
1
.337
.344
8.56
8.74
.150
.157
3.81
3.99
Guage Plane
.010
0.254
Detail A
.041
1.04
REF
.016
.035
0.41
0.89
.008
0.20
MIN.
PI90LV14/PI90LVT14
1:5 Clock Distribution
.008
.013
0.20
0.33
0˚-6˚
.025
BSC
0.635
X.XX
X.XX
20-Pin TSSOP (L) Package
20
1
.0256
BSC
0.65
.058
REF
1.47
.008
0.203
.012
0.305
DENOTES DIMENSIONS
IN MILLIMETERS
.252
.260
6.4
6.6
.007
.012
0.19
0.30
.169
.177
.002
.006
.053
.069
4.3
4.5
.047
1.20
Max
.004
.010
0.05
0.15
1.35
1.75
SEATING
PLANE
0.101
0.254
SEATING
PLANE
.015 x 45˚
0.38
0.41
.016
1.27
.050
.228
.244
5.79
6.19
X.XX
DENOTES CONTROLLING
X.XX
DIMENSIONS IN MILLIMETERS
0.45
0.75
.238
.269
6.1
6.7
Detail A
.018
.030
.007
.010
0.178
0.254
.004
.008
0.09
0.20
Ordering Information
edoCgniredrOepyTegakcaPegnaRgniredrO
L41VL09IP
L41TVL09IP
Q41VL09IP
Q41TVL09IP
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
POSSTlim-371niP-02
C°58otC°04–
POSQlim-051niP-02
Pericom Semiconductor Corporation
6
PS8538 04/25/01
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