Datasheet PI74LPT646L, PI74LPT646Q, PI74LPT646R, PI74LPT646S, PI74LPT652L Datasheet (PERICOM)
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PS2064A 01/15/97
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PI74LPT646
PI74LPT652
3.3V 8-BIT REGISTERED TRANSCEIVERS
Fast CMOS 3.3V 8-Bit
Registered T ransceiver
Logic Block Diagram
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Product Features
• Compatible with LCX™ and LVT™ families of products
• Supports 5V tolerant mixed signal mode operation
– Input can be 3V or 5V
– Output can be 3V or connected to 5V bus
• Advanced low power CMOS operation
• Excellent output drive capability:
Balanced drives (24 mA sink and source)
• Low ground bounce outputs
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Packages available:
– 24-pin 173-mil wide plastic TSSOP (L)
– 24-pin 150-mil wide plastic QSOP (Q)
– 24-pin 150-mil wide plastic TQSOP (R)
– 24-pin 300-mil wide plastic SOIC (S)
Product Description
Pericom Semiconductor’s PI74LPT series of logic circuits are produced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74LPT646 and PI74LPT652 are designed with a bus
transceiver with 3-state D-type flip-flops and control circuitry
arranged for multiplexed transmission of data directly from the data
bus or from the internal storage registers. The PI74LPT652 utilizes
GAB and GBA signals to control the transceiver functions. The
PI74LPT646 utilizes the enable control (G) and direction pins
(DIR) to control the transceiver functions. SAB and SBA control
pins are used to select either real-time or stored data transfer. The
circuitry used for select control will eliminate the typical decoding
glitch that occurs in a multiplexer during the transition between
real-time and stored data. A low input level selects real-time data
and a high selects stored data.
The PI74LPT646 and PI74LPT652 can be driven from either 3.3V
or 5.0V devices allowing this device to be used as a translator in a
mixed 3.3/5.0V system.
PI74LPT646
PI74LPT652
0D
CPAB
C
0
CPBA
SBA
DIR
G
SAB
0D
C
0
A REG
B REG
B
0
A
0
1 OR 8 CHANNELS
TO 7 OTHER CHANNELS
GBA GAB
PI74LPT652 ONLY
PI74LPT646
ONLY
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PI74LPT646
PI74LPT652
3.3V 8-BIT REGISTERED TRANSCEIVERS
Pin Name Description
A0-A7 Data Register A Inputs
Data Register B Outputs
B0-B7 Data Register B Inputs
Data Register A Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Output Data Source Select Inputs
DIR, G Output Enable Inputs (LPT646)
GAB, GBA Output Enable Inputs (LPT652)
GND Ground
VCC Power
Product Pin Description
CPAB
SAB
DIR
A
0
A1
A2
A3
A4
A5
A6
A7
GND
V
CC
CPBA
SBA
G
B
0
B1
B2
B3
B4
B5
B6
B7
24-PIN
L24
Q24
R24
S24
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PI74LPT646
Product Pin Configuration
CPAB
SAB
GAB
A
0
A1
A2
A3
A4
A5
A6
A7
GND
V
CC
CPBA
SBA
GBA
B
0
B1
B2
B3
B4
B5
B6
B7
24-PIN
L24
Q24
R24
S24
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PI74LPT652
Product Pin Configuration
PI74LPT646 Truth Table
Inputs DATA I/O
(2)
Function/Operation G DIR CPAB CPBA SAB SBA A0-A7 B0-B7
Isolation H X H or L H or L X X Input Input
Store A and B Data H X ↑↑XX
Real Time B Data to A Bus L L X X X L Output Input
Stored B Data to A Bus L L X H or L X H
Real Time A Data to B Bus L H X X L X Input Output
Stored A Data to B Bus L H H or L X H X
Inputs DATA I/O
(2)
Function/Operation GAB GBA CPAB CPBA SAB SBA A0-A7 B0-B7
Isolation L H H or L H or L X X Input Input
Store A and B Data L H ↑↑XX
Store A, Hold B X H ↑ H or L X X Input
Unspecified
(1)
Store A in Both Registers H H ↑↑X
(2)
X Input Output
Hold A, Store B L X H or L ↑ XX
Unspecified
(1)
Input
Store B in Both Registers L L ↑↑XX
(2)
Output Input
Real Time B Data to A Bus L L X X X L Output Input
Stored B Data to A Bus L L X H or L X H
Real Time A Data to B Bus HHXXLXInputOutput
Stored A Data to B Bus H H H or L X H X
Stored A Data to B Bus and H L H or L H or L H H Output Output
Stored B Data to A Bus
PI74LPT652 Truth Table
Notes:
1. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data
input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition
on the clock inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
H = High Voltage Level; L = Low Voltage Level; X = Don't Care; ↑ = LOW-to-HIGH transition
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PI74LPT646
PI74LPT652
3.3V 8-BIT REGISTERED TRANSCEIVERS
REAL-TIME TRANSFER
BUS B TO A
LPT646 DIR G CPAB CPBA SAB SBA
LLXXXL
LPT652 GAB GBA CPAB CPBA SAB SBA
LLXXXL
REAL-TIME TRANSFER
BUS A TO B
LPT646 DIR G CPAB CPBA SAB SBA
HL X X L X
LPT652 GAB GBA CPAB CPBA SAB SBA
HH X X L X
STORAGE FROM
A AND/OR B
TRANSFER STORES
DATA TO A AND/OR B
BUS
A
BUS
B
BUS
A
BUS
B
LPT646 DIR G CPAB CPBA SAB SBA
HL ↑ XXX
LLX ↑ XX
XH ↑↑XX
LPT652 GAB GBA CPAB CPBA SAB SBA
XH ↑ XXX
LXX ↑ XX
LH ↑↑XX
LPT646
(1)
DIR G CPAB CPBA SAB SBA
L L X H or L X H
H L H or L X H X
LPT652 GAB GBA CPAB CPBA SAB SBA
H L H or L H or L H H
1. Note: The LPT646 cannot transfer data to
A bus and B bus simultaneously.
BUS
A
BUS
B
BUS
A
BUS
B
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PI74LPT646
PI74LPT652
3.3V 8-BIT REGISTERED TRANSCEIVERS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 2.7V to 3.6V)
Parameters Description Test Conditions
(1)
Min. Typ
(2)
Max. Units
VIH Input HIGH Voltage (Input pins) Guaranteed Logic HIGH Level 2.2 — 5.5 V
Input HIGH Voltage (I/O pins) 2.0 — 5.5 V
VIL Input LOW Voltage Guaranteed Logic LOW Level –0.5 — 0.8 V
(Input and I/O pins)
IIH Input HIGH Current (Input pins) VCC = Max. VIN = 5.5V — — ±1 µA
Input HIGH Current (I/O pins) VCC = Max. VIN = VCC ——±1µA
IIL Input LOW Current (Input pins) VCC = Max. VIN = GND — — ±1 µA
Input LOW Current (I/O pins) VCC = Max. VIN = GND — — ±1 µA
IOZH High Impedance Output Current VCC = Max. VOUT = 5.5V — — ±1 µA
IOZL (3-State Output pins) VCC = Max. VOUT = GND — — ±1 µA
VIK Clamp Diode Voltage VCC = Min., IIN = –18 mA — –0.7 –1.2 V
IODH Output HIGH Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V
(3)
–36 –60 –110 mA
IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V
(3)
50 90 200 mA
VOH Output HIGH Voltage VCC = Min. IOH = –0.1 mA Vcc-0.2 — — V
VIN = VIH or VIL IOH = –3 mA 2.4 3.0 — V
VCC = 3.0V, IOH = –8 mA 2.4
(5)
3.0 — V
VIN = VIH or VIL IOH = –24 mA 2.0 — —
VOL Output LOW Voltage VCC = Min. IOL = 0.1 mA — — 0.2 V
VIN = VIH or VIL IOL = 16 mA — 0.2 0.4 V
IOL = 24 mA — 0.3 0.5 V
IOS Short Circuit Current
(4)
VCC = Max.
(3)
, VOUT = GND –60 –85 –240 mA
IOFF Power Down Disable VCC = 0V, VIN or VOUT
≤≤
≤≤
≤ 4.5V — — ±100 µA
VH Input Hysteresis — 150 — mV
Capacitance (TA = 25°C, f = 1 MHz)
Parameters
(1)
Description Test Conditions Typ. Max. Units
CIN Input Capacitance VIN = 0V 4.5 6 pF
COUT Output Capacitance VOUT = 0V 5.5 8 pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC – 0.6V at rated current.
Note:
1. This parameter is determined by device characterization but is not production tested.
Storage Temperature............................................................–65°C to +150°C
Ambient Temperature with Power Applied...........................–40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only).... –0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) –0.5V to +7.0V
DC Input Voltage .................................................................. –0.5V to +7.0V
DC Output Current ............................................................................ 120 mA
Power Dissipation...................................................................................1.0W
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PI74LPT646
PI74LPT652
3.3V 8-BIT REGISTERED TRANSCEIVERS
Power Supply Characteristics
Parameters Description Test Conditions
(1)
Min. Typ
(2)
Max. Units
ICC Quiescent Power Supply Current VCC = Max. VIN = GND or VCC 0.1 10 µA
∆ICC Quiescent Power Supply Current VCC = Max. VIN = VCC – 0.6V
(3)
2.0 30 µA
TTL Inputs HIGH
ICCD Dynamic Power Supply
(4)
VCC = Max., VIN = VCC 50 75 µA/
Outputs Open VIN = GND MHz
G = DIR = GND
One Bit Toggling
50% Duty Cycle
IC Total Power Supply VCC = Max., VIN = VCC – 0.6V 0.6 2.3 mA
Current
(6)
Outputs Open VIN = GND
fI = 10 MHZ
50% Duty Cycle
G = DIR = GND
One Bit Toggling
VCC = Max., VIN = VCC – 0.6V 2.1 4.7
(5)
Outputs Open VIN = GND
fI = 2.5 MHZ
50% Duty Cycle
G = DIR = GND
8 Bits Toggling
Notes:
1. ForMax. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
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PI74LPT646
PI74LPT652
3.3V 8-BIT REGISTERED TRANSCEIVERS
PI74LPT646 Switching Characteristics over Operating Range
(1)
LPT646 LPT646A LPT646C
Com. Com. Com.
Parameters Description Conditions
(2)
Min.
(3)
Max. Min.
(3)
Max. Min.
(3)
Max. Units
tPLH Propagation Delay CL = 50pF 2.0 7.5 2.0 6.3 1.5 5.4 ns
tPHL Bus to Bus RL = 500Ω
tPZH Output Enable Time 2.0 14.0 2.0 9.8 1.5 7.8 ns
tPZL G, DIR to Bus
tPHZ Output Disable Time
(3)
2.0 9.0 2.0 6.3 1.5 6.3 ns
tPLZ G, DIR to Bus
tPLH Propagation Delay 2.0 9.0 2.0 6.3 1.5 5.7 ns
tPHL Clock to Bus
tPLH Propagation Delay 2.0 9.5 2.0 7.7 1.5 6.2 ns
tPHL SBA or SAB to Bus
tSU Setup Time HIGH or 4.0 — 2.0 — 2.0 — ns
LOW, BUS to Clock
tH Hold Time HIGH or 2.0 — 1.5 — 1.5 — ns
LOW, Bus to Clock
tW Clock Pulse Width
(3)
6.0 — 5.0 — 5.0 — ns
HIGH or LOW
Notes:
1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For Vcc = 2.7V, extended range, all
Propagation Delays and Enable/Disable times should be degraded by 20%.
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. This parameter is guaranteed but not production tested.
5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
PI74LPT652 Switching Characteristics over Operating Range
(1)
LPT652 LPT652A LPT652C
Com. Com. Com.
Parameters Description Conditions
(2)
Min.
(3)
Max. Min.
(3)
Max. Min.
(3)
Max. Units
tPLH Propagation Delay CL = 50pF 2.0 7.5 2.0 6.3 1.5 5.4 ns
tPHL Bus to Bus RL = 500Ω
tPZH Output Enable Time 2.0 14.0 2.0 9.8 1.5 7.8 ns
tPZL GBA, GAB to Bus
tPHZ Output Disable Time
(3)
2.0 9.0 2.0 6.3 1.5 6.3 ns
tPLZ GBA, GAB to Bus
tPLH Propagation Delay 2.0 9.0 2.0 6.3 1.5 5.7 ns
tPHL Clock to Bus
tPLH Propagation Delay 2.0 9.5 2.0 7.7 1.5 6.2 ns
tPHL SBA or SAB to Bus
tSU Setup Time HIGH or 4.0 — 2.0 — 2.0 — ns
LOW, BUS to Clock
tH Hold Time HIGH or 2.0 — 1.5 — 1.5 — ns
LOW, Bus to Clock
tW Clock Pulse Width
(3)
6.0 — 5.0 — 5.0 — ns
HIGH or LOW
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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