Datasheet PI74LPT543L, PI74LPT543Q, PI74LPT543R, PI74LPT543S Datasheet (PERICOM)

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PS2062A 01/15/97

PI74LPT543

3.3V 8-BIT LATCHED TRANSCEIVER

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Product Description

Pericom Semiconductor’s PI74LPT series of logic circuits are produced in the Company’s advanced 0.6 micron CMOS technology, achieving industry leading speed grades.

The PI74LPT543 is an 8-bit wide non-inverting transceiver designed with two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0–A7 or to take data from B0–B7, as indicated in the Truth Table. With CEAB LOW, a LOW signal makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change the A inputs. With CEAB and OEAB both LOW, the 3-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses the CEAB, LEAB, and OEAB inputs.

The PI74LPT543 can be driven from either 3.3V or 5.0V devices allowing this device to be used as a translator in a mixed

3.3/5.0V system.

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Logic Block Diagram

Product Features

• Compatible with LCX™ and LVT™ families of products

• Supports 5V tolerant mixed signal mode operation – Input can be 3V or 5V – Output can be 3V or connected to 5V bus

• Advanced low power CMOS operation

• Excellent output drive capability: Balanced drives (24 mA sink and source)

• Low ground bounce outputs

• Hysteresis on all inputs

• Industrial operating temperature range: –40°C to +85°C

• Packages available: – 24-pin 173-mil wide plastic TSSOP (L) – 24-pin 150-mil wide plastic QSOP (Q) – 24-pin 150-mil wide plastic TQSOP (R) – 24-pin 300-mil wide plastic SOIC (S)

Fast CMOS 3.3V 8-Bit

Latched T ransceiver

PI74LPT543

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PS2062A 01/15/97

PI74LPT543

3.3V 8-BIT LATCHED TRANSCEIVER

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Pin Name Description

OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) CEAB A-to-B Enable Input (Active LOW) CEBA B-to-A Enable Input (Active LOW) LEAB A-to-B Latch Enable Input (Active LOW) LEBA B-to-A Latch Enable Input (Active LOW) A0-A7 A-to-B Data Inputs or B-to-A 3-State Outputs B0-B7 B-to-A Data Inputs or A-to-B 3-State Outputs GND Ground VCC Power

Product Pin Description

LEBA

OEBA

A1 A2 A3 A4 A5 A6 A7

CEAB

GND

CEBA B

B1 B2 B3 B4 B5 B6 B7 LEAB OEAB

24-PIN

L24 Q24 R24 S24

Product Pin Configuration

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

Latch Output

Inputs Status Buffers

CEAB LEAB OEAB A-to-B B0–B7

H X X Storing High-Z X H X Storing X X X H X High Z L L L Transparent Current A Inputs L H L Storing Previous* A Inputs

Truth Table (Non-Inverting)

(1,2)

For A-to-B (Symmetric with B-to-A)

Notes:

1. *Before LEAB LOW-to-HIGH Transition H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care or Irrevelant

2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA, and OEBA.

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PS2062A 01/15/97

PI74LPT543

3.3V 8-BIT LATCHED TRANSCEIVER

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Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Note:

Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 2.7V to 3.6V)

Parameters Description Test Conditions

(1)

Min. Typ

(2)

Max. Units

VIH Input HIGH Voltage (Input pins) Guaranteed Logic HIGH Level 2.2 — 5.5 V

Input HIGH Voltage (I/O pins) 2.0 — 5.5 V

VIL Input LOW Voltage Guaranteed Logic LOW Level –0.5 — 0.8 V

(Input and I/O pins)

IIH Input HIGH Current (Input pins) VCC = Max. VIN = 5.5V — — ±1 µA

Input HIGH Current (I/O pins) VCC = Max. VIN = VCC ——±1µA

IIL Input LOW Current (Input pins) VCC = Max. VIN = GND — — ±1 µA

Input LOW Current (I/O pins) VCC = Max. VIN = GND — — ±1 µA IOZH High Impedance Output Current VCC = Max. VOUT = 5.5V — — ±1 µA IOZL (3-State Output pins) VCC = Max. VOUT = GND — — ±1 µA VIK Clamp Diode Voltage VCC = Min., IIN = –18 mA — –0.7 –1.2 V IODH Output HIGH Current VCC = 3 .3V, VIN = VIH or VIL, VO = 1.5V

(3)

–36 –60 –110 mA

IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V

(3)

50 90 200 mA

VOH Output HIGH Voltage VCC = Min. IOH = –0.1 mA Vcc-0.2 — — V

VIN = VIH or VIL IOH = –3 mA 2.4 3.0 — V VCC = 3.0V, IOH = –8 mA 2.4

(5)

3.0 — V

VIN = VIH or VIL IOH = –24 mA 2.0 — —

VOL Output LOW Voltage VCC = Min. IOL = 0.1 mA — — 0.2 V

VIN = VIH or VIL IOL = 16 mA — 0.2 0.4 V

IOL = 24 mA — 0.3 0.5 V

IOS Short Circuit Current

(4)

VCC = Max.

(3)

, VOUT = GND –60 –85 –240 mA

IOFF Power Down Disable VCC = 0V, VIN or VOUT

≤≤

≤ 4.5V — — ±100 µA

VH Input Hysteresis — 150 — mV

Capacitance (TA = 25°C, f = 1 MHz)

Parameters

(1)

Description Test Conditions Typ. Max. Units

CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 5.5 8 pF

Notes:

1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading.

3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

4. This parameter is guaranteed but not tested.

5. VOH = VCC – 0.6V at rated current.

Note:

1. This parameter is determined by device characterization but is not production tested.

Storage Temperature............................................................. –55°C to +125°C

Ambient Temperature with Power Applied............................ –40°C to +85°C

Supply Voltage to Ground Potential (Inputs & Vcc Only)......–0.5V to +7.0V

Supply Voltage to Ground Potential (Outputs & D/O Only) ..–0.5V to +7.0V

DC Input Voltage ....................................................................–0.5V to +7.0V

DC Output Current .............................................................................. 120 mA

Power Dissipation....................................................................................1.0W

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PS2062A 01/15/97

PI74LPT543

3.3V 8-BIT LATCHED TRANSCEIVER

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Power Supply Characteristics

Parameters Description Test Conditions

(1)

Min. Typ

(2)

Max. Units

ICC Quiescent Power Supply Current VCC = Max. VIN = GND or VCC 0.1 10 µA ∆ICC Quiescent Power Supply Current VCC = Max. VIN = VCC – 0.6V

(3)

2.0 30 µA

TTL Inputs HIGH

ICCD Dynamic Power Supply

(4)

VCC = Max., VIN = VCC 50 75 µA/ Outputs Open VIN = GND MHz CEAB and OEAB = GND CEBA = VCC One Bit Toggling 50% Duty Cycle

IC Total Power Supply VCC = Max., VIN = VCC – 0.6V 0.6 2.3 mA

Current

(6)

Outputs Open VIN = GND fI = 10 MHZ 50% Duty Cycle CEAB and OEAB = GND

CEBA = VCC One Bit Toggling

VCC = Max., VIN = VCC – 0.6V 2.1 4.7

(5)

Outputs Open VIN = GND fI = 2.5 MHZ 50% Duty Cycle CEAB and OEAB = GND

CEBA = VCC 8 Bits Toggling

Notes:

1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.

2. Typical values are at Vcc = 3.3V, +25°C ambient.

3. Per TTL driven input; all other inputs at Vcc or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

6. IC =IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz.

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PS2062A 01/15/97

PI74LPT543

3.3V 8-BIT LATCHED TRANSCEIVER

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LPT543 LPT543A LPT543C

Com. Com. Com.

Parameters Description Conditions

(2)

Min.

(3)

Max. Min.

(3)

Max. Min.

(3)

Max. Units

tPLH Propagation Delay Transparent CL = 50 pF 2.5 8.5 2.5 6.5 2.5 5.3 ns tPHL Mode AN to BN or BN to AN RL = 500Ω

tPLH Propagation Delay 2.5 12.5 2.5 8.0 2.5 7.0 ns tPHL LEBA to AN, LEAB to BN

tPZH Output Enable Time 2.0 12.0 2.0 9.0 2.0 8.0 ns tPZL OEBA or OEAB to AN or BN

CEBA or CEAB to AN or BN

tPZH Output Disable Time

(3)

2.0 9.0 2.0 7.5 2.0 6.5 ns

tPZL OEBA or OEAB to AN or BN

CEBA or CEAB to AN or BN

tSU Setup Time, HIGH or LOW 3.0 — 2.0 — 2.0 — ns

AN or BN to LEBA or LEAB

tH Hold Time, HIGH or LOW 2.0 — 2.0 — 2.0 — ns

AN or BN to LEBA or LEAB

tW LEBA or LEAB Pulse Width LOW

(3)

5.0 — 5.0 — 5.0 — ns

Switching Characteristics over Operating Range

(1)

Notes:

1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For Vcc = 2.7V, extended range, all Propagation Delays and Enable/Disable times should be degraded by 20%.

2. See test circuit and wave forms.

3. Minimum limits are guaranteed but not tested on Propagation Delays.

4. This parameter is guaranteed but not production tested.

5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com