Datasheet PI74ALVCH16344A, PI74ALVCH16344V Datasheet (PERICOM)

1

PS8166B 10/19/99

Product Description

Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.

The PI74ALVCH16344 is a 1-bit to 4-bit buffer/driver designed for

2.3V to 3.6V Vcc operation.
The address/driver is designed for applications where four seperate

memory locations must be addressed by a single address.
To ensure the high-impedance state during power up or power down,

OE should be tied to VCC through a pullup resistor; the minimum
value of the resistor is determined by the current-sinking capability
of the driver.

The PI74ALVCH16344 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.

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PI74ALVCH16344

1-Bit to 4-Bit Address/Driver

with 3-State Outputs

Logic Block Diagram

Product Features

• PI74ALVCH16344 is designed for low voltage operation

• V

CC

= 2.3V to 3.6V

• Hysteresis on all inputs

• Typical V

OLP

(Output Ground Bounce)

< 0.8V at VCC = 3.3V, TA = 25°C

• Typical V

OHV

(Output VOH Undershoot)

< 2.0V at VCC = 3.3V, TA = 25°C

• Bus Hold retains last active bus state during 3-State,

eliminating the need for external pullup resistors

• Industrial operation at 40°C to +85°C

• Packages available:

 56-pin 240 mil wide plastic TSSOP (A)
 56-pin 300 mil wide plastic SSOP (V)

OE1

A1

B11

A2

B14

B21

B24

OE3

A5

B51

A6

B54

B61

B64

OE2

A3

B31

A4

B34

B41

B44

OE4

A7

B71

A8

B74

B81

B84

1

8

14

2

6

9

13

29

36

42

34

30

41

37

28

15

21

16

20

23

27

56

43

49

48

44

55

51

2

PS8166B 10/19/99

PI74ALVCH16344

1-Bit to 4-Bit Address Driver with 3-State Outputs

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stupnIstuptuO

EOA nB

LH H

LL L

HH Z

1
2
3
4
5
6
7
8
9

56

10

55

11

54

12

53

13

52

14

51

15

50

16

49

17

48

18

47

19

46

20

45

21

44

22

43

23

42

24

41
40
39
38
37
36
35
34

33
25
26
27

32

31

30

28 29

OE

1

B

11

B

12

GND

B

13

B

14

VCC

A

1

B

21

B

22

GND

B

23

B

24

A

2

A

3

B

31

B

32

GND

B

33

B

34

A

4

VCC

B

41

B

42

GND

B

43

B

44

OE

2

B

81

B

82

GND

B

83

B

84

VCC

A

8

B

71

B

72

GND

B

73

B

74

A

7

A

6

B

61

B

62

GND

B

63

B

64

A

5

VCC

B

51

B

52

GND

B

53

B

54

OE

3

OE

4

Pin Name Description

OE 3-State Output Enable Inputs (Active LOW)
A Inputs
B 3-State Outputs
GND Ground
VCC Power

Product Pin Description Truth Table

(1)

Notes:

1 . H = High Signal Level

L = Low Signal Level
X = Don’t Care or Irrelevant
Z = High Impedance

Product Pin Configuration

56-Pin

A,V

3

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PI74ALVCH16344

1-Bit to 4-Bit Address Driver with 3-State Outputs

PS8166B 10/19/99

Recommended Operating Condition

(1)

sretemaraPnoitpircseDsnoitidnoCtseT.niM.pyT.xaMstinU

V

CC

egatloVylppuS56.16.3

V

V

HI

egatloVtupnIleveLHGIH

V

CC

V59.1otV56.1=Vx56.0

CC

V

CC

V7.2otV3.2=7.1

V

CC

V6.3otV7.2=2

V

LI

egatloVtupnIleveLWOL

V

CC

V59.1otV56.1=Vx53.0

CC

V

CC

V7.2otV3.2=7.0

V

CC

V6.3otV7.2=8.0

V

I

egatloVtupnI0V

CC

V

O

egatloVtuptuO0V

CC

I

HO

tnerruCtuptuOlevel-hgiH

V

CC

V56.1=4

Am

V

CC

V3.2=21

V

CC

V7.2=21

V

CC

V0.3=42

I

LO

tnerruCtuptuOlevel-woL

V

CC

V56.1=4

V

CC

V3.2=21

V

CC

V7.2=21

V

CC

V0.3=42

∆t ∆/ v

emitllafroesirnoitisnarTtupnI001V/sn

T

A

erutarepmeTriA-eerFgnitarepO04-58C°

Note:

1. Unused control inputs must be held at VCC or GND to ensure proper device operation.

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Supply Voltage Range,V

CC

...............................................................

0.5V to 4.6V

Input Voltage Range, V

I

: Except I/O ports

(1)

..............................

0.5V to 4.6V

I/O ports

(1,2)

...........................

0.5V to V

CC

+ 0.5V

Output Voltage Range, V

O

(1,2)

............................................

0.5V to V

CC

+0.5V

Input Clamp Current, I

IK (VI

<0) ........................................................ 50mA

Output Clamp Current, I

OK (VO

<0) .................................................. 50mA

Continuous Output Current, I

O

...................................................................

±50mA

Continuous Current through each V

CC

or GND ...............................±100mA

Package Thermal Impedance, θ

JA

(3)

............................................................

39ºC/W

Storage Temperature Range, T

STG

...............................................

65ºC to 150ºC

Note:

1. The input negative voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

Note:

Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi­cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

4

PS8166B 10/19/99

PI74ALVCH16344

1-Bit to 4-Bit Address Driver with 3-State Outputs

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DC Electrical Characteristics (Over the Operating Range, T

A

= 40°C to +85°C, VCC = 3.3V ±10%)

sretemaraPsnoitidnoCtseTV

CC

.niM.pyT

)1(

.xaMstinU

V

HO

I

HO

001= µAV6.3otV56.1V

CC

2.0

V

I

HO

4=mA V56.12.1

I

HO

6=mA V3.20.2

I

HO

21=mA

V3.27.1

7.2V 2.2

V0.34.2

I

HO

42=mA V0.30.2

V

LO

I

LO

001= µAV6.3otV56.12.0

I

LO

=Am4V56.154.0

I

LO

=Am6V3.24.0

I

LO

21=mA

V3.27.0

V7.24.0

I

LO

=Am42V355.0

I

I

VI=V

CC

DNGroV6.35±

µA

I

I

)dloH(

V

I

=V85.0

V56.1

52

V

I

=V70.152

V

I

=V7.0

V3.2

54

V

I

=V7.154

V

I

=V8.0

V3

57

V

I

=V257

V

I

=V6.3ot0

)2(

V6.3005±

I

ZO

)3(

VO=V

CC

DNGroV6.301±

I

CC

VI=V

CC

IDNGro

O

0=V6.302

∆I

CC

VtatupnienO

CC

,V6.0

VtastupnirehtO

CC

DNGro

V6.3otV3057

C

I

stupnIlortnoCV

I

=V

CC

DNGroV3.34

Fp

C

OI

stropBroAV

O

=V

CC

DNGroV3.38

Notes:

1. All typical values are at VCC = 3.3V, TA = 25ºC.

2. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to

switch the input from one state to another.

3. For I/O ports, the IOZ includes the input leakage current.

5

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PI74ALVCH16344

1-Bit to 4-Bit Address Driver with 3-State Outputs

PS8166B 10/19/99

sretemaraP

morF

)TUPNI(

oT

)TUPTUO(

V

CC

V2.0±V5.2=V

CC

V7.2=V

CC

V3.0±V3.3=

stinU

.niM

)2(

.xaM.niM

)2(

.xaM.niM

)2(

.xaM

t

DP

AB 0.10.50.40.16.3

sn

t

NE

EOB 0.18.60.60.10.5

t

SID

EOB 0.10.62.50.10.5

)0(kst

)3(

-53.0

)0(kst

)4(

-5.0

Switching Characteristics over Operating Range

(1)

Notes:

1. See test circuit and waveforms, Figures 1 and 2.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between outputs of same bank, and same device and same transition.
This parameter is warranted but not production tested.

4. Skew between outputs of all banks, and same device, A1-A8 tied together.
This parameter is warranted but not production tested.

Operating Characteristics, TA = 25ºC

retemaraPsnoitidnoCtseT

V

CC

V5.2=

V2.0±

V

CC

±V3.3=

V3.0

stinU

lacipyT

C

DP

noitapissiDrewoP

ecnaticapaC

delbanEstuptuO

C

L

,Fp05=

zHM01=f

8648

Fp

delbasiDstuptuO1141

6

PS8166B 10/19/99

PI74ALVCH16344

1-Bit to 4-Bit Address Driver with 3-State Outputs

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Parameter Measurement Information

VCC = 2.5V ±0.2V

t

su

t

h

Timing
Input

Data
Input

V

CC

V

CC

0V

V

CC

/2

V

CC

/2

V

CC

/2

0V

CL = 30pF

From Output

Under Test

GND

2xV

CC

Open

(See Note A)

500

Ω

S1

500

Ω

Input

0V

V

CC

/2 VCC/2

t

w

V

CC

Voltage Waveforms Propagation Delay Times

tseT1S

t

dp

nepO

t

/ZLP

t

LZP

Vx2

CC

t

/ZHP

t

HZP

DNG

Load Circuit

Voltage Waveforms Enable and Disable Times

Voltage Waveforms Setup and Hold Times

Voltage Waveforms Pulse Duration

Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tr ≤ 2ns, tf ≤ 2ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as t

ten

.

G. t

PLH

and t

PHL

are the same as tpd.

.

Figure 1. Load Circuit and Voltage Waveforms

t

PZL

Output

Control

(Low-level

enabling)

0V

V

CC

/

2

V

CC

/

2

V

CC

/

2

V

CC

/

2

t

PLZ

t

PHZ

V

OL

V

CC

0V

t

PZH

Output

Waveform 1

S1at2xV

CC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

V

OH

V

OH

V

OL

V

CC

+0.15V

-0.15V

INPUT

OUTPUT

V

CC

0V

V

OH

V

OL

t

PLH

t

PHL

VCC/2

V

CC

/2

V

CC

/2

V

CC

/2

7

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PI74ALVCH16344

1-Bit to 4-Bit Address Driver with 3-State Outputs

PS8166B 10/19/99

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax [phone] • http://www.pericom.com

t

su

t

h

Timing
Input

Data
Input

2.7V

2.7V

0V

1.5V 1.5V

1.5V

0V

Parameter Measurement Information

VCC = 2.7V and 3.3V ±0.3V

1.5V 1.5V

2.7V

Input

0V

t

w

Voltage Waveforms Propagation Delay Times

tseT1S

t

dp

nepO

t

/ZLP

t

LZP

V6

t

/ZHP

t

HZP

DNG

Load Circuit

Voltage Waveforms Enable and Disable Times

Voltage Waveforms Setup and Hold Times

Voltage Waveforms Pulse Duration

Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as t

ten

.

G. t

PLH

and t

PHL

are the same as tpd.

.

Figure 2. Load Circuit and Voltage Waveforms

INPUT

OUTPUT

2.7V

0V

V

OH

V

OL

t

PLH

t

PHL

1.5V

1.5V

1.5V

1.5V

CL = 50pF

From Output

Under Test

GND

6V

Open

(See Note A)

500

Ω

500

Ω

S1

t

PZL

Output

Control

(Low-level

enabling)

0V

1.5V

1.5V

1.5V

1.5V

t

PLZ

t

PHZ

V

OL

3V

0V

t

PZH

Output

Waveform 1

S1 at 6V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

V

OH

V

OH

V

OL

2.7V

+0.3V

-0.3V