Datasheet PI74ALVCH162260A, PI74ALVCH162260V Datasheet (PERICOM)

PI74ALVCH162260

12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs

1

PS8127 03/17/98

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PI74ALVCH162260

12-Bit To 24-Bit Multiplexed D-Type Latch

with 3-STATE Outputs

Product Description

Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.

The PI74ALVCH162260 is a 12-bit to 24-bit multiplexed D-type
latch designed for 2.3V to 3.6 VCC operation. It is used in
applications where two separate datapaths must be multiplexed
onto, or demultiplexed from, a single data path.

Typical applications include multiplexing and/or demulti­plexing address and data information in microprocessor or
bus-interface applications. This device is also useful in
memory-interleaving applications.

Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are
available for address and/or data transfer. The output-enable
(OE1B, OE2B, and OEA) inputs control the bus transceiver
functions. The OE1B and OE2B control signals also allow bank
control in the A-to-B direction.

Address and/or data information can be stored using the
internal storage latches. The latch-enable (LE1B, LE2B, LEA1B,
and LEA2B) inputs are used to control data storage. When the
latch-enable input is HIGH, the latch is transparent. When the
latch-enable input goes LOW, the data present at the inputs
is latched and remains latched until the latch-enable input is
returned HIGH.

To reduce overshoot and undershoot, the B-port outputs
include 26Ω series resistors.

To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pullup resistor, the
minimum value of the resistor is determined by the current­sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.

Logic Block Diagram

G1

OE2B

C1

1D

1B1

TO 11 OTHER CHANNELS

OE1B

OEA

A1

LE1B

LE2B
LEA1B
LEA2B

SEL

1
1

C1

1D

C1

1D

C1

1D

2B1

23

6

28

8

1

29

56

55

30

27

2

Product Features

• PI74ALVCH162260 is designed for low voltage operation

• V

CC

= 2.3V to 3.6V

• Hysteresis on all inputs

• Typical V

OLP

(Output Ground Bounce)

< 0.8V at VCC = 3.3V, TA = 25°C

• Typical V

OHV

(Output VOH Undershoot)

< 2.0V at VCC = 3.3V, TA = 25°C

• Bus Hold retains last active bus state during 3-STATE,

eliminating the need for external pullup resistors

• Industrial operation at 40°C to +85°C

• Packages available:

 56-pin 240 mil wide plastic TSSOP (A)
 56-pin 300 mil wide plastic SSOP (V)

2

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PS8127 03/17/98

PI74ALVCH162260

12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs

Pin Name Description

OE Output Enable Input (Active LOW)
SEL Select
LE Latch Enable
A,1B,2B Data Inputs
A,1B,2B 3-State Outputs
GND Ground
VCC Power

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

33
25
26
27
28

32

31

30

29

Product Pin Description

Note:

1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance

Product Pin Configuration

56-PIN

V56
A56

OEA

LE1B

2B3

GND

2B2

2B1

V

CC

A1

A2

A3

GND

A4

A5

A6

A7

A8

A9

GND

A10

A11

A12

V

CC

1B1

1B2

GND

1B3

LE2B

SEL

OE2B

LEA2B

2B4

GND

2B5

2B6

V

CC
2B7

2B8

2B9

GND

2B10

2B11

2B12

1B12

1B11

1B10

GND

1B9

1B8

1B7

V

CC
1B6

1B5

GND

1B4

LEA1B

OE1B

STUPNISTUPTUO

AB1AELB2AELB1EOB2EOB1B2

HH H L L H H

LH H L L L L

HH L L L H 0B2

LH L L L L 0B2

HL H L L 0B1H

LL H L L 0B1L

XL L L L 0B10B2

XX X H H Z Z

XX X L H evitcAZ

XX X H L Z evitcA

XX X L L evitcAevitcA

Truth Tables

(1)

B to A (OEB = H)

A to B (OEA = H)

In pu ts

Output

A

1B 2B SEL LE1B LE2B OEA

HXH H X L H

LXH H X L L

XXH L X L A

0

XH L X H L H
XL L X H L L
XX L X L L A

0

XXX X X H Z

PI74ALVCH162260

12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs

3

PS8127 03/17/98

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sretemaraPnoitpircseDsnoitidnoCtseT.niM.pyT.xaMstinU

V

CC

egatloVylppuS3.26.3

V

V

HI

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V

CC

V6.3otV7.2=0.2

V

CC

V7.2otV3.2=7.1

V

LI

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V

CC

V6.3otV7.2=8.0

V

CC

V7.2otV3.2=7.0

V

NI

egatloVtupnI0V

CC

V

TUO

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CC

I

HO

tuptuolevel-hgiH

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V

CC

V3.2=21-

Am

V

CC

V7.2=21-

V

CC

V0.3=42-

I

LO

tuptuolevel-woL

)troPA(tnerruc

V

CC

V3.2=21

V

CC

V7.2=21

V

CC

V0.3=42

I

HO

tuptuolevel-hgiH

)troPB(tnerruc

V

CC

V3.2=6-

V

CC

V7.2=8-

V

CC

C

V0.3=21-

I

LO

tuptuolevel-woL

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V

CC

V3.2=6

V

CC

V7.2=8

V

CC

V0.3=21

T

A

erutarepmetria-eerfgnitarepO04-58C°

Note:

1. Unused control inputs must be held HIGH or LOW to prevent them from floating.

Storage Temperature ........................................................... 65°C to +150°C

Ambient Temperature with Power Applied ........................ 40°C to +85°C

Input Voltage Range, V

IN

......................................................

0.5V to V

CC

+0.5V

Output Voltage Range, V

OUT

...............................................

0.5V to V

CC

+0.5V

DC Input Voltage .................................................................... 0.5V to +5.0V

DC Output Current ............................................................................ 100 mA

Power Dissipation .................................................................................. 1.0W

Note:

Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

4

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PS8127 03/17/98

PI74ALVCH162260

12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs

Notes:

1 . For Max. or Min. conditions use appropriate value specified under Electrical Characteristics for the applicable device type.
2 . Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading.
3 . This is the bus-hold maximum dynamic current required to swtich the input from one state to another.

DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)

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I

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I

HO

21-=mA

V

HI

=V7.1V3.27.1

V

HI

0.2=V V7.22.2

V

HI

V0.2=V0.34.2

I

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I

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V

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V

HI

=V0.20.3V 4.2

I

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8-=mA VHI=V0.2V7.20.2

I

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21-=mA VHIV0.2=V0.30.2

V

LO

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I

LO

001= mA.xaMot.niM2.0

I

LO

6=AmV

LI

V7.0=V3.24.0

I

LO

21=Am

V

LI

V7.0=V3.27.0

V

LI

V8.0=V7.24.0

I

LO

42=AmV

LI

V8.0=V0.355.0

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LO

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I

LO

001-= mA.xaMot.niM2.0

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4= mAV

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V7.0=V3.24.0

I

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LI

V7.0=V3.255.0

V

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V8.0=V0.355.0

I

LO

8=AmV

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V8.0=V7.26.0

I

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V8.0=V0.38.0

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V

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V

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57

V

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V0.2=57-

V

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PI74ALVCH162260

12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs

5

PS8127 03/17/98

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Timing Requirements over Operating Range

Note:

1. Unused control inputs must be held HIGH or LOW to prevent them from floating.

Switching Characteristics over Operating Range

(1)

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LESA2.15.76.61.16.5

t

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EOA 0.12.74.60.14.5

EOB0.17.71.70.10.6

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EOA 7.19.50.53.16.4

EOB7.14.65.53.11.5

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Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax [phone] • http://www.pericom.com

Notes:

1 . See test circuit and wave forms.
2 . Minimum limits are guaranteed but not tested on Propagation Delays.

Operating Characteristics, TA = 25ºC

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