Datasheet PI6CV855L Datasheet (PERICOM)

PI6CV855

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PLL Clock Driver for 2.5V

SSTL

2 DDR SDRAM Memory

Product Features

 PLL clock distribution optimized for SSTL_2 DDR SDRAM

applications.

 Distributes one differential clock input pair to five differential

clock output pairs.  Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2  Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2  External feedback pins (FBIN,FBIN) are used to

synchronize the outputs to the clock input.  Operates at AVDD = 2.5V for core circuit and internal PLL,

and V

= 2.5V for differential output drivers

DDQ

 Available Package:

 Plastic 28-pin TSSOP

Block Diagram

Product Description

PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM applications. This PLL Clock Buffer is designed for 2.5 V

DDQ

and

2.5V AVDD operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to five differential pairs of clock outputs (Y[0:4], Y[0:4]) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the Analog Power input (AVDD). When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes.

When the input frequency falls below a suggested detection frequency that is below the operating frequency of the PLL, the device will enter a low power mode. In low power mode, PLL is turned OFF, Y[0:4] and Y[0:4] outputs are 3-stated.

The PI6CV855 is able to track Spread Spectrum Clocking to reduce EMI.

Pin Configuration

CLK CLK

FBIN FBIN

AV

28

Y4

27

Y4 V

26 25 24 23

L

22 21 20 19 18 17 16 15

DDQ

GND FBOUT FBOUT

V

DDQ

FBIN FBIN GND

V

DDQ

Y3 Y3 GND

Y0 Y0

DD

Y1 Y1

Y2 Y2

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28-Pin

Y0 Y0

Y1 Y1

PLL

Logic

and

DD

Test Ciruit

Y2 Y2

Y3 Y3

Y4 Y4

GND

V

DDQ

CLK CLK

AV

AGND

GND

V

DDQ

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Pinout Table

PI6CV855

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

niP

emaN

KLC KLC

.oNniP

5 6

]4:0[Y72,71,31,11,3

]4:0[Y82,61,41,01,2.stuptuokcolCtnemelpmoC

TUOBF TUOBF

NIBF NIBF

V

QDD

VA

DD

32 42

12 02

62,22,81,21,4

7

DNGA8

DNG52,91,51,9,1.snipO/IrofdnuorG

O/I

epyT

ItupnikcolCecnerefeR

O

ItupnikcabdeeFtnemelpmoCdna,tupnikcabdeeF

rewoP

dnuorG

noitpircseD

.stuptuokcolC

tuptuOkcabdeeFtnemelpmoCdna,tuptuokcabdeeF

.snipO/IrofylppuSrewoP

VA.ylppusrewoperoc/golanA

DD

VA

DD

nehW.sesoprupgnitsetrofLLPehtssapybotdesuebnac

.stuptuoecivedehtotyltceriddereffubsiKLC&dessapybsiLLP,dnuorgotdeppartssi

yrtiucriceroc/golanaehtrofecnereferdnuorgehtsedivorP.dnuorgeroc/golanA

Function Table

stupnIstuptuOetatSLLP

VA

DD

DNGLHZZZZ ffO/dessapyB

DNGHLZZZZ ffO/dessapyB

)mon(V5.2LHLHLHno

)mon(V5.2HLHLHLno

)mon(V5.2zHM02<ZZZZffo

Notes: For testing and power saving purposes, PI6CV855 will power down if the frequency of the reference inputs CLK, CLK is well below the operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CV855 will be powered down when the CLK,CLK stop running.

Z = High impedance X = Dont care

KLCKLC]4:0[Y]4:0[YTUOBFTUOBF

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Absolute Maximum Ratings (Over operating free-air temperature range)

lobmySretemaraP.niM.xaMstinU

PI6CV855

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

V

VA,

QDD

DD

V

I

V

O

egnaregatlovtupnI5.0

egnaregatlovtuptuO5.0

egnaregatlovylppuseroc/golanadnaegnaregatlovylppusO/I5.06.3

V

QDD

gtsTerutarepmetegarotS56051

Note: Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

Timing Requirements (Over recommended operating free-air temperature)

VA

lobmySnoitpircseD

f

KC

t

CD

t

BATS

V,

DD

QDD

.niM.xaM

)2,1(

ycneuqerfkcolcgnitarepO

)3(

ycneuqerfkcolcnoitacilppA

06071

59071

elcycytudkcolctupnI0406%

purewopretfaemitnoitazilibatsLLP001sµ

V2.0±V5.2=

V

5.0+

o

C

stinU

zHM

Notes:

1. The PLL is able to handle spread spectrum induced skew.

2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is

not required to meet the other timing parameters. (Used for low-speed debug).

3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.

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DC Specifications

Recommended Operating Conditions

lobmySretemaraP.niM.moN.xaMstinU

PI6CV855

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

VA

DD

V

QDD

V

HO

V

LO

V

XI

V

XO

V

NI

V

DI

V

DO

T

A

levelegatlovtupnI3.0V

TUOBFdna

Electrical Characteristics

retemaraPsnoitidnoCtseTA

egatlovylppuseroc/golanA3.25.27.2

egatlovylppustuptuO3.25.27.2

egatlovtuptuolevel-hgiH8.1V

QDD

egatlovtuptuolevel-woL05.0

egatlovgnissorcriap-laitnereffidtupnIV(

tupnikcolcMARDSehttaegatlovgnissorcriap-laitnereffidtuptuOV(

KLCdnaKLCneewtebegatlovlaitnereffidtupnI63.0V

TUOBFdna]n[Ydna]n[YneewtebegatlovlaitnereffidtuptuO

QDD

2.0)2/V(

7.0V

QDD

3.0+

QDD

6.0+

QDD

6.0+

QDD

V

2.0+)2/

erutarepmetriaeerfgnitarepO007C°

V,

DDV

QDD

.niM.pyT.xaMstinU

V

KI

I

QDD

stupnillAI

NIBF,KLCV

VfotnerrucylppuscimanyD

I

V

QDD

Am81=V3.22.1V

V=

QDD

V7.2=

DD

DNGroV7.201±Aµ

)1(

tnerrucylppuscitatSzHM02<KLC&KLC001Aµ

VAfotnerrucylppuscimanyD

I

DDA

V

DD

)1(

V7.2=

tnerrucylppuscitatSzHM02<KLC&KLC001Aµ

KLCdnaKLC

C

I

V

V=

I

DD

DNGroV5.20.20.3Fp

NIBFdnaNIBF

Notes:

1. Driving 9 or 18 DDR SDRAM memory chips with 120-ohm termination resistor for each clock output pair at 134 MHz.

2. The maximum power down clock frequency is below 20 MHz.

003Am

21Am

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AC Specifications

Switching characteristics over recommended operating free-air temperature range, f (See Figure 1 and 2)

retemaraPnoitpircseDmargaiD

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

> 100 MHz (unless otherwise noted).

CLK

VA

V,

CC

QDD

.niM.moNxaM

V2.0±V5.2=

PI6CV855

stinU

(t θ)tesffoesahpcitatS

)1(

4erugiF05005

)cc(tijtrettijelcyc-ot-elcyC3erugiF5757

)rep(tijtrettijdoireP6erugiF5757

)reph(tijtrettijdoirep-flaH7erugiF001001

)i(lstetarwelskcolctupnI

)o(lstetarwelskcolctuptuO

)2(

8erugiF0.10.2

)o(kstwekskcolctuptuO5erugiF001sp

ycneuqerfnoitaludomCSS0.030.05zHk

noitaivedycneuqerftupnikcolcCSS00.005.0%

htdiwdnabpoolLLP2zHM

elgnaesahP 130.0seerged

Notes:

1. Static Phase offset does not include jitter.

2. The slew rate is determined from the IBIS model with test load shown in Figure 1.

3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.

sp

sn/V

)3(

.

sretemarapgniwollofehthtiwsrezisehtnysCSSgnitroppuselihwsretemarapevobaehtllasteem558VC6IPehtnoLLPehT

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V

PI6CV855

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

DD

V

DDQ

Z = 60Ω

DDR

SDRAM

Z = 60Ω

R =120Ω

DDR

SDRAM

Figure 1. IBIS Model Output Load

/2

Z = 60Ω

R =10Ω

Z = 50Ω

C=14pF

R = 50Ω

SCOPE

–V

DDQ

–V

/2

DDQ

Z = 60Ω

C=14pF

–V

/2

DDQ

/2

R =10Ω

Z = 50Ω

Figure 2. Output Load Test Circuit

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Yx,FBOUT

PI6CV855

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

CLK

FBIN

t

cycle n

=

t

jit(cc)

Figure 3. Cycle-to-Cycle Jitter

t

( )

n

t

cycle n

-

t

cycle n+1

n=N

∑

=

t

( ) n

1

N

t

cycle n+1

t

( )

n+1

(N is a large number of samples)

Figure 4. Static Phase Offset

Yx

Yx, FBOUT

t

sk(o)

Figure 5. Output Skew

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Yx, FBOUT

t

jit(per)

t

cycle n

=

t

1 f

O

cycle n

PI6CV855

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

1 f

O

Yx, FBOUT

Figure 6. Period Jitter

t

half period n

=

t

jit(hper)

t

Figure 7. Half-Period Jitter

80%

1 f

O

half period n

t

n+1

half period

1

2*f

O

80%

V

DDQ

Clock Inputs and Outputs

20%

t

sl(i), tsl(o)

t

sl(i), tsl(o)

20%

0V

Figure 8. Input and Output Slew Rates

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Packaging Mechanical: 28-Pin TSSOP (L)

28

.169 .177

1

.378 .386

9.6

9.8

.047

1.20

Max

4.3

4.5

SEATING PLANE

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

0.45

.018

0.75

.030

.252 BSC

6.4

DENOTES CONTROLLING

X.XX

DIMENSIONS IN MILLIMETERS

X.XX

.004 .008

PI6CV855

0.09

0.20

.0256

BSC

0.65

Ordering Information

edoCgniredrOemaNegakcaPepyTegakcaP

L558VC6IP82LPOSSTediwmm4.4,nip-82

.007 .012

0.19

0.30

.002 .006

0.05

0.15

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com

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Datasheet PI6CV855L Datasheet (PERICOM)

Specifications and Main Features

Frequently Asked Questions

User Manual