Page 1
177
PS8096B 01/25/99
234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901
2
PI6C9930
3.3V Zero-Delay Clock Buffer
Product Description
The PI6C9930 Clock Buffer offers zero-delay, low-skew system
clock distribution. These multiple output clock drivers optimize the
timing of high-performance computer systems. Each of eight
individual drivers can drive series-terminated transmission lines
with impedances as low as 50Ω while delivering minimal output
skews and full-swing logic levels.
Connecting Q0 to FB provides REF/2 outputs on Q1-Q7. Connecting
any of Q1 - Q7 output to FB produces six copies of the REF input
plus one REF x 2 on Q0.
Test Mode
In normal system operation, this pin is connected to ground. For
testing purposes, the TEST pin can have a removable jumper to
ground, or be tied LOW through a 100Ω resistor. This will allow drive
by an external tester. If the TEST input is forced HIGH, the device
will operate with its internal phase-locked loop disconnected, and
input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal mode.
Block Diagram
Features
• Near zero input to output delay
• Seven copies of the REF/2 or
Six copies of REF plus one REF × 2
• 25 100 MHz output
• 50% duty cycle
• Low skew
• Low jitter (<250ps cycle-to-cycle)
• Low noise balanced drive outputs
• V
CC
= 3.3V ±0.3V, TA = 0° to 70°
• 24-pin 209 mil wide SSOP (H)
• 24-pin 150 mil wide QSOP (Q)
• 24-pin 300 mil wide SOIC (S)
Applications
• PCI 66 MHz or 33 MHz systems
Pinout
24-Pin
H, Q, S
Page 2
PI6C9930
3.3V Zero-Delay Clock Buffer
178
PS8096B 01/25/99
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Pin Description
egnaRerutarepmeTtneibmAV
CC
laicremmoCC°07+otC°0V3.0±V3.3
Operating Range
emaNniPO/InoitpircseDlanoitcnuF
FERI
dnaycneuqerfehtseilppustupnisihT.tupnIycneuqerFecnerefeR
derusaemsinoitairavlanoitcnufllahcihwtsniagagnimit
BFI )stuptuothgiefoenootdetcennocyllacipyt(tupnikcabdeefLLP
SFI pu-lluPlanretnI.tcelesegnarycneuqerflevel-owT
TSETI pu-lluPlanretnI.noitcesedoMtseTeeS.tceleslevel-owT
Q
O
Oredividon,tuptuOkcolC
7Q-1QO 2ybedividlanretnihtiwstuptuokcolC
V
NCC
RWPsrevirdtuptuorofylppusrewoP
V
QCC
RWPyrtiucriclanretnirofylppusrewoP
DNGRWPdnuorG
CNnoitcennoCoN
Storage Temperature ............................................................65°C to +150°C
Ambient Temperature with Power Applied ......................... 55°C to +125°C
Supply Voltage to Ground Potential ...................................... 0.5V to +7.0V
DC Input Voltage ................................................................... 0.5V to +7.0V
Output Current into Outputs (LOW) ...................................................... 64mA
Page 3
PI6C9930
3.3V Zero-Delay Clock Buffer
179
PS8096B 01/25/99
Electrical Characteristics Over Operating Range
lobmySsretemaraPsnoitidnoCtseT.niM.xaMstinU
V
HO
egatloVHGIHtuptuOV
CC
I,.niM=
HO
Am42-=4.2
V
V
LO
egatloVWOLtuptuOV
CC
I,.niM=
LO
Am42+=4.0
V
HI
egatloVHGIHtupnI
)ylnostupniBFdnaFER(
0.2V
CC
V
LI
egatloVWOLtupnI
)ylnostupniBFdnaFER(
5.0-8.0
I
HI
tnerruCegakaeLHGIHtupnI
)ylnostupniBFdna,SF,tseT,FER(
V
CC
V,.xaM=
NI
.xaM=01
mA
I
LI
tnerruCegakaeLWOLtupnI
)ylnostupniBFdna,SF,tseT,FER(
V
CC
V,.xaM=
NI
V4.0=005-
I
SO
tnerruCtiucriCtrohStuptuO
)2(
V
CC
V,.xaM=
TUO
)ylnoC°52(DNG=052-
Am
I
QCC
tnerruCgnitarepO
yrtiucriClanretnIybdesU
V
NCC
V=
QCC
,.xaM=
nepOtceleSstupnIllA
58
I
NCC
riaPtuptuOreptnerruCreffuBtuptuO
)3(
V
NCC
V=
QCC
I,.xaM=
TUO
Am0=
xamf,nepOstceleSstupnI
41
DPriaPtuptuOrepnoitapissiDrewoP
)4(
V
NCC
V=
QCC
I,.xaM=
TUO
Am0=
f,nepOstceleSstupnI
XAM
87Wm
Notes:
1. If these inputs, which are normally wired to VCC, GND, are switched, the function
and timing of the outputs may glitch and the PLL may require an additional t
LOCK
time before all datasheet limits are achieved.
2. Tested one output at a time, output shorted for less than one second, less than l0% duty
cycle. Room temperature only.
3. (TBD) Total output current per output pair is approximated by the following expression that
includes device current plus load current.
I
CCN
= [(4 + 0.11F) + [((835 - 3F)/Z) + (.0022FC)]N1] x 1.1
Where: F = frequency in MHz
Z = line impedance in ohms
C = capacitive load in pF
FC = F × C
N = number of loaded outputs: 0, l, or 2
4. (TBD) Total power dissipation per output pair can be approximated by the following expression that
includes device power dissipation plus power dissipation due to the load circuit:
PD = [(22 + 0.61F) + [((1550 - 2.7F)/Z) + (0.125FC)]N] × 1.1 (See note 3 for variable definition)
5. TBD
6. Applies to REF and FB inputs only. Tested initially and after any design or process
changes that may affect these parameters.
Page 4
PI6C9930
3.3V Zero-Delay Clock Buffer
180
PS8096B 01/25/99
3.3V
R1
R2
C
L
R1 = 100Ω
R2 = 100Ω
C
L
= 20pF
(Includes fixture and
probe capacitance)
AC Test Load and Waveform
AC Timing Diagram
AC Test Load
3.3 Volt Clock
0.4Vcc
Clock Waveforms
0.5Vcc
0.3Vcc
0.5Vcc
0.3Vcc
T_high
T_cyc
0.3Vcc
0.4Vcc
T_low
0.4Vcc
p-to-p
(minimum)
0.6Vcc
0.2Vcc
Capacitance
(1,6)
(TA = 25°C, f = 1 MHz, VIN = 0V, V
OUT
= 0V)
retemaraPnoitpircseDsnoitidnoCtseT.xaMstinU
C
NI
ecnaticapaCtupnITAV,zHM1=f,C52=
CC
V3.3=01Fp
Clock Waveforms
Page 5
PI6C9930
3.3V Zero-Delay Clock Buffer
181
PS8096B 01/25/99
Switching Characteristics Over Operating Range
(14)
(Commercial: TA = 0°C to 70°C, VCC = 3.3V ± 10%)
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
lobmySnoitpircseD.niM.pyT.xaMstinU
f
MON
kcolCnoitarepO
zHMniycneuqerF
WOL=SF5205
zHM
gnitaolFroHGIH=SF05001
t
HWPR
HGIHhtdiWesluPFER0.5
sn
t
LWPR
WOLhtdiWesluPFER0.5
t
WEKS
)stuptuOllA(wekStuptuOoreZ
)8,7(
3.06.0
t
VED
wekSeciveD-ot-eciveD
)01,9(
2.1
t
DP
esiRBFotesiRFER,yalednoitagaporP5.0-0.05.0+
t
CYC
zHM66@cepStegraT,elcyCytuDtuptuO540555%
s
ETAR
etaRwelS
)21,11(
15.14 sn/V
t
KCOL
emiTkcoLLLP
)31(
5.0sm
t
RJ
rettiJtuptuOelcyC-ot-elcyC523sp
Notes:
7. Skew is defined as the time between the earliest and the latest output transition among all
outputs with AC Test Load.
8. t
SKEW
is defined as the skew between outputs.
9. t
DEV
is the output-to-output skew between any two outputs on separate devices operating
under the same conditions (VCC, ambient temperature, air flow, etc.).
10. Tested initially and after any design or process changes that may affect these parameters.
11. Specified with outputs loaded without 20pF in AC Test Load.
12. Slew Rate (s
RATE
) measured between 0.3VCC and 0.5VCC (0.99V and 1.65V).
13. t
LOCK
is the time that is required before synchronization is achieved. This specification is
valid only after V
CC
is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until tPD is within specified
limits.
14. Test measurement levels for the PI6C9930 are PCI levels (0.4VCC to 0.4VCC). Test
conditions assume signal transition times of 2ns or less and output loading as shown in the
AC Test Loads and Waveforms unless otherwise specified.
N/PnoitpircseD
H0399C6IPegakcaPPOSSnip42
Q0399C6IPegakcaPPOSQnip42
S0399C6IPegakcaPCIOSnip42
Ordering Information
Loading...