Datasheet PI6C9911J, PI6C9911-2J, PI6C9911-5IJ, PI6C9911-5J, PI6C9911E-2J Datasheet (PERICOM)

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

2

PI6C9911 & PI6C9911E

5V High-Speed Programmable Skew

Clock Buffers - SuperClock







Product Features

• Four pairs of programmable skew outputs

• User-selectable output functions:

− Selectable skews

− Inverted and noninverted

− Operation at ½ and ¼ input frequency

− Operation at 2X and 4X input frequency

• Low skew <100ps typical same pair, 250ps max.

• Allow REF clock input to have Spread Spectrum

modulation for EMI reduction

• 2X, 4X, ½ and ¼ outputs

• 3-level inputs for skew and output frequency control

• External feedback, internal loop filter

• Low cycle-to-cycle Jitter: <25ps RMS

• Duty cycle of output clock signals: 45% min. 55% max.

• Same pinout as Cypress CY7B9911

• Available in 32-pin PLCC Package (J)

• Output Operation

3.75 to 100 MHz for PI6C9911

3.75 to 125 MHz for PI6C9911E

Description

The PI6C9911 and PI6C9911E are low-skew, low jitter, 5V phase­lock-loop (PLL) programmable skew clock drivers, for
high-performance computing and networking applications. These
parts offer user-selectable skew-control of 4 output pairs, provid­ing the timing delays necessary to optimize high-performance
clock-distribution circuits.

Each output can be hardwired to one of nine delay or function
configurations. Delay increments are determined by the input clock
frequency and the configurations selected by the user.

The PI6C9911 and PI6C9911E allow the REF clock input to have
Spread Spectrum modulation for EMI reduction.

Both buffers are pin-compatable with Cypresss RoboClock
CY7B9911, but with improved AC/DC characteristics.

The PI6C9911 and PI6C9911E also have the same pinout as
Cypresss CY7B9911and with balanced output drive.

Logic Block Diagram

TEST

Phase

FB

REF

Three Level

Select Inputs

Freq

Det

Filter

FS

4F0
4F1

3F0
3F1

2F0
2F1

1F0
1F1

Vco and

Time Unit

Generator

SKEW

SELECT

MATRIX

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

Pin Configuration

3F1
4F0

4F1
VCCQ
VCCN

4Q1

4Q0
GND
GND

1

3F0FSVCCQ

4 3 2 1 32 31 30

5
6
7
8
9
10
11
12
13

14 15 16 17 18 19 20

3Q1

3Q0

REF

GND

32-Pin

J

VCCNFBVCCN

TEST

2Q1

2F1

2F0

29

GND

28

1F1

27

1F0

26

VCCN

25

1Q0

24

1Q1

23

GND

22

GND

21

2Q0

PS8451B 03/28/01

2

PI6C9911 & PI6C9911E

5V High Speed Programmable Skew

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

Clock Buffers - SuperClock

Pin Definitions

emaNlangiSO/InoitpircseD







FER

BF .)stuptuothgieehtfoenootdetcennocyllacipyt(tupnikcabdeefLLP

SF.tcelesegnarycneuqerflevel-eerhT

1F1,0F1 .)1Q1,0Q1(1riaptuptuorofstupnitcelesnoitcnuflevel-eerhT

I

1F2,0F2 .)1Q2,0Q2(2riaptuptuorofstupnitcelesnoitcnuflevel-eerhT

1F3,0F3 .)1Q3,0Q3(3riaptuptuorofstupnitcelesnoitcnuflevel-eerhT

1F4,0F4 .)1Q4,0Q4(4riaptuptuorofstupnitcelesnoitcnuflevel-eerhT

TSET .snoitpircsedmargaidkcolbehtrednunoitcesedomtseteeS.tceleslevel-eerhT

1Q1,0Q1

1Q2,0Q2.2riaptuptuO

O

1Q3,0Q3.3riaptuptuO

1Q4,0Q4.4riaptuptuO

V

NCC

V

QCC

RWP

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.derusaemsinoitairavlanoitcnuf

1elbaTeeS

.

2elbaTeeS

.

2elbaTeeS

.

2elbaTeeS

.

2elbaTeeS

.

2elbaTeeS

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.

2elbaTeeS

.

2elbaTeeS

.

2elbaTeeS

.

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DNGdnuorG

Block Diagram Description

Phase Frequency Detector and Filter

These two blocks accept input signals from the reference frequency
(REF) input and the feedback (FB) input and generate correction
information to control the frequency of the Voltage-Controlled
Oscillator (VCO). These blocks, along with the VCO, form a Phase­Locked Loop (PLL) that tracks the incoming REF signal.

VCO and Time Unit Generator

The VCO accepts analog control inputs from the PLL filter block
and generates a frequency that is used by the time unit generator to
create discrete time units that are selected in the skew mix matrix.
The operational range of the VCO is determined by the FS control
pin. The time unit (tU) is determined by the operating frequency of
the device and the level of the FS pin as shown in Table 1.

Skew Select Matrix

The skew select matrix is comprised of four independent sections.
Each section has two low-skew, high-fanout drivers (xQ0, xQ1),
and two corresponding three-level function select (xF0, xF1)
inputs. Table 2 shows the nine possible output functions for each
section as determined by the function select inputs. All times are
measured with respect to the REF input assuming that the output
connected to the FB input has 0tU selected.

2

PS8451B 03/28/01

2

PI6C9911 & PI6C9911E

5V High Speed Programmable Skew

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

Clock Buffers - SuperClock







Table 1. Frequency Range Select and tU Calculation

f

)3,2(

SF

.niM.xaM

WOL5103447.22

1199C6IP

DIM5205625.83

HGIH04001615.26

WOL0204447.22

E1199C6IP

DIM5307625.83

HGIH06521615.26

)zHM(

MON

tU =

f

NOM

1

x N

where N=

(1)

Table 2. Programmable Skew Configurations

etamixorppA

stceleSnoitcnuFsnoitcnuFtuptuO

(1)

ycneuqerF

ta)zHM(

hcihw

t

U

sn0.1=

,1F2,1F1

1F4,1F3

WOL

DIM

HGIH

,0F2,0F1

0F4,0F3

WOLt4-

DIMt3-

HGIHt2-

WOLt1-

,1Q1,0Q1

1Q2,0Q2

U

U

U

U

DIMt0-

HGIHt1+

WOLt2+

DIMt3+

HGIHt4+

U

U

U

U

1Q3,0Q3

,0Q4

1Q4

2ybediviD

t6-

U

t4-

U

t2-

U

U

t2+

U

t4+

U

t6+

U

4ybediviDdetrevnI

FB Input

1Fx

3Fx

2Fx

(N/A) LM -6t

LL LH -4t

LM (N/A) -3t

LH ML -2t

ML (N/A) -1t

MM MM 0t

MH (N/A) +1t

HL MH +2t

HM (N/A) +3t

HH HL +4t

(N/A) HM +6t
(N/A) LL/HH DIVIDED

(N/A) HH INVERT

REF Input

4Fx

U

U

U

U

U

U

U

U

U

U

U

-6t
t

U

U

U

U

U

U

U

U

U

U

-5t

-4t

0

0

t

-3t

0

0

t

t

-2t
t

U

-1t

0

0

t

t0t

+1t

0

+2t

0

t

+3t

0

t

+4t

0

t

+5t

0

t

U

+6t

0

t

Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output

3

(4)

PS8451B 03/28/01

2

PI6C9911 & PI6C9911E

5V High Speed Programmable Skew

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

Clock Buffers - SuperClock







Test Mode

The TEST input is a three-level input. In normal system operation,

Maximum Ratings

(Above which the useful life may be impaired)
this pin is connected to ground, allowing the PI6C9911 to
operate as explained briefly above (for testing purposes, any of the
three-level inputs can have a removable jumper to ground, or be
tied LOW through a 100 ohm resistor. This will allow an external
tester to change the state of these pins).

If the TEST input is forced to its MID or HIGH state, the device will
operate with its internal phase locked loop disconnected, and in­put levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal mode.

In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function

Storage Temperature ............................................65ºC to +150ºC

Ambient Temperature

with Power Applied ..............................................55ºC to +125ºC

Supply Voltage to Ground Potential ....................... 0.5V to +7.0V

DC Input Voltage .................................................... 0.5V to +7.0V

Output Current into Outputs (LOW) ...................................64mA

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ................................. >2001V

Latch-Up Current ............................................................ >200mA

select inputs (xF0 and xF1) and the waveform characteristics of the
REF input.

Operating Range

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laicremmoCCº07+otCº0

lairtsudnICº58+otCº04

Notes for Tables on Pages 3 through 7:

1. For all three-state inputs, HIGH indicates a connection to V

, LOW indicates a connections to GND, and MID indicates an open

CC

connection. Internal termination circuitry holds an unconnected input to VCC/2.

2. The level to be set on FS is determined by the normal operating frequency (f

Logic Block Diagram). Nominal frequency (f

) always appears at 1Q0 and the other outputs when they are operated in their

NOM

undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be f
undivided.The frequency of REF and FB inputs will be f

NOM

/2 or f

/4 when the part is configured for a frequency multiplication

NOM

) of the VCO and the Time Unit Generator (see

NOM

when the output connected to FB is

NOM

by using a divided output as the FB input.

3. When the FS pin is selected HIGH, the REF input must not transition upon power-up untill VCC has reached 4.3V.

4. FB connected to an output selected for zero skew (ie., xF1 = xF0 = MID).

6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshhold voltages vary as a percentage of VCC). Internal

termination resistors hols unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may
glitch and the PLL may require an additional t

time before all datasheet limits are achieved.

LOCK

10. Test measurement levels are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less and output

loading as shown in the AC Test Loads and Waveforms unless specified.

11. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.

12. Skew is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has

been selected when all are loaded with 30pF and terminated with 50Ω to 2.06V.

13. t

14. t

is defined as the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.

SKEWPR

is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.

SKEW0

15. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided

(3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).

16. t

17. t

is the output-to-output skew between any 2 devices operating under the same conditions (VCC ambient temperature, air flow, etc.).

DEV

is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t

ODCV

specifications.

18. Specified with outputs loaded with 30pF. Devices are terminated through 50Ω to 2.06V.

19. t

20. t

21. t

is measured at 2.0V. t

PWH

and t

ORISE

is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within

LOCK

measured between 0.8V and 2.0V.

OFALL

is measured at 0.8V

PWL

normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within
specified limits.

CC

%01±V5

SKEW2

and t

SKEW4

4

PS8451B 03/28/01

2

PI6C9911 & PI6C9911E

5V High Speed Programmable Skew

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

Clock Buffers - SuperClock

DC Characteristics Over the Operating Range

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CC

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Capacitance at REF and FB

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C

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CC

AC Test Loads and Waveforms (PI6C9911)

5V

R1

C

L

R2

TTL AC Test Load

R1 = 130
R2=91
CL= 30pF

(Includes fixture

and probe capacitance)

Ω

Ω

(16)

2.0V

Vth= 1.5V

0.8V

0.0V

≤

1ns

TTL Input Test Waveform

3.0V

2.0V
Vth= 1.5V

0.8V

≤

1ns

41

5

PS8451B 03/28/01

2

PI6C9911 & PI6C9911E

5V High Speed Programmable Skew

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

Clock Buffers - SuperClock







Switching Characteristics over the Operating Range

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kcolcgnitarepO

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MON

niycneuqerF

zHM

t

HWPR

t

LWPR

t

U

t

RPWEKS

t

0WEKS

t

1WEKS

t

2WEKS

t

3WEKS

)31,21(

)1Qx,0Qx(

)stuptuOssalCemaS

WOL=SF

)2,1(

)3,2,1(

HGIH=SF

HGIHhtdiWesluPFER

WOLhtdiWesluPFER

tinUwekSelbammargorP 1elbaTeeS

wekSriaP-dehctaMtuptuOoreZ

)41,21(

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)51,21(

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)51,21(

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)51,21(

)stuptuOssalCtnereffiD

.niM.pyT.xaM.niM.pyT.xaM.niM.pyT.xaM

510351035103
520552055205
040010400104001

0.40.40.4sn

(2,10,11)

2-1199C6IP5-1199C6IP1199C6IP

stinU

zHMDIM=SF

50.002.01.052.01.052.0

01.052.052.05.03.057.0

52.05.06.07.06.00.1

03.05.005.02.10.15.1

52.05.005.09.07.02.1

t

4WEKS

t

VED

t

DP

t

VCDO

t

HWP

t

LWP

t

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t

LLAFO

t

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sp

002002002

6

PS8451B 03/28/01

2

PI6C9911 & PI6C9911E

5V High Speed Programmable Skew

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

Clock Buffers - SuperClock







Switching Characteristics over the Operating Range

retemaraPnoitpircseD

)2,1(

kcolcgnitarepO

F

MON

niycneuqerF

zHM

t

HWPR

t

LWPR

t

U

t

RPWEKS

t

0WEKS

t

1WEKS

t

2WEKS

t

3WEKS

t

4WEKS

t

VED

t

DP

t

VCDO

esiRBFot

)31,21(

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020402040204
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01.052.052.05.03.057.0

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03.05.005.02.10.15.1

52.05.005.09.07.02.1

05.09.005.02.12.17.1
sn

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t

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002002002

PS8451B 03/28/01

2

PI6C9911 & PI6C9911E

5V High Speed Programmable Skew

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

Clock Buffers - SuperClock

AC Timing Diagrams

t

REF

t

RPWL

REF

t

RPWH







FB

OTHER Q

INVERTED Q

REF DIVIDED BY 2

t

PD

t

ODCV

t

ODCV

t

JR

Q

t

SKEWPR,

t

SKEW0,1

t

SKEW3,4

t

SKEW3,4

t

SKEWPR,

t

SKEW0,1

t

SKEW2

t

SKEW3,4

t

SKEW2

t

SKEW3,4

t

SKEW2,4

REF DIVIDED BY 4

8

PS8451B 03/28/01

2

PI6C9911 & PI6C9911E

5V High Speed Programmable Skew

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

Clock Buffers - SuperClock

Package Diagram 32-Pin PLCC (J)

1.27

.045

1.143

Typ.

.050

BSC







.585
.595

14.859

15.113

.100
.140

2.450

3.556

Pin 1

.447
.453

11.354

11.506
.485

.495

12.319

12.573

.390
.430

.013
.021

9.906

10.922

.547
.553

13.894

14.046

0.331

0.533

.015

0.381
Min.

.065
.095

1.524

2.413

.045 Typ.

1.143

.026
.032

0.661

0.812

.025

0.635 Typ.

DENOTES DIMENSIONS

X.XX

IN MILLIMETERS

X.XX

.490
.530

12.446

13.462

Ordering Information

rebmuNtraPycaruccAegakcaPerutarepmeTgnitarepO

J2-1199C6IP
J5-1199C6IP

J1199C6IP

JI5-1199C6IP

JI1199C6IP

J2-E1199C6IP
J5-E1199C6IP

JE1199C6IP

JI5-E1199C6IP

JIE1199C6IP

2380 Bering Drive  San Jose, CA 95131  1-800-435-2336  Fax [phone]  http://www.pericom.com

sp052
sp005
sp057

sp005
sp057

CCLPniP-23

sp052
sp005
sp057

sp005
sp057

Pericom Semiconductor Corporation

9

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lairtsudnI

laicremmoC

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PS8451B 03/28/01