Datasheet PI6C9910-5H, PI6C9910-5S, PI6C9910AH, PI6C9910AS Datasheet (PERICOM)

108

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PI6C9910

Zero-Delay Clock Buffer

Block Diagram

Features

 Zero input to output delay  Eight clock copies from one clock input  15 - 80 MHz output operation  Fifty percent duty cycle  Low skew (< 250ps typ.) VCC = 5.0V +/- 10%, TA = 0° to 70°  Low jitter (< 250 ps cycle to cycle), < 60ps RMS  Low noise unbalanced drive outputs (PI6C9910-5)  Low noise balanced drive outputs (PI6C9910A)  Packages available:

 24-pin 300 mil wide SOIC (S)  24-pin 209 mil wide SSOP (H)

 Compatible with Cypress CY7B9910-5

Test Mode

In normal operation the TEST pin is tied to ground. For testing purposes it can have a removable jumper to ground or a 100Ω pull-down resistor. When the TEST pin is driven HIGH, the VCO output is disconnected, and all eight outputs (Q0-Q7) are directly driven from the REF input.

Pinout

Description

The PI6C9910 is a low-skew clock driver designed to simplify clock distribution in systems requiring near synchronous clocks. A typical application is in SDRAM modules. Each of the eight outputs (Q0-Q7) can drive individual 50Ω transmission lines with minimal distortion or skew, and full 5V swing.

An on-chip phase-locked loop (PLL) synchronizes the feedback (FB) to the reference (REF) input, achieving zero-delay buffered outputs.

Inserting an external counter between any of the Qx outputs and the FB pin allows for generation of eight synchronous clock copies whose frequency is a multiple of a lower frequency REF input.

The voltage-controlled oscillator (VCO) frequency is determined by the filtered ouput coming from the Phase/Frequency Detector. The frequency select (FS) input sets the VCO operating range.

PI6C9910-5 has unbalanced output drivers (TTL), and is fully compatible with the Cypress CY7B9910-5. The PI6C9910A features balanced-drive outputs (CMOS) for improved rise/fall time symmetry.

The FS and TEST inputs have internal pull-up resistors.

REF

V

CCQ

FS

NC

V

CCQ

V

CCN

Q0 Q1

GND

Q2 Q3

V

CCN

GND TEST NC GND V

CCN

Q7 Q6 GND Q5 Q4 V

CCN

FB

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

24-Pin

S, H

Voltage Controlled Oscillator

Filter

Phase

Freq.

Det

FB

TEST

REF

FS

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

PI6C9910

Zero-Delay Clock Buffer

109

PS8341B 03/05/99

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Storage Temperature................................................. 65°C to +150°C

Ambient Temperature with Power Applied .............. 55°C to +125°C

Supply Voltage to Ground Potential ............................ 0.5V to +7.0V

DC Input Voltage......................................................... 0.5V to +7.0V

Output Current into Outputs (LOW) ...........................................64mA

Static Discharge Voltage (per MIL-STD-883, Method 3015) >2001V

Latch-Up Current .................................................................... >200mA

Note:

Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Pin Description

Operating Range

egnaRerutarepmeTtneibmAV

CC

laicremmoC0° 07+otC °C%01±V5

emaNniPO/InoitpircseDlanoitcnuF

FERI ycneuqerfehtseilppustupnisihT.tupnIycneuqerFecnerefeR

.derusaemsinoitairavlanoitcnufllahcihwtsniagagnimitdna

BFI thgiefoenootdetcennocyllacipyt(tupnikcabdeefLLP

.)stuptuo

SFI -lluPlanretnI.1elbaTeeS.tcelesegnarycneuqerflevel-owT

.pu

TSETI pu-lluPlanretnI.noitceSedoMtseTeeS.tceleslevel-owT

]7-0[QO .stuptuOkcolC

V

CCN

RWP.srevirdtuptuorofylppusrewoP

V

CCQ

RWP.yrtiucriclanretnirofylppusrewoP

DNGRWP.dnuorG

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

PI6C9910

Zero-Delay Clock Buffer

110

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Electrical Characteristics Over Operating Range

(1)

Notes:

1. These inputs are normally wired to VCC, GND. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t

LOCK

time betore all datasheet limits are achieved.

2. Tested one output at a time, output shorted for less than one second, less than l0% duty cycle. Room temperature only.

Capacitance (TA = 25°C, f = 1 MHz)

lobmySretemaraPsnoitidnoCtseT.niM.xaMstinU

V

OH

)5-0199C6IP(egatloVHGIHtuptuOV

CC

I,.niM=

OH

Am61-=

4.2



V

OL

)5-0199C6IP(egatloVWOLtuptuOV

CC

I,.niM=

OL

Am64=



54.0

V

OH

)A0199C6IP(egatloVHGIHtuptuOV

CC

I,.niM=

OH

Am42-=

4.2



V

OL

)A0199C6IP(egatloVWOLtuptuOV

CC

I,.niM=

OL

Am42=



04.0

I

IH

tnerruCegakaeLHGlHtupnI

)ylnostupniBFdna,SF,tseT,FER(

V

CC

V,.xaM=

IN

.xaM=



01

µA

I

IL

tnerruCegakaeLWOLtupnI

)ylnostupniBFdnaFER(

V

CC

V,.xaM=

IN

V4.0=

− 01 

tnerruCegakaeLWOLtupnI

)ylnostupniSFdnatseT(

005-



I

OS

tnerruCtiucriCtrohStuptuO

)2(

V

CC

V,.xaM=

OUT

52(DNG= ° )ylnoC

−052

Am

I

CCQ

tnerruCgnitarepO

yrtiucriClanretnIybdesU

V

CCNV=CCQ

,.xaM= nepOstceleSstupnIllA



58

I

CCN

tnerruCreffuBtuptuO

riaPtuptuOrep

V

CCNV=CCQ

,.xaM=

I

OUT

Am0=

f,nepOstceleSstupnI

MAX



41

DP

noitapissiDrewoP

riaPtuptuOrep

V

CCNV=CCQ

,.xaM=

I

OUT

Am0=

f,nepOstceleSstupnI

MAX



87Wm

retemaraP

noitpircseDsnoitidnoCtseT

.xaMstinU

C

IN

ecnaticapaCtupnI

BFdnaFER

T

A

V,zHM1=f,C52=

CC

V0.5=01Fp

PI6C9910

Zero-Delay Clock Buffer

111

PS8341B 03/05/99

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Unbalanced Output Drive AC Test Load and Waveform

AC Timing Diagram

TTL AC Test Load

TTL Input Test Waveform

2.0V

Vth = 1.5V

0.8V

0.0V

2.0V Vth = 1.5V

0.8V

≤1 ns

Table 1. Frequency Range Select

3.0V

5V

R1

R2

C

L

R1 = 130Ω R2 = 91Ω C

L

= 30pF

(Includes fixture and probe capacitance)

SF

f

NOM

)zHM(

muminiMmumixaM

WOL5153

HGIH5208

t

PD

t

RPWH

t

REF

t

RPWL

t

ODCV

t

SKEW

t

SKEW

t

JR

t

ODCV

OTHER Q

Q

FB

REF

PI6C9910

Zero-Delay Clock Buffer

112

PS8341B 03/05/99

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Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com

Switching Characteristics Over Operating Range

(1)

Notes:

1. Test measurement levels for the PI6C9910-5 are TTL levels (1.5V to 1.5V).

Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.

2. Skew is defined as the time between the earliest and the latest output transition

among all outputs with AC Test Load.

3. t

SKEW

is defined as the skew between outputs.

4. t

DEV

is the output-to-output skew between any two outputs on separate devices

operating under the same conditions (VCC, ambient temperature, air flow, etc.).

5. Tested initially and after any design or process changes that may affect these

parameters.

6. t

ODCV

is the deviation of the output from a 50% duty cycle.

7. Specified with outputs loaded with AC Test Load (30pF).

8. t

ORISE

and t

OFALL

measured between 0.8V and 2.0V.

9. t

LOCK

is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.

lobmySnoitpircseD.niM.pyT.xaMstinU

f

NOM

kcolCnoitarepO

zHMniycneuqerF

WOL=SF51 53

zHM

HGIH=SF52 08

t

RPWH

HGIHhtdiwesluPFER0.5

sn

t

RPWL

WOLhtdiwesluPFER0.5

t

SKEW

)stuptuOllA(wekStuptuOoreZ

)3,2(

52.05.0

t

DEV

wekSeciveD-ot-eciveD

)5,4(

 0.1

t

PD

esiRBFotesiRFER,yaleDnoitagaporP5.0-0.05.0+

t

ODCV

noitairaVelcyCytuDtuptuO

)6(

0.1-0.00.1+

t

ORISE

emiTesiRtuptuO

)8,7(

51.00.15.1

t

OFALL

emiTllaFtuptuO

)8,7(

51.00.15.1

t

LOC K

emiTkcoLLLP

)9(

 5.0sm

t

JR

rettiJtuptuO

elcyC-ot-elcyC

)5(

 052

sp

SMR

)5(

 06

PI6C9910

Zero-Delay Clock Buffer

113

PS8341B 03/05/99

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SEATING PLANE

.050 BSC

1

0-8˚

.2914 .2992

X.XX X.XX

DENOTES DIMENSIONS IN MILLIMETERS

7.40

7.60

.5985 .6141

15.20

15.60

1.27

.0926 .1043

2.35

2.65

.394 .419

10.00

10.65

.0040 .0118

0.10

0.30

.013 .020

0.33

0.51

.010 .029

0.254

0.737

.0091 .0125

0.23

0.32

0.41

1.27

.016 .050

x 45˚

24

.021 .031

0.533

0.787

.311 .334

.078

.002

SEATING PLANE

.0098

Max.

.0256

BSC

.022 .037

.004 .009

.291 .322

1

24

.197 .220

0.25

X.XX X.XX

DENOTES DIMENSIONS IN MILLIMETERS

0.050

7.40

8.20

0.55

0.95

0.09

0.25

5.00

5.60

2.0

7.90

8.50

0.65

Max

Min

Package Mechanical Information

300-Mil 24-Pin SOIC

209-Mil 24-Pin SSOP

Ordering Information

rebmuNtraPegakcaP

SA0199C6IP42SegakcaPCIOSnip-42liM-003

HA0199C6IP42HegakcaPPOSSnip-42liM-902

S5-0199C6IP42SegakcaPCIOSnip-42liM-003 H5-0199C6IP42HegakcaPPOSSnip-42liM-902

Datasheet PI6C9910-5H, PI6C9910-5S, PI6C9910AH, PI6C9910AS Datasheet (PERICOM)

Specifications and Main Features

Frequently Asked Questions

User Manual