Datasheet PI6C2309-1HL, PI6C2309-1HLI, PI6C2309-1HW, PI6C2309-1HWI, PI6C2309-1L Datasheet (PERICOM)

1

PS8478 04/27/00

Product Features

• Zero input-output propagation delay

• Less than 200ps input to output propagation delay

• Multiple low-skew outputs
– Output-output skew less than 250ps
– Device-device skew less than 700ps
– Two banks of four outputs and one ON-chip
– Internal feedback connection

• 10 MHz to 100 MHz operating range

• Low Jitter <200ps

• 3.3V operation

• High drive option (PI6C2309-1H)

• Temperature Rating: Commercial & Industrial

• Space-saving 16-pin, 150-mil SOIC package (W16)
and 16-pin TSSOP package (L16)

Functional Description

Providing two banks of four outputs, the PI6C2309-1 is a 3.3V zero­delay buffer designed to distribute clock signals in applications
including PC, workstation, datacom, telecom, and high-performance
systems.

The PI6C2309-1 provides 9 copies of a clock signal that has less than
200ps propagation delay compared to the reference clock. The skew
among the output clock signals for PI6C2309-1 is less than 250ps.
When there are no rising edges on the REF input, the PI6C2309-1
enters a power-down state. In this mode, the PLL is off and all
outputs are three-stated. This results in less than 50µA of current
draw.

The PI6C2309-1 has two banks of four outputs and a CLK_OUT that
can be controlled by the select inputs (see table below). If all output
clocks are not required, Bank B can be three-stated. For test
purposes or if the internal PLL is not needed, it can be bypassed.

Block Diagrams

Pin Configuration PI6C2309-1

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

3.3V Zero-Delay Buffer

PI6C2309-1

2S1S]4-1[AKLC]4-1[BKLCTUO_KLCecruoStuptuOnwodtuhSLLP

00 etatS-eerhTetatS-eerhTnevirDLLPN
01 nevirDetatS-eerhTnevirDLLPN
10 nevirDnevirDnevirDecnerefeRY
11 nevirDnevirDnevirDLLPN

Select Input Decoding for PI6C2309-1

1
2
3

V

DD

4

GND 5

CLKA2

6

CLKB2 7

S18

CLKB1

CLK_OUT

CLKA3
V

DD

CLKB4
CLKB3

S2

16
15
14
13
12
11
10

9

REF

CLKA1

GND

CLKA4

16-Pin

L, W

PLL

MUX

REF

FBK

S2

S1

Select Input

Decoding

CLK_OUT
CLKA1
CLKA2
CLKA3
CLKA4

CLKB2
CLKB3
CLKB4

CLKB1

2

PS8478 04/27/00

PI6C2309-1

3.3V Zero-Delay Buffer

To achieve a Zero Delay between the input and output, all outputs
should be uniformly loaded. The relative loading of CLK_OUT(with
respect to the remaining outputs) can adjust the input-output delay.
This is shown in the graph above.

Zero Delay and Skew Control

REF. Input to CLKA/CLKB Delay vs. Difference in Loading between CLK_OUT pin and CLKA/CLKB pins.

Maximum Ratings

Supply Voltage to Ground ................................ –0.5V to +7.0V

DC Input Voltage (Except REF) ................ –0.5V to VDD +0.5V

DC Input Voltage REF...............................................–0.5 to 7V

Storage Temperature...................................... –65º C to +150ºC

Maximum Soldering Temperature (10 seconds)...............260ºC

Junction Temperature ...................................................... 150ºC

Static Discharge Voltage

(per MIL-STD-883, Method 3015)................................. >2000V

For applications requiring zero input-output delay, all outputs,
including CLK_OUT, should be equally loaded. Even if CLK_OUT
is not used, it must have a capacitive load that is equal to that on every
other output. If input-output delay adjustments are required, use the
above graph to calculate loading differences between the feedback
output and remaining outputs.

600

800

400

200

0

-200

-400

-600

-800

-900

-1000

-25 -20 -15 -10 -5

0 5 10 15 20 25

Output Load Difference: CLK_OUT Load - CLKA/CLKB Load (pF)

REF - Input to Output CLK Delay (ps)

PI6C2309-1H

PI6C2309-1

3

PS8478 04/27/00

PI6C2309-1

3.3V Zero-Delay Buffer

Electrical Characteristics (Over the operating condition)

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tnerruCWOLtupnIV

NI

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05

µA

I

HI

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DD



002

V

LO

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V

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

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µA

I

DD

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Pin Description

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31V

DD

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413AKLC

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514AKLC

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61TUO_KLC

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Operating Conditions

Notes:

1 . Weak pull-down.

2. Weak pull-down on all outputs.

3. Weak pull-ups on these inputs.
4 . REF and CLK_OUT inputs have a threshhold

voltage of VDD/2.

5. Parameter is guaranteed by design and characterization.
Not 100% tested in production.

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7

4

PS8478 04/27/00

PI6C2309-1

3.3V Zero-Delay Buffer

Notes:

5. Parameter is guaranteed by design and characterization. Not 100% tested in production.

6. For definition of t

1-8

, see Switching Waveforms on page 5

Switching Characteristics

(5,6)

(Over the operating condition)

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t

3

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t

3

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t

3

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)5(

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t

4

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t

4

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t

4

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5

PS8478 04/27/00

PI6C2309-1

3.3V Zero-Delay Buffer

Switching Waveforms

Test Circuit #1

V

DD

C

LOAD

V

DD

GND GND

Outputs

0.1µF

0.1µF

Test Circuit for all parameters except t

8

t

2

t

1

1.4V 1.4V 1.4V

t3,t

8

t4,t

8

0.8V

2.0V

0.8V

2.0V

OUTPUT

0V

3.3V

1.4V

t

5

OUTPUT

1.4V

OUTPUT

VDD/2

t

6

INPUT

VDD/2

CLK_OUT

VDD/2

t

7

CLK_OUT Device 1

VDD/2

CLK_OUT Device 2

Duty Cycle Timing

All Outputs Rise/Fall Time

Output-Output Skew

Input-Output Propagation Delay

Device-Device Skew

6

PS8478 04/27/00

PI6C2309-1

3.3V Zero-Delay Buffer

SEATING PLANE

.050
BSC

1

16

0-8˚

.149
.157

X.XX
X.XX

DENOTES DIMENSIONS
IN MILLIMETERS

3.78

3.99

.386
.393

9.80

10.00

1.27

.053
.068

1.35

1.75

.2284
.2440

5.80

6.20

.0040
.0098

0.10

0.25

.013
.020

.0155
.0260

0.330

0.508

0.393

0.660

.0075
.0098

0.25

0.50

.0099
.0196

x 45˚

0.19

0.25

.016
.050

0.41

1.27

REF

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax [phone] • http://www.pericom.com

Package Diagrams

16-Pin SOIC (150-Mil Wide) W Package

Note: Controlling dimensions in millimeters. Ref: JEDEC MS - 012 AC

Ordering Information

.193
.201

.047
max.

.002
.006

SEATING
PLANE

.0256

BSC

.018
.030

.004
.008

.252
BSC

1

16

.169
.177

X.XX
X.XX

DENOTES CONTROLLING DIMENSIONS
IN MILLIMETERS

0.05

0.15

6.4

0.45

0.75

0.09

0.20

4.3

4.5

1.20

4.9

5.1

0.65

0.19

0.30

.007
.012

16-Pin TSSOP L Package

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W1-9032C6IP

61WCIOSlim-051nip-61

laicremmoC

WH1-9032C6IP

L1-9032C6IP

61LPOSSTmm4.4nip-61

LH1-9032C6IP

IW1-9032C6IP

61WCIOSlim-051nip-61

lairtsudnI

IWH1-9032C6IP

IL1-9032C6IP

61LPOSSTmm4.4nip-61

ILH1-9032C6IP