Datasheet PI6C182AH, PI6C182H Datasheet (PERICOM)

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PI6C182

Precision 1-10 Clock Buffer

Product Features

• Low noise non-inverting 1-10 buffer

• Supports frequency up to 125 MHz (PI6C182A)

• Supports up to four SDRAM DIMMs

• Low skew (<200ps) between any two output clocks

2

• I

C Serial Configuration interface

• Multiple V

, VSS pins for noise reduction

DD

• 3.3V power supply voltage

• Separate Hi-Z state pin for testing

• 28-pin SSOP package (H)

Block Diagram

SDRAM0

SDRAM1

BUF_IN

SDRAM2

SDRAM3

SDRAM9

OE

SDATA

SCLOCK

I2C

I/O

Description

Pericom Semiconductors PI6C clock series is produced using the
companys advanced submicron CMOS technology, achieving
industry leading speed.

The PI6C182/182A is a high-speed low-noise 1-10 noninverting
buffer designed for SDRAM clock buffer applications.

PI6C182 supports frequencies up to 110 MHz. PI6C182A sup­ports higher frequencies up to 125 MHz.

At power up all SDRAM output are enabled and active. The I2C
Serial control may be used to individually activate/deactivate any
of the 10 output drivers.

The output enable (OE) pin may be pulled low to Hi-Z state all
outputs.

Note:

Purchase of I2C components from Pericom conveys a license to
use them in an I2C system as defined by Philips.

Pin Configuration

V

DD0

SDRAM0
SDRAM1

V

SS0

V

DD1

SDRAM2

SDRAM3 7

V

SS1

BUF_IN

V

DD2

SDRAM8

V

SS2

V

DDIIC

SDATA

1

2

3

4

5

6

8

9

10
11
12
13

14

28-Pin

H

28

27

26

25

24

23

22

21

20
19
18

17

16

15

V

DD5

SDRAM7

SDRAM6

V

SS5

V

DD4

SDRAM5

SDRAM4

V

SS4

OE

V

DD3

SDRAM9

V

SS3

V

SSIIC

SCLOCK

1

PS8165C 01/18/01

Pin Description

niPlobmySepyT.ytQnoitpircseD

7,6,3,2]3-0[MARDSO4 tuptuokcolc0etyBMARDS

72,62,32,22]7-4[MARDSO4 tuptuokcolc1etyBMARDS

81,11]9-8[MARDSO2 tuptuokcolc2etyBMARDS

9NI_FUBI1 reffub01-1roftupnI

PI6C182

Precision 1-10 Clock Buffer

02EOI1

41ATADSO/I1 IrofnipataD

51KCOLCSO/I1 InipkcolC

82,42,91,01,5,1V

52,12,71,21,8,4V

31V

61V

]5-0[DD

]5-0[SS

CIIDD

CIISS

rewoP6 reffubMARDSrofylppusrewopV3.3

dnuorG6 sreffubMARDSrofdnuorG

rewoP1 IrofylppusrewopV3.3

dnuorG1 IrofdnuorG

OE Functionality

EO]9-0[MARDSetoN

0Z-iH1

1NI_FUB2

Notes:

1. Used for test purposes only

2. Buffers are non-inverting

k001>asaH.WOLdlehnehwstuptuollasetatsZ-iH Ω

rotsiserpu-lluplanretni

2

2

2

2

yrtiucricC

k001>asaH.yrtiucricC Ω rotsiserpu-lluplanretni

k001>asaH.yrtiucricC Ω rotsiserpu-lluplanretni

yrtiucricC

PI6C182 Serial Configuration Map

Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)

tiB#niPnoitpircseD

7tiB)0otezilaitinI(CN
6tiB)0otezilaitinI(CN
5tiB)0otezilaitinI(CN

PI6C182 I2C Address Assignment

6A5A4A3A2A1A0AW/R

1101001 0

4tiB)0otezilaitinI(CN
3tiB7 )evitcanI/evitcA(3MARDS
2tiB6 )evitcanI/evitcA(2MARDS
1tiB3 )evitcanI/evitcA(1MARDS
0tiB2 )evitcanI/evitcA(0MARDS

Note:

Inactive means outputs are held LOW and
are disabled from switching

2

PS8165C 01/18/01

2-Wire I2C Control

The I2C interface permits individual enable/disable of each clock
output and test mode enable.

The PI6C182 is a slave receiver device. It can not be read back.
Sub addressing is not supported. All preceding bytes must be sent
in order to change one of the control bytes.

Every byte put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers SDATA changes only when SCLOCK
is LOW. Exceptions: A HIGH to LOW transition on SDATA
while SCLOCK is HIGH indicates a start condition. A LOW to
HIGH transition on SDATA while SCLOCK is HIGH is a stop
condition and indicates the end of a data transfer cycle.

PI6C182

Precision 1-10 Clock Buffer

a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW = write to addressed device). If the
devices own address is detected, PI6C182 generates an acknowl­edge by pulling SDATA line LOW during ninth clock pulse, then
accepts the following data bytes until another start or stop condi­tion is
detected.

Following acknowledgement of the address byte (D2), two more
bytes must be sent:

1. Command Code byte

2. Byte Count byte.

Each data transfer is initiated with a start condition and ended with

Although the data bits on these two bytes are dont care, they
must be sent and acknowledged.

Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)

tiB#niPnoitpircseD

7tiB72)evitcanI/evitcA(7MARDS
6tiB62)evitcanI/evitcA(6MARDS
5tiB32)evitcanI/evitcA(5MARDS
4tiB22)evitcanI/evitcA(4MARDS
3tiB)0otezilaitinI(CN
2tiB)0otezilaitinI(CN
1tiB)0otezilaitinI(CN
0tiB)0otezilaitinI(CN

Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)

tiB#niPnoitpircseD

7tiB81)evitcanI/evitcA(9MARDS
6tiB11)evitcanI/evitcA(8MARDS
5tiB)devreseR(
4tiB)devreseR(
3tiB)devreseR(
2tiB)devreseR(
1tiB)devreseR(
0tiB)devreseR(

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature.......................................................... 65°C to +150°C

Ambient Temperature with Power Applied........................... 0°C to +70°C

3.3V Supply Voltage to Ground Potential ........................... 0.5V to +4.6V

DC Input Voltage .................................................................. 0.5V to +4.6V

Note:

Stresses greater than those listed under MAXIMUM RAT­INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex­tended periods may affect reliability.

Supply Current (VDD = +3.465V, C

lobmySretemaraPnoitidnoCtseT.niM.pyT.xaMstinU

I

DD

I

DD

I

DD

I

DD

tnerruCylppuS

LOAD

= Max.)

zHM0=NI_FUB3

zHM66.66=NI_FUB031

Am

zHM0.001=NI_FUB032

zHM3.331=NI_FUB063

3

PS8165C 01/18/01

PI6C182

Precision 1-10 Clock Buffer

DC Operating Specifications (V

lobmySretemaraPnoitidnoCtseT.niM.xaMstinU

egatloVtupnI

V

HI

V

LI

I

LI

V

DD

V

HO

V

LO

C

TUO

C

NI

L

NIP

T

A

egatlovhgihtupnIV

egatlovwoltupnIV

tnerrucegakaeltupnIV<0

%5±V3.3=]9-0[

egatlovhgihtuptuOI

egatlovwoltuptuOI

ecnaticapacniptuptuO6

ecnaticapacniptupnI5

ecnatcudnIniP7Hn

erutarepmeTtneibmAwolfriAoN007C°

= +3.3V ±5%, TA = 0°C - 70°C)

DD

DD

NI<VDD

Am1-=4.2

HO

Am1=4.0

LO

0.2VDD3.0+

SS

5-5+Am

SDRAM Clock Buffer Operating Specification

lobmySretemaraPsnoitidnoCtseT.niM.pyT.xaMstinU

I

NIMHO

I

XAMHO

I

NIMLO

I

XAMLO

t

t

MARDS

HR

MARDS

HT

tnerrucpu-lluPV

tnerrucpu-lluPV

tnerrucnwod-lluPV

tnerrucnwod-lluPV

etaregdeesirtuptuO

ylnoMARDS

etaregdellaftuptuO

ylnoMARDS

V0.2=45-

TUO

TUO

TUO

TUO

V531.3=64-

V0.1=45

V4.0=35

%5±V3.3

V4.2-V4.0@

%5±V3.3

V4.0-V4.2@

5.14

5.14

3.0-8.0

V

V

Fp

Am

sn/V

AC Timing

lobmySretemaraP

t

PKDS

HKDS

t

LKDS

t

ESIRDS

t

LLAFDS

t

HLP

t

LHP

t,

t

LZP

HZP

t

t,

ZLP

ZHP

elcyCytuDV5.1taderusaeM545554555455%

t

WKSDS

zHM66zHM001zHM331

.niM.xaM.niM.xaM.niM.xaM

doirepKLCMARDS0.515.510.015.015.70.8

emithgihKLCMARDS6.53.31.2

emitwolKLCMARDS3.51.39.1

emitesirKLCMARDS5.10.45.10.45.10.4

emitllafKLCMARDS5.10.45.10.45.10.4

yaledporpHLreffuBMARDS0.10.50.10.50.10.5

yaledporpLHreffuBMARDS0.10.50.10.50.10.5

yaledelbanEreffuBMARDS0.10.80.10.80.10.8

yaledelbasiDreffuBMARDS0.10.80.10.80.10.8

wekStuptuOottuptuOMARDS052052002sp

4

stinU

snt

sn/V

sn

PS8165C 01/18/01

PI6C182

Precision 1-10 Clock Buffer

Clocking
Interface

(TTL)

Input

Waveform

3.3V

2.4

1.5

0.4

Test Load

tSDKL

Test
Point

t

SDRISE

Output
Buffer

tSDKH

tSDKP

t

SDFALL

1.5V 1.5V

t

plh

t

phl

Output

Waveform

1.5V 1.5V

Figure 1. Clock Waveforms

Minimum and Maximum Expected Capacitive Loads

kcolCdaoL.niMdaoL.xaMstinUsetoN

MARDS0203FpnoitacificepSMMIDMARDS

Notes:

1. Maximum rise/fall times are guaranteed at maximum specified load.

2. Minimum rise/fall times are guaranteed at minimum specified load.

3. Rise/fall times are specified with pure capacitive load as shown.

Testing is done with an additional 500Ω resistor in parallel.

Design Guidelines to Reduce EMI

1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall
time are still within the specified values.

2. Minimize the number of vias of the clock traces.

3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).

4. Position clock signals away from signals that go to any cables or any external connectors.

5

PS8165C 01/18/01

PCB Layout Suggestion

C1 C7

VDD

VSS

C2

VDD

VSS

C3

VDD

VSS

C4

VDD

PI6C182

Precision 1-10 Clock Buffer

28

1

2

3

4

5

6

7

8

9

10

11

12

13

14

VDD

27

26

25

VSS

C6

24

VDD

23

22

21

VSS

20

19

18

17

16

15

C5

VDD

VSS

VSS

Ferrite Bead

22uF

VCC

C8

Via to GND Plane

Via to VDD Plane

Void in Power Plane

Note:

This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C1-C7 should be placed as close as possible to
their respective VDD.

Recommended capacitor values:

C1-C7 .............. 0.1µF, ceramic

C8 .................. 22µF

6

PS8165C 01/18/01

PI6C182

Clock from

Chipset

SDRAM

10

Figure 2. Design Guidelines

28-Pin SSOP Package Data

PI6C182

Precision 1-10 Clock Buffer

R

S

CL

SDRAM
DIMM
Spec.

Ordering Information

N/PnoitpircseD

H281C6IPegakcaPPOSSnip-82zHM011

HA281C6IPegakcaPPOSSnip-82zHM041

Pericom Semiconductor Corporation

2380 Bering Drive  San Jose, CA 95131  1-800-435-2336  Fax [phone]  http://www.pericom.com

7

PS8165C 01/18/01