Datasheet PI6C110EV Datasheet (PERICOM)

1

PS8410 08/11/99

REF/SEL2 1

V

DD3.3

2

XTAL_IN 3

3.3V

2.5V

2.5V

3.3V

3.3V

3.3V

XTAL_OUT 4

V

SS3.3

5

V

SS3.3

6
3V66 0 7
3V66 1 8
V

DD3.3

9
V

DD3.3

10

PCI 0 11
PCI 1 12
PCI 2 13

V

SS3.3

14

PCI 3 15
PCI 4 16

V

SS3.3

17

PCI 5 18
PCI 6 19
PCI 7 20

V

DD3.3

21

V

DDA

22

V

SSA

23

V

SS3.3

24

48MHz0 25
48MHz1 26

V

DD3.3

27

SEL0 28

V

SS2.5

APIC0
APIC1
V

DD2.5

CPU 0
V

DD2.5

CPU 1
CPU 2
V

SS2.5

56

V

SS3.3

55

SDRAM0

54

SDRAM1

53

V

DD3.3

52

SDRAM2

51

SDRAM3

50

V

SS3.3

49

SDRAM4

48

SDRAM5

47

V

DD3.3

46

SDRAM6

45

SDRAM7

44

V

SS3.3

43

DCLK

42

V

DD3.3

41
40
39
38
37
36
35
34

33

PWR_DWN#
SCLK
SDATA
SEL1

32
31
30
29

3.3V

56-Pin

(V56)

DCLK

REF
OSC

REF

X

IN

X

OUT

48 MHz 0-1

3V66 0-1

PCI 0-7

SDRAM 0-7

CPU 0-2

PLL2

PLL1

2

2

APIC 0-1

2

3

8

8

Pin Configuration

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

2

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

Block Diagram

Features

 3 of 2.5V 66/100/133 MHz CPU (CPU[0-2])
 2 of 2.5V 33 MHz APIC (APIC[0-1])
 9 of 3.3V 100/133 MHz SDRAM (SDRAM[0-7], DCLK)
 8 of 3.3V 33 MHz PCI (PCI[0-7])
 2 of 3.3V 66 MHz (3V66 [0-1])
 2 of 3.3V 48 MHz (48MHz [0-1])
 1 of 3.3V 14.3 MHz (REF)
 Selectable CPU and SDRAM clocks (on power up only)
 Power down function using PWR_DWN#
 Spread Spectrum Enable/Disable by I2C
I2C interface to turn off unused clocks
 56 pin SSOP package (V)

Description

Pericom PI6C110E integrates a dual PLL clock generator, SDRAM
buffer and I2C interface. The clock generator section comprised
of an oscillator, 2 low jitter phased locked loop, skew control, and
power down logic. The SDRAM buffers are high speed and low
skew to handle data transfers in excess of 133 MHz.

When Spread Spectrum mode is enabled, all clock outputs are
modulated except for REF and 48 MHz[0-1] outputs. These clocks
are down spread linearly (triangular modulation) by +0%, 0.6%.

To minimize power consumption and EMI radiation some unused
outputs can be turned off. Two wire I2C interface is used to enable/
disable Spread Spectrum mode, and to turned off PCI clocks, CPU
clocks, and 48 MHz clocks.

For low power sleep mode, the entire device can be placed to power
down mode. Driving the PWR_DWN# to low state disables the
entire chip. In this state the crystal oscillator, and both PLLs are
turned off. Furthermore, all outputs are deactivated to low state, all
inputs are inactive except for PWR_DWN#.

All trademarks are of their respective companies.

V

2

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

niPepyT.ytQS/PlobmySnoitpircseD

1O/I13.32LES/FER

sinipsihtpurewopgniruD.tuptuoecnereferzHM813.41yllamroN

.mhOK001/wnwoddellupyllanretnI.2tibkcolc,2LESsadelpmas

3I13.3NI_LATXtupnilatsyrczHM813.41

4O13.3TUO_LATXtuptuolatsyrczHM813.41

8,7O23.3]1-0[66V3zHM66

,51,31,21,11

02,91,81,61

O8 3.3]7-0[ICPstuptuoICP

62,52O13.3]1-0[zHM84tuptuozHM84

92,82I23.3]1-0[LESpulluplanretni,stupnitcelesycneuqerflevelLTTVL

03O/I13.3ATADSI

2

pulluplanretni,ATADSelbitapmocC

13I13.3KCOLCSI

2

pulluplanretni,KCOLCSelbitapmocC

23I13.3#NWDRWPwolevitca,tupnilortnocnwoDrewoPlevelLTTVL

,93,73,63,43

64,54,34,24,04

O9 3.3

,KLCD

]7-0[MARDS

.]2-0[LESnognidnepedzHM331/001.stuptuoKLCDdnaMARDS

Ihguorhtffodenrutebnac]7-0[MARDS

2

.KLCDtontub,C

25,05,94O35.2]2-0[UPC]2-0[LESnognidnepedzHM331/001/66.tuptuokcolCsuBtsoH

55,45O25.2]1-0[CIPAkcolcICPotsuonorhcnys,kcolcCIPAzHM33

,72,12,01,9,2

44,83,33

RWP83.3V

3.3DD

ylppuSrewoPV3.3

,42,71,41,6,5

74,14,53

DNG8A/NV

3.3SS

dnuorGV3.3

35,15RWP25.2V

5.2DD

ylppuSrewoPV5.2

65,84DNG2A/NV

5.2SS

dnuorGV5.2

22RWP13.3V

ADD

ylppuSrewoPeroCV3.3

32DNG1A/NV

ASS

dnuorGeroCV3.3

Pin Description Table

2LES1LES0LESnoitcnuF

X0 0 etatS-irT

X0 1 tseT

010 zHM001=MARDS,zHM66=UPC

011 zHM001=MARDS,zHM001=UPC

110 zHM331=MARDS,zHM331=UPC

111 zHM001=MARDS,zHM331=UPC

Frequency Select Function Table

3

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

Symbol Parameter Min. Max. Units Notes

V

IH3

3.3V Input High Voltage -0.5 4.6 V 1

V

IL3

3.3V Input Low Voltage -0.5 V

ESD prot. Input ESD protection 2000 V 2

DC Specifications

DC parameters must be sustainable under steady state (DC) conditions.

Notes:

1. Maximum VIH is not to exceed maximum VDD.

2. Human body model.

Symbol Parameter Min. Max. Units Notes

V

DDA

3.3V Core Supply Voltage -0.5 4.6 V

V

DD2.5

2.5V I/O Supply Voltage -0.5 3.6 V

V

DD3.3

3.3V I/O Supply Voltage -0.5 4.6 V

T

S

Storage Temperature -65 150 °C

Absolute Maximum DC Power Supply

Absolute Maximum DC I/O

Symbol Parameter Condition Min. Max. Units Notes

V

DDA

3.3V Core Supply Voltage 3.3V ±5% 3.135 3.465 V 2

V

DD3.3

3.3V I/O Supply Voltage 3.3V ±5% 3.135 3.465 V 2

V

DD2.5

2.5V I/O Supply Voltage 2.5V ±5% 2.375 2.625 V 2

V

IH3

3.3V Input High Voltage V

DDA

2.0 VDD+0.3 V 4

V

IL3

3.3V Input Low Voltage VSS-0.3 0.8 V 4

I

IL

Input Leakage Current 0 <VIN <V

DD3.3

-5 +5 µA 1,4

C

in

Input Pin Capacitance 5 pF

C

xtal

Xtal Pin Capacitance 13.5 22.5 pF 3

C

out

Output Pin Capacitance 6 pF

L

PIN

Pin Inductance 7 nH

T

A

Ambient Temperature No Airflow 0 70 °C

DC Operating Specification

Notes:

1. Input Leakage Current does not include inputs with Pull-Up or Pull-down resistors.

2. No power sequencing is implied or allowed to be required in the system.

3. As seen by the crystal. Device is intended to be used with a 17-20pF AT crystal.

4. All inputs referenced to 3.3V power supply.

4

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

Clock Output Buffer DC Characteristics

emaNreffuBV

CC

)V(egnaR)mhO(ecnadepmIepyTreffuB

CIPA,UPC526.2-573.254-5.311epyT

FER,zHM84

564.3-531.3

06-023epyT

MARDS42-014epyT

66V3,ICP55-215epyT

lobmySretemaraPnoitidnoC.niM.pyT.xaMstinU

I

NIMHO

tnerruCpU-lluP

V

TUO

=V0.172

Am

I

XAMHO

V

TUO

=V573.272

I

NIMLO

tnerruCnwoD-lluP

V

TUO

=V2.103

I

XAMLO

V

TUO

=V3.003

Type 1: CPU, APIC Clocks

lobmySretemaraPnoitidnoC.niM.pyT.xaMstinU

I

NIMHO

tnerruCpU-lluP

V

TUO

=V0.192

Am

I

XAMHO

V

TUO

=V531.332

I

NIMLO

tnerruCnwoD-lluP

V

TUO

=V59.192

I

XAMLO

V

TUO

=V4.072

Type 3: 48 MHz, REF Clocks

lobmySretemaraPnoitidnoC.niM.pyT.xaMstinU

I

NIMHO

tnerruCpU-lluP

V

TUO

V0.2=45

Am

I

XAMHO

V

TUO

V531.3=64

I

NIMLO

tnerruCnwoD-lluP

V

TUO

V0.1=45

I

XAMLO

V

TUO

V4.0=35

Type 4: SDRAM Clocks

lobmySretemaraPnoitidnoC.niM.pyT.xaMstinU

I

NIMHO

tnerruCpU-lluP

V

TUO

=V0.133

Am

I

XAMHO

V

TUO

=V531.333

I

NIMLO

tnerruCnwoD-lluP

V

TUO

=V59.103

I

XAMLO

V

TUO

=V4.083

Type 5: PCI, 3V66 Clocks

5

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

AC Timing Specifications

(see notes on next page)

lobmySretemaraP

zHM66zHM001zHM331

stinUsetoN

.niM.xaM.niM.xaM.niM.xaM

doirePTdoirepKLCUPC/tsoH0.515.510.015.015.70.8sn7,2

HGIHTemithgihKLCUPC/tsoH2.5A/N0.3A/N78.1A/Nsn3

WOLTemitwolKLCUPC/tsoH0.5A/N8.2A/N76.1A/Nsn4

etaRegdE)V5.2reffuB1epyT(etaRegdEgnisiR0.10.40.10.40.10.4sn/V

etaRegdE)V5.2reffuB1epyT(etaRegdEgnillaF0.10.40.10.40.10.4sn/V
esiRTemitesirKLCUPC/tsoH4.06.14.06.14.06.1sn6,1
llaFTemitllafKLCUPC/tsoH4.06.14.06.14.06.1sn6,1

doirePT doirepKLCzHM33CIPA 0.03 A/N 0.03 A/N 0.03 A/N sn 7,2

HGIHT emithgihKLCzHM33CIPA 0.21 A/N 0.21 A/N 0.21 A/N sn 3

WOLT emitwolKLCzHM33CIPA 0.21 A/N 0.21 A/N 0.21 A/N sn 4

etaRegdE )V5.2reffuB1epyT(etaRegdEgnisiR 0.1 0.4 0.1 0.4 0.1 0.4 sn/V

etaRegdE )V5.2reffuB1epyT(etaRegdEgnillaF 0.1 0.4 0.1 0.4 0.1 0.4 sn/V
esiRT emitesirKLCzHM33CIPA 4.0 6.1 4.0 6.1 4.0 6.1 sn 6,1
llaFT emitllafKLCzHM33CIPA 4.0 6.1 4.0 6.1 4.0 6.1 sn 6,1

doirePTdoirepKLC66V30.510.610.510.610.510.61sn7,2

HGIHTemithgihKLC66V352.5A/N52.5A/N52.5A/Nsn3

WOLTemitwolKLC66V35.5A/N5.5A/N5.5A/Nsn4

etaRegdE)V3.3reffuB5epyT(etaRegdEgnisiR0.10.40.10.40.10.4sn/V

etaRegdE)V3.3reffuB5epyT(etaRegdEgnillaF0.10.40.10.40.10.4sn/V
esiRTemitesirKLC66V35.00.25.00.25.00.2sn6,1
llaFTemitllafKLC66V35.00.25.00.25.00.2sn6,1

doirePT doirepKLCCIPA&ICP 0.03 A/N 0.03 A/N 0.03 A/N sn 7,2

HGIHT emithgihKLCCIPA&ICP 0.21 A/N 0.21 A/N 0.21 A/N sn 3

WOLT emitwolKLCCIPA&ICP 0.21 A/N 0.21 A/N 0.21 A/N sn 4

etaRegdE )V3.3reffuB5epyT(etaRegdEgnisiR 0.1 0.4 0.1 0.4 0.1 0.4 sn/V

etaRegdE )V3.3reffuB5epyT(etaRegdEgnillaF 0.1 0.4 0.1 0.4 0.1 0.4 sn/V
esiRT emitesirKLCCIPA&ICP 5.0 0.2 5.0 0.2 5.0 0.2 sn 6,1
llaFT emitllafKLCCIPA&ICP 5.0 0.2 5.0 0.2 5.0 0.2 sn 6,1

doirePTdoirepKLCMARDSA/NA/N5.015.015.70.8sn7,2

HGIHTemithgihKLCMARDSA/NA/N0.3A/N78.1A/Nsn3

WOLTemitwolKLCMARDSA/NA/N8.2A/N76.1A/Nsn4

etaRegdE)V3.3reffuB4epyT(etaRegdEgnisiRA/NA/N5.10.40.10.4sn/V

etaRegdE)V3.3reffuB4epyT(etaRegdEgnillaFA/NA/N5.10.40.10.4sn/V
esiRTemitesirKLCMARDSA/NA/N4.06.14.06.1sn6,1
llaFTemitllafKLCMARDSA/NA/N4.06.14.06.1sn6,1

HZpt,LZpT )stuptuOllA(yaleDelbanEtuptuO 0.1 0.01 0.1 0.01 0.1 0.01 sn
HZpt,ZLpT )stuptuOllA(yaleDelbasiDtuptuO 0.1 0.01 0.1 0.01 0.1 0.01 sn

elbatsT pu-rewopmorfnoitazilibatskcolcllA 3 3 3 sm 5

6

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

AC Timing Notes:

1.Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels.

2.Period, jitter, offset and skew measured on rising edge @1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.

3. T

HIGH

is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.

4. T

LOW

is measured at 0.4V for all outputs.

5.The time specified is measured from when the power supply achieves its nominal operating level
(typical condition V

DD3.3V

= 3.3V) until the frequency output is stable and operating within specification.

6. T

RISE

and T

FALL

are measured as a transition through the threshold region

VOL = 0.4V and VOH = 2.0V (1mA) JEDEC Specification.

7.The average period over any 1µs period of time must be greater than the minimum specified period.

Pin-pin

Output Skew Cycle-Cycle Skew, jitter

Group MAX. Jitter Duty Cycle Nom V

DD

measure point

CPU 175ps 250ps 45/55 2.5V 1.25V
SDRAM 250ps 250ps 45/55 3.3V 1.5V
APIC 250ps 500ps 45/55 2.5V 1.25V
48 MHz N/A 500ps 45/55 3.3V 1.5V
3V66 175ps 500ps 45/55 3.3V 1.5V
PCI 500ps 500ps 45/55 3.3V 1.5V
REF N/A 1000ps 45/55 3.3V 1.5V

Group Skew And Jitter Limits

Clock Output Wave

TRISE

2.0

0.4

Tperiod

1.25

THIGH

TLOW

Duty Cycle

.5V Clocking

Interface

Output

Buffer

Test Point

Test Load

TFALL

TRISE

2.4

0.4

Tperiod

1.5

THIGH

TLOW

Duty Cycle

3.3V Clocking
Interface

TFALL

2

Output

Output Waveform

Figure 1.

7

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

Vol = 0. 4V

Vih = 1.7V

1.25V

Vil = 0.7V

Voh = 2.0V

Measu remen t Points F o r Comp on ent Output

Measurement Poin ts Fo r System Level Inputs

V

DD

2.5

Vss

Vo l = 0.4V

Vih = 2.0V

1.5V

Vil = 0.8V

Voh = 2.4V

Measurement Points For Component Output

Measurement Points fo r System Level Inputs

V

DD

2.5

Vss

2.5 Volt Mea su re P oints

3.3 Volt Mea sure Po ints

Figure 2. Component Versus System Measure Points

Note:
Only offset specifications listed above are guaranteed/tested. The specification is treated as ANY output within first
specified bank to ANY output of the second specified bank. Pin-pin skew is implied within offset specification, jitter
is not. Previous offset specifications such as CPU to PCI offset are no longer required.

Group to Group Skew Tolerance

puorG

66UPC66UPC001UPC001UPC331UPC331UPC

tesffOecnareloTtesffOecnareloTtesffOecnareloT

001MARDSotUPCsn5.2sp005sn0.5sp005sn0.0sp005

331MARDSotUPCA/NA/NA/NA/Nsn0.5sp005

66V3otUPCsn0.5sp005sn0.5sp005sn0.0sp005

66V3ot001MARDSsn0.0sp005sn0.0sp005sn0.0sp005

66V3ot331MARDSA/NA/NA/NA/Nsn0.0sp005

ICPot66V3sn5.3~5.1sp005sn5.3~5.1sp005sn5.3~5.1sp005

CIPAotICPsn0.0sn0.1sn0.0sn0.1sn0.0sn0.1

TOD&zHM84cnysAA/NcnysAA/NcnysAA/N

8

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

Group Offset Measurement Clarification

0.0ns 10.0ns 20.0ns 30.0ns

7.5ns

7.5ns

5.0ns 5.0ns

0.0ns

0.0ns

0.0ns

0.0ns

7.5ns0.0ns

3.75ns

1.5~3.5ns

0.0ns

15ns 22.5ns

CPU66

SDRAM100

3V66

CPU100

SDRAM100

3V66

CPU133

SDRAM100

3V66

CPU133

SDRAM133

3V66

3V66

PCI

APIC

9

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

Truth Table

Notes:

1. Required for board level bed of nails testing.

2. Normal mode of operation.

3. TCLK is a test clock over driven on the XTAL_IN input during test mode.

4. Required for DC output impedance verification.

5. Range of reference frequency allowed is min = 14.316 MHz, nominal = 14.31818 MHz, max = 14.32 MHz.

6. Frequency accuracy of 48 MHz is ±167PPM to match 48 MHz default.

2LES1LES0LESUPCMARDS66V3ICPzHM84FERCIPAsetoN

X00 Z-iHZ-iHZ-iHZ-iHZ-iHZ-iHZ-iH1

X01 2/KLCT2/KLCT3/KLCT6/KLCT2/KLCTKLCT6/KLCT4,3

010 zHM66zHM001zHM66zHM33zHM84zHM813.41zHM33

6,5,2

011 zHM001zHM001zHM66zHM33zHM84zHM813.41zHM33

110 zHM331zHM331zHM66zHM33zHM84zHM813.41zHM33

111 zHM331zHM001zHM66zHM33zHM84zHM813.41zHM33

Clock Enable Configuration

Notes:

1. LOW means outputs held static LOW.

2. ON means active.

3. PWR_DWN# pulled LOW, impacts all outputs including REF and 48 MHz outputs.

#NWD_RWPUPCMARDSCIPA66V3ICP

,FER

ZHM84

csOsOCV

0WOLWOLWOLWOLWOLWOLFFOFFO

1NONONONONONONONO

System Clock Design Considerations

PI6C110E supports 4 operational modes. It varies the FSB (Front Side Bus) and SDRAM clock frequencies. FSB selection is 66
MHz, 100 MHz or 133 MHz. SDRAM frequency is either 100 MHz or 133 MHz. The supported modes are:

SEL[2:0] Mode CPU SDRAM 3V66 APIC/PCI

0 1 0 Mode 0 66 100 66 33
0 1 1 Mode 1 100 100 66 33 default
1 1 0 Mode 2 133 133 66 33
1 1 1 Mode 3 133 100 66 33

The clock select pins, SEL[2:0] have the appropriate 100K (±20K) internal pull up and pull down to allow the system defaults to 100 MHz
CPU clock and 100 MHz SDRAM clock without external strapping resistor. SEL2 in pulled down, SEL1 and SEL0 is pulled up to indicate
0 1 1.

The APIC clock is a 33 MHz, the same frequency and phase as the PCI clocks, except it is powered by 2.5V supply. APIC and PCI clocks
are always in phase with the other clocks. In Mode 0, CPU and 3V66 are inverted. In Mode 1 and Mode 3, CPU and SDRAM clocks
are inverted.

System Debug and Timing Margin Analysis

To support system debug and to measure/test margin analysis, the internal PI6C110E oscillator circuits allows the input crystal frequency
to be driven with parallel resonant crystal with frequency range of 10 MHz to 20 MHz in laboratory environment. The alternative is to
put the device in TEST mode, SEL2 = dont care, SEL1 = 1 and SEL0 = 0. Then drive a clock signal to XTAL_IN (pin 3) from
a signal generator and float XTAL_OUT (pin 4).

10

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

Power Management

Notes:

1. Clock on/off latency is defined in the number of rising edges of free running PCI clock
between the clock disable goes low/high to the first valid clock comes out of the device.

2. Power up latency is when PWRDWN# goes inactive (high) to when the first valid clocks
are driven from the device.

The power down selection is used to put the part into a very low
power state without turning off the power to the part. PWRDWN#
is an asynchronous active low input. This signal is synchronized
internal to the device prior to powering down the clock synthesizer.
PWRDWN# is an asynchronous function for powering up the
system. Internal clocks are not running after the device is put in
power down. When PWRDWN# is active low all clocks are driven

langiSetatSlangiS

ycnetaL

skcolCICPfosegdegnisirfo.oN

#NWDRWP)noitarepolamron(1sm3

)nwodrewop(0woleBmargaiDgnimiTeeS

Power Management

Maximum Current

noitidnoC

,noitpmusnocylppus5.2.xaM

,sdaolpacteercsid.xaM

V

5.2DD

V526.2=

V=stupnicitatsllA

3.3DD

Vro

SS

,noitpmusnocylppus3.3.xaM

,sdaolpacteercsid.xaM

V

3.3DD

,V564.3=

V=stupnicitatsllA

3.3DD

Vro

SS

edoMnwoDrewoP

)0=)#NWDRWP(

Aµ001Aµ002

zHM001=MARDS,zHM66=UPC

010=]2-0[LES

Am07Am082

zHM001=MARDS,zHM001=UPC

110=]0-2[LES

Am001Am082

zHM331=MARDS,zHM331=UPC

011=]0-2[LES

DBTDBT

zHM001=MARDS,zHM331=UPC

111=]0-2[LES

DBTDBT

to a low value and held prior to turning off the VCOs and the crystal.
The power -up latency needs to be less than 3ms. The REF and
48 MHz clocks are expected to be stopped in the LOW state as soon
as possible. Due to the state of the internal logic, stopping and
holding the REF clock outputs in the LOW state may require more
than one clock cycle to complete.

11

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

PWRDWN# Timing Diagram

Notes:

1. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the
next high to low transition.

2. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside the part.

3. The shaded sections on the SDRAM, REF, and 48 MHz clocks indicate dont care states.

4. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66/133 MHz.

VCO Internal

CPU

3V66

PCI 33 MHz

APIC 33MHz

PWRDWN#

SDRAM

REF 14.318 MHz

48 MHz

25ns 50ns 75ns

Center

0ns

12

Minimum and Maximum Lumped Capacitive Loads

kcolC

.niM

daoL

.xaM

daoL

stinUsetoN

UPC0102

Fp

sdaol2elbissop,daolecived1

ICP0103stnemeriuqer1.2ICPteemtsuM

MARDS0203sceps331CP/001CP

66V30103sdaol2elbissop,daolecived1

zHM840102,daolecived1

FER0102,daolecived1

CIPA0102,daolecived1

12

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

Note: The acknowledgment bit is returned by the slave/receiver (the clock driver).

I2C Considerations

1. Address Assignment: Any clock driver in this specification can use the single, 7 bit address shown below. All devices can use

the address if only one master clock driver is used in a design.

The following address was confirmed by Philips on 09/04/96.

A6 A5 A4 A3 A2 A1 A0 R/W#
1 1 0 1 0 0 1 0

Note:

The R/W# bit is used by the I2C controller as a data direction bit. A zero indicates a transmission (WRITE) to the clock device.
A one indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller
to WRITE data; the R/W# bit of the address will always be seen as a zero.

2. Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality.

3. Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality.

4. Logic Levels: Assume all devices are based on a 3.3 Volt supply.

5. Data Byte Format: Byte format is 8-bits.

6. Data Protocol:

To simplify the clock I2C interface, the clock driver serial protocol was specified to use only block writes from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. Indexed bytes are not allowed.

The clock driver must meet this protocol which is more rigorous than previously stated I2C protocol. Treat the description from
the viewpoint of controller. The controller writes to the clock driver and if possible would read from the clock driver.

The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte
count which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would

be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed
to transfer a maximum of 32 data bytes.”

1 bit 7 bits 1 1 8 bits 1
Start bit Slave Address R/W Ack Command Code Ack Byte Count = N

Ack Data Byte 1 Ack Data Byte 2 Ack ...  Data Byte N Ack Stop
1 bit 8 bits 1 8 bits 1 8 bits 1 1

13

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software
programmable via the controller, but will be specified as 0000 0000 in the clock specification. The byte count byte is the number of
additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is
required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. For example:

7. Clock Stretching: The clock device must not hold/stretch the SCLK or SDATA lines low for more than 10 mS. Clock stretching is

discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an error/
time-out mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without
the use of clock/data stretching.

8. General Call: It is assumed that the clock driver will not have to respond to the general call.

9. Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15

of the I2C specification.

A) Pull-Up Resistors: There is a 100k internal resistor pull-ups on the SDATA and SCLK inputs. Assume that the board designer
will use a single external pull-up resistor for each line and that these values are in the 5-6K Ohm range. Assume one I2C device
per DIMM (serial presence detect), one I2C controller, one clock driver plus one/two more I2C devices on the platform for capacitive
loading purposes.

B) Input Glitch Filters: Only fast mode I2C devices require input glitch filters to suppress bus noise. The clock driver is specified
as a standard mode device and is not required to support this feature.

10. PWRDWN#: If a clock driver is placed in Power down mode, the SDATA and SCLK inputs are Tri-Stated and the device must retain

all programming information.

For specific I2C information consult the Philips I2C Peripherals Data Handbook ICI2 (1996)

A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller
interface can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the
bytes that are sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes
than the clock driver can handle.

etybtnuocetyBsetoN

BSMBSL

00000000.etybenotsaeltaevahtsuM.dewollatoN

00001000)cepsni0etybyltnerruc(retsigertcelesycneuqerfdnalanoitcnufrofataD

00000100)1etybneht,0etyb(atadfosetybowttsrifsdaeR

00001100)redroni2,1,0etyb(atadfosetybeerhttsrifsdaeR

00000010)redroni3,2,1,0etyb(atadfosetybruoftsrifsdaeR

00001010)redroni4,3,2,1,0etyb(atadfosetybeviftsrifsdaeR

00000110)redroni5,4,3,2,1,0etyb(atadfosetybxistsrifsdaeR

00001110)redroni6,5,4,3,2,1,0etyb(atadfosetybnevestsrifsdaeR
0100000023=detroppustnuocetyb.xaM

14

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

Byte 0 : Control Register (1 = Enable, 0 = Disable)

Byte 1: Control Register (1 = Enable, 0 = Disable)

Byte 2: Control Register (1 = Enable, 0 = Disable)

PI6C110E Conditions

At power up all SDRAM outputs are enabled and active. The SDATA and SCLK inputs have internal pull-up resistors with values
above 100K Ohms as well for complete platform flexibility.

PI6C110E Serial Configuration Map
A) The serial bits will be read by the clock driver in the following order:

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
B) All unused register bits (reserved and N/A) are designed as don't care. The controller will force all of these bits to a 0 level.
C) All reserved bits should be programmed to a logic level  0.

Note:

1. Default is for ALL clocks to be enabled and all reserved bits should be programmed to a logic level 0.
Spread spectrum modulation should power up disabled (Byte 0 bit 3 = 0).

Note: Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not
expected to be configured during the normal modes of operation.

tiB#niPemaNnoitpircseDniP

7tiB '0'otevirDdevreseR

)evitcanI/evitcA(

6tiB '0'otevirDdevreseR
5tiB '0'otevirDdevreseR
4tiB '0'otevirDdevreseR

3tiB

murtcepSdaerpS

)ffO=0/nO=1(
2tiB621BSU
1tiB520BSU
0tiB942UPC

tiB#niPemaNnoitpircseDniP

7tiB637MARDS

)evitcanI/evitcA(

6tiB736MARDS
5tiB935MARDS
4tiB044MARDS
3tiB243MARDS
2tiB342MARDS
1tiB541MARDS
0tiB640MARDS

tiB#niPemaNnoitpircseDniP

7tiB027ICP

)evitcanI/evitcA(

6tiB916ICP
5tiB815ICP
4tiB614ICP
3tiB513ICP
2tiB312ICP
1tiB211ICP
0tiB '0'otevirDdevreseR

Byte 3 and Byte 4:
Reserved Register (1 = Enable, 0 = Disable)

tiB#niPemaNnoitpircseDniP

7tiB '0'otevirDdevreseR

)evitcanI/evitcA(

6tiB '0'otevirDdevreseR
5tiB '0'otevirDdevreseR
4tiB '0'otevirDdevreseR
3tiB '0'otevirDdevreseR
2tiB '0'otevirDdevreseR
1tiB '0'otevirDdevreseR
0tiB '0'otevirDdevreseR

15

PS8410 08/11/99

PI6C110E

Clock Solution for 133 MHz

Celeron/Pentium II/III Processors

Ordering Information

N/PnoitpircseD

VE011C6IPegakcaPPOSSnip-65

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax [phone] • http://www.pericom.com

56 Pin SSOP Package Data

0.25

0.20

.025 BSC

0.635

.008

.008
.016

0-8˚

0.20

0.40

.110 2.79

.010

Gauge Plane

.291
.299

X.XX
X.XX

DENOTES DIMENSIONS
IN MILLIMETERS

7.39

7.59

.396
.416

10.06

10.56

.02
.04

0.51

1.01

.015
.025

0.381

0.635

.720
.730

18.29

18.54

.008
.0135

0.20

0.34

1

56

x 45˚

Nom.

Max