Datasheet PI6C106 Datasheet (PERICOM)

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PI6C106

Pentium/ProTM System Clock Chip

Features

• Three CPUs @2.5V, up to 100 MHz

• Seven PCIs @ 3.3V (including one free running, 1 early)

• One 48 MHz @ 3.3V fixed

• One REF (3.3V, 14.318 MHz)

• One IOAPIC (2.5V, 14.318 MHz)

• Strong REF clock (1V/ns @50pF load)

• Excellent power management features including

Power Down, PCI, and CPU stops

• Spread Spectrum for EMI control (0.5% down spread)

• Early PCI (2.5ns ±700ps)

• Enhanced PCICLK4 (1.5X)

• 28-pin SSOP Packaging (H)

CPU_STOP#

SPREAD#

SEL 100/66.6#

PD#

PCI_STOP#

X1
X2

OSC

PLL

Spread

Spectrum

÷2

PLL2

CPU

STOP

÷3

BUS

STOP#

REF0

VDDLA

IOAPIC

VDDLC

CPUCLK(0:2)

PCICLK_E

PCICLK(0:4)

PCICLK_F

48MHz

Description

The PI6C106 is part of a reduced pin count two-chip clock solution
for designs using an Intel BX style chipset. Companion SDRAM
buffers are PI6C182 & PI6C184.

There are two PLLs, with the first PLL capable of spread spectum
operation. CPU frequencies up to 100 MHz are supported.

Frequency Table

#6.66/001LESzHMUPCzHMICP

10013.33

06.663.33

Pin ConfigurationBlock Diagram

REF0

GND1

X1

X2

GND2
PCICLK_E
PCICLK_F

PCICLK0
PCICLK1

VDD2

PCICLK2

PCICLK3

PCICLK4/

SEL100/66.6#

VDD3

48MHz

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28-Pin

H

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VDD1
IOAPIC
VDDLA

CPUCLK0
CPUCLK1
CPUCLK2
VDDLC
GND
PCI_STOP#
CPU_STOP#
PD#
SPREAD#
GND3

1

PS8546A 07/13/01

Pin Descriptions

rebmuNniPemaNniPepyTnoitpircseD

11DNGRWP.2X,1X,tuptuoFERrofdnuorG

PI6C106

Pentium/ProTM System Clock Chip

21XNI

32XTUOFp33pacdaollanretnisah,tutuolatsyrCTUO_LATX

42DNGRWPstuptuoICProfdnuorG

5E_KLCICPTUO

6F_KLCICPTUO.#POTS_ICPybdetceffatoN.tuptuoICPgninnuReerF

11,01,8,7)3:0(KLCICPTUO.V3.3elbitapmocLTT.stuptuokcolcICP

92DDVRWP.V3.3yllanimon,stuptuoKLCICProfrewoP

4_KLCICPTUO)X5.1(.V3.3elbitapmocLTT.tuptuokcolcICP

21

#6.66/001LESNI

313DDVRWP.zHM84rofrewoP

41zHM84TUO.zHM84@tuptuoKLCdexiF

513DNGRWP.zHM84rofdnuorG

61#DAERPSNI.1.0daerpsnwod%5.0.evitcanehwmurtcepSdaerpSnosnruT

kcabdeefdnapacdaolFp33lanretnisah,tupnilatsyrCzHM813.41NI_LATX

.2Xmorfrotsiser

ybdetceffatoN.sp052±sn2yb)F_,4:0(KLCICPsdaeL.KLCICPylraE

.#POTS_ICP

.zHM6.66rozHM001gnilbanerofniptceleS

.)zHM3.33suonorhcnyssyawlaICP(zHM6.66=L,zHM001=H

71#DPNI.ffodenruteratuptuolla,sLLPlanretnI.pihcnwodsrewoP

81#POTS_UPCNI.wolsitupninehwlevel"0"cigolta)0:2(KLCUPCstlaH

91#POTS_ICPNI

02DNGRWP.erocLLProfdnuorG

12CLDDVRWPV5.2yllanimon,stuptuoUPCrofrewoP

42,32,22)0:2(KLCUPCTUOV5.2yllanimonstuptuokcolctsoHdnaUPC

52ALDDVRWP.CIPAOIrofrewoP

62CIPAOITUO.zHM813.41tuptuokcolcCIPAOI

721DDVRWP.stuptuoFERrofrewoP

820FERTUO.tuptuokcolczHM813.41

Note:

Inactive means outputs are held LOW and are disabled from switching

F_KLCICPdna

E_KLCICPtceffatonseoD.wolsitupninehwlevel"0"cigolta)4:0(KLCUPCstlaH

2

PS8546A 07/13/01

PI6C106

Pentium/ProTM System Clock Chip

CPU_STOP# Timing Diagram

CPUS_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
All other clocks will continue to run while the CPUCLKs clocks are disabled.
The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full
pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.

Internal

CPUCLK

PCICLK (0:4)

CPU_STOP#

PCI_STOP# (HIGH)

PD# (HIGH)

CPUCLK (0:2)

Notes:

1. All timing is referenced to the internal CPUCLK.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside PI6C106.

3. All other clocks continue to run undisturbed including SDRAMR.

4. PD# and PCI_STOP# are shown in a high (true) state.

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the PI6C106. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP#
is synchronized by the PI6C106 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed.
PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.

Internal

CPUCLK

Internal

PCICLK

PCICLK

(free-runningl)

CPU_STOP#

PCI_STOP#

PWR_DWN#

PCICLK

(external)

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the PI6C106 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the PI6C106.

3. All other clocks continue to run undisturbed.

4. PD# and CPU_STOP# are shown in a high (true) state.

3

PS8546A 07/13/01

PI6C106

Pentium/ProTM System Clock Chip

PD# Timing Diagram

The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internal by the PI6C106 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active
(low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed
to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are dont care signals during
the power down operations.

CPUCLK
(Internal)

PCICLK

(Internal)

PD#

CPUCLK

(0:2)

PCICLK_E, PCICLK_F,

PCICLK (0:4)

REF, IOAPIC

INTERNAL

VCOs

INTERNAL

CRYSTAL OSC.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the PI6C106 device).

2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the PI6C106.

3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.

4

PS8546A 07/13/01

Absolute Maximum Ratings

Supply Voltage ........................................................... 7.0 V

Logic Inputs ...............................GND 0.5 V to VDD +0.5 V

Ambient Operating Temperature .................. 0°C to +70°C

Storage Temperature ................................ 65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. These ratings arestress
specifications only and functional operation of the device at these
or any other conditions above those listed in theoperational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periodsmay affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0°C - 70°C; Supply Voltage VDD = V

retemaraPlobmySsnoitidnoC.niM.pyT.xaMstinU

egatloVhgiHtupnIV

egatloVwoLtupnIV

tnerruChgiHtupnII

tnerruCwoLtupnII

gnitarepO

tnerruCylppuS

ycneuqerFtupnIF

)1(

ecnaticapaCtupnI

)1(

emiTnoitisnarT

)1(

emiTgniltteS

)1(

noitazilibatSkcolC

HI

LI

HI

1LI

2LI

I

PO3.3DD

i

C

NI

C

XNI

T

snart

T

S

T

BATS

= 3.3 V ±5% (unless otherwise stated).

DDL

VNIV=

V

V

C

L

C

L

V

DD

NI

NI

zHM6.66;Fp0=001

zHM001;Fp0=001

V3.3=2161zHM

DD

stupnIcigoL5

snip2X&1X7254

VmorF

DD

srotsiserpu-lluponhtiwstupnI;V0=5

srotsiserpu-lluphtiwstupnI;V0=002

ycneuqerftegrat%1otgnissorctsrifoT3

ycneuqerftegrat%1otgnissorctsrifmorF2

ycneuqerftegrat%1otV3.3=3

PI6C106

Pentium/ProTM System Clock Chip

V

-0+

2

V

3.08.0

SS

DD

3.

V

5

AµtnerruCwoLtupnII

Am

Fp

sm

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0°C - 70°C; Supply Voltage VDD = 3.3 V ±5%, V

retemaraPlobmySsnoitidnoC.niM.pyT.xaMstinU

tnerruCylppuSgnitarepOI

tnerruCnwoDrewoPI

)1(

wekS

T

T

PO5.2DD

PO5.2DD

)4:0,F(ICP_UPC

)F(CICP-)E(ICP

Note: 1. Guaranteed by design, not 100% tested in production.

= 2.5V ±5% (unless otherwise stated).

DDL

C

L

C

L

V

T

V

V5.1=8.12.3

T

zHM8.66;Fp0=05

zHM001;Fp0=05

sdaeLUPC;V52.1/V5.1=5.14

5

Am

001Aµ

sn

PS8546A 07/13/01

Electrical Characteristics - CPU

TA = 0°C - 70°C; VDD = 3.3V ±5%, V

retemaraPlobmySsnoitidnoC.niM.pyT.xaMstinU

DDL

PI6C106

Pentium/ProTM System Clock Chip

= 2.5V ±5%; CL = 10-20pF (unless otherwise stated).

egatloVhgiHtuptuOV
egatloVwoLtuptuOV

tnerruChgiHtuptuOI
tnerruCwoLtuptuOI

emiTesiRt

emiTllaFt

elcyCytuDd

wekSt

)2(

tnemecalpsiDegdEelgniS,rettiJ

amgiSenO,rettiJt

etulosbA,rettijt

HO

LO

HO

LO

r

f

t

ks

t

desj

1j

sbaj

I

HO

I

LO

V

HO

V

LO

V

LO

V

HO

V

T

V

T

V

T

V

T

V

T

Am21=2
Am21=4.0
V7.1=61
V7.0=91

V,V4.0=

HO

V,V0.2=

LO

V52.1=5455%
V52.1=571

V52.1=052

V52.1=051
V52.1=003003

Notes:

1. Guaranteed by design, not 100% tested in production.

2. Edge displacement of a period relative to a 10-clock-cycle rolling average period

Electrical Characteristics - PCI

TA = 0°C - 70°C; VDD = V

= 3.3V ±10%, CL = 30pF (unless otherwise stated).

DDL

retemaraPlobmySsnoitidnoC.niM.pyT.xaMstinU

V

Am

V0.2=6.1

sn

V4.0=6.1

sp

egatloVhgiHtuptuOV
egatloVwoLtuptuOV

tnerruChgiHtuptuOI
tnerruCwoLtuptuOI

emiTesiRt

emiTllaFt

elcyCytuDd

wekSt

)2(

tnemecalpsiDegdEelgniS,rettiJ

etulosbA,rettijt

1HO

1LO

1HO

1LO

r

f

t

ks

t

desj

sbaj

I

HO

I

LO

V

HO

V

LO

V

LO

V

HO

V

T

V

T

V

T

V

T

V

T

Am11=6.2

Am4.9=4.0

V0.2=22

V8.0=61

V,V4.0=

V,V4.2=
V5.1=5455%
V5.1=005

V52.1=005

V5.1=052002
V5.1=052

Notes:

1. Guaranteed by design, not 100% tested in production.

V

Am

HO

V4.2=2

sn

V4.0=2

LO

sp

6

PS8546A 07/13/01

Electrical Characteristics - REF0

TA = 0°C - 70°C; VDD = V

= 3.3V ±10%, CL = 50pF (unless otherwise stated).

DDL

retemaraPlobmySsnoitidnoC.niM.pyT.xaMstinU

PI6C106

Pentium/ProTM System Clock Chip

egatloVhgiHtuptuOV
egatloVwoLtuptuOV

tnerruChgiHtuptuOI
tnerruCwoLtuptuOI

emiTesiRt

emiTllaFt

elcyCytuDd

,rettiJamgiSenOt

etulosbA,rettiJt

HO

LO

HO

LO

r

)1(

f

t

s1j

sbaj

I

HO

I
V
V
V
V
V

T

V

T

V

T

Am9=4.0

LO

HO

LO

LO

HO

V5.1=3555%
V5.1=3
V5.1=55

Electrical Characteristics - IOAPIC

TA = 0°C - 70°C; VDD = V

egatloVhgiHtuptuOV
egatloVwoLtuptuOV

tnerruChgiHtuptuOI
tnerruCwoLtuptuOI

emiTesiRt

emiTllaFt

elcyCytuDd

,rettiJamgiSenO

)1(

)1(

etulosbA,rettiJ

= 3.3V ±10%, CL = 20pF (unless otherwise stated).

DDL

retemaraPlobmySsnoitidnoC.niM.pyT.xaMstinU

HO

LO

HO

LO

2r

2f

2t

t

s1j

t

sbaj

I

HO

I

LO

V

HO

V

LO

V

LO

V

HO

V

T

V
V

V5.1=3

T

V5.1=66

T

Am21=6.2

V

V0.2=22

Am

V8.0=61

V,V4.0=

HO

V,V4.2=

V4.2=2

sn

V4.0=2

LO

sn

Am21=0.2

V

Am21=4.0
V7.1=61

Am

V7.0=91

V,V4.0=

HO

V,V0.2=

V0.2=6.1
V4.0=6.1

LO

sn

V52.1=5455%

sn

Electrical Characteristics - 48M

TA = 0°C - 70°C; VDD = V

egatloVhgiHtuptuOV
egatloVwoLtuptuOV

tnerruChgiHtuptuOI
tnerruCwoLtuptuOI

emiTesiRt

emiTllaFt

)1(

elcyCytuD

,rettiJamgiSenO

)1(

)1(

etulosbA,rettiJ

Note: 1. Guaranteed by design, not 100% tested in production.

= 3.3V ±5%, CL = 20pF (unless otherwise stated).

DDL

retemaraPlobmySsnoitidnoC.niM.pyT.xaMstinU

HO

LO

HO

LO

r

f

d

t

t

s1j

t

sbaj

I

HO

I

LO

V

HO

V

LO

V

LO

V

HO

V

T

V

T

V

T

Am11=4.2

V

Am4.9=4.0

V0.2=81

Am

V8.0=21

V,V4.0=

HO

V,V4.2=

V4.2=5.2
V4.0=5.2

LO

sn

V5.1=5455%
V5.1=3

sn

V5.1=66

7

PS8546A 07/13/01

28-Pin SSOP Package (H)

PI6C106

Pentium/ProTM System Clock Chip

Ordering Information

.oNtraPegakcaPN/PgniredrO

601C6IP)82-H(POSSH-601C6IP

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax [phone] • http://www.pericom.com

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PS8546A 07/13/01