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PI29FCT52/53T
REGISTERED TRANSCEIVERS
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PS2001A 03/08/96
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Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CE CP
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CE CP
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CPA
CEA
OEA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
CPB
CEB
OEB
A
REG
B
REG
PI29FCT52T and PI29FCT53T Logic Block Diagram
NOTE: PI29FCT52T function is shown.
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PI29FCT52T
PI29FCT53T
Fast CMOS
Registered Transceivers
Product Description:
Pericom Semiconductor’s PI29FCT series of logic circuits are produced in the Company’s advanced 0.8 micron CMOS technology,
achieving industry leading speed grades.
The PI29FCT52T and the PI29FCT53T are 8-bit registered
transceivers designed with two 8-bit back-to-back registers to store
data flowing in both directions between two bidirectional buses.
Separate clock enable and 3-state output enable signals are provided
for each register. The PI29FCT52T is a non-inverting option of the
PI29FCT53T.
Product Features:
• PI29FCT52/53T is pin compatible with bipolar FAST™
Series at a higher speed and lower power consumption
• TTL input and output levels
• Extremely low static power
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Packages available:
– 24-pin 300 mil wide plastic DIP (P)
– 24-pin 150 mil wide plastic QSOP (Q)
– 24-pin 150 mil wide plastic TQSOP (R)
– 24-pin 300 mil wide plastic SOIC (S)
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PI29FCT52/53T
REGISTERED TRANSCEIVERS
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PS2001A 03/08/96
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Pin Name Description
A0-A7 A Register Inputs or B Register Outputs
B0-B7 B Register Inputs or A Register Outputs
CPA Clock for A Register
CPB Clock for B Register
OEA Output Enable for B Register
OEB Output Enable for A Register
CEA Clock Enable for A Register
CEB Clock Enable for B Register
GND Ground
VCC Power
Product Pin Description
B7
B6
B5
B4
B3
B2
B1
B0
OEB
CPA
CEA
GND
V
CC
A7
A6
A5
A4
A3
A2
A1
A0
OEA
CPB
CEB
24-PIN
P24
Q24
R24
S24
PI29FCT52/53T Product Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Inputs Internal
Function DN CP CE QN
Hold Data X X H NC
Load Data L ↑ LL
H ↑ LH
PI29FCT52/53T Register Truth Table
(1)
(Applies to A or B Register)
Internal Y-Outputs
Function OE QN 52 53
Disable Outputs H X Z Z
Enable Outputs L L L H
LH H L
PI29FCT52/53T Output Control Table
(1)
1. H = High Voltage Level
L = Low Voltage Level
X = Don't Care
Z = High Impedance
NC = No Change
↑ = LOW-to-HIGH transition
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PI29FCT52/53T
REGISTERED TRANSCEIVERS
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PS2001A 03/08/96
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature....................................................................–65°C to +150°C
Ambient Temperature with Power Applied .....................................-40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .............. –0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only)...........–0.5V to +7.0V
DC Input Voltage ............................................................................ –0.5V to +7.0V
DC Output Current.....................................................................................120 mA
Power Dissipation ..........................................................................................0.5W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5V ± 5%)
Parameters Description Test Conditions
(1)
Min. Typ
(2)
Max. Units
VOH Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = –15.0 mA 2.4 3.0 V
VOL Output LOW Current VCC = Min., VIN = VIH or VIL IOL = 64 mA 0.3 0.55 V
VIH Input HIGH Voltage Guaranteed Logic HIGH Level 2.0 V
VIL Input LOW Voltage Guaranteed Logic LOW Level 0.8 V
IIH Input HIGH Current VCC = Max. VIN = VCC 1µA
IIL Input LOW Current VCC = Max. VIN = GND –1 µA
IOZH High Impedance VCC = Max. VOUT = 2.7V 1 µA
IOZL Output Current VOUT = 0.5V –1 µA
VIK Clamp Diode Voltage VCC = Min., IIN = –18 mA –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.
(3)
, VOUT = GN D –60 –120 m A
IOFF Power Down Disable VCC = GND, VOUT = 4.5V — — 100 µA
VH Input Hysteresis 200 m V
Capacitance (TA = 25°C, f = 1 MHz)
Parameters
(4)
Description Test Conditions Typ Max. Units
CIN Input Capacitance VIN = 0V 6 10 pF
COUT Output Capacitance VOUT = 0V 8 12 pF
Notes:
1 . For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
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REGISTERED TRANSCEIVERS
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Power Supply Characteristics
Parameters Description Test Conditions
(1)
Min. Ty p
(2)
Max. Units
ICC Quiescent Power VCC = Max. VIN = GND 0.1 500 µA
Supply Current or VCC
∆ICC Supply Current per VCC = Max. VIN = 3.4V
(3)
0.5 2.0 mA
Input @ TTL HIGH
ICCD Supply Current per VCC = Max., VIN = VCC 0.15 0.25 mA /
Input per MHz
(4)
Outputs Open VIN = GND MHz
OEA or OEB = GND
One Input Toggling
50% Duty Cycle
IC Total Power Supply VCC = Max., VIN = VCC 1.5 3.5
(5)
mA
Current
(6)
Outputs Open VIN = GND
fCP = 10 MHZ
50% Duty Cycle VIN = 3.4V 2.0 5.5
(5)
OEA or OEB = GND VIN = GND
fI = 5 MHZ
One Bit Toggling
VCC = Max., VIN = VCC 3.8 7.3
(5)
Outputs Open VIN = GND
fCP = 10 MHZ
50% Duty Cycle VIN = 3.4V 6.0 16.3
(5)
OEA or OEB = GND VIN = GND
Eight Bits Toggling
fI = 2.5 MHZ
50% Duty Cycle
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
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PI29FCT52/53T
REGISTERED TRANSCEIVERS
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PS2001A 03/08/96
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PI29FCT52T Switching Characteristics over Operating Range
29FCT52AT 29FCT52BT 29FCT52CT
Com. Com. Com.
Parameters Descr ipt io n Conditions
(1)
Min Max Min Max Min Max Unit
t
PLH
Propagation Delay CL = 50 pF 2.0 10.0 2.0 7.5 2.0 6.3 ns
t
PHL
CPA, CPB, to AN, B
N
RL = 500Ω
t
PZH
Output Enable Time 1 .5 10.5 1.5 8.0 1.5 7.0 ns
t
PZL
OEA, OEB, to AN, B
N
t
PHZ
Output Disable Time
(3)
1.5 10.0 1.5 7.5 1.5 6.5 ns
t
PLZ
OEA, OEB, to AN, B
N
t
SU
Set-up Time HIGH or 2.5 — 2.5 — 2.5 — ns
LOW, A
N
, BN to
CPA, CPB
t
H
Hold Time HIGH or 2.0 — 1.5 — 1.5 — ns
LOW, A
N
, BN to
CPA, CPB
t
SU
Set-up Time HIGH or 3.0 — 3.0 — 3.0 — ns
LOW, CEA, CEB to
CPA, CPB
t
H
Hold Time HIGH or 2.0 — 2.0 — 2.0 — ns
LOW, CEA, CEB to
CPA, CPB
t
W
Pulse Width HIGH
(3)
or 3.0 — 3.0 — 3.0 — ns
LOW, CPA or CPB
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
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PI29FCT52/53T
REGISTERED TRANSCEIVERS
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PS2001A 03/08/96
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PI29FCT53T Switching Characteristics over Operating Range
29FCT53AT 29FCT53BT 29FCT53CT
Com. Com. Com.
Parameters Descr ipt io n Conditions
(1)
Min Max Min Max Min Max Unit
t
PLH
Propagation Delay CL = 50 pF 2.0 10.0 2.0 7.5 2.0 6.3 ns
t
PHL
CPA, CPB, to AN, B
N
RL = 500Ω
t
PZH
Output Enable Time 1 .5 10.5 1.5 8.0 1.5 7.0 ns
t
PZL
OEA, OEB, to AN, B
N
t
PHZ
Output Disable Time
(3)
1.5 10.0 1.5 7.5 1.5 6.5 ns
t
PLZ
OEA, OEB, to AN, B
N
t
SU
Set-up Time HIGH or 2.5 — 2.5 — 2.5 — ns
LOW, A
N
, BN to
CPA, CPB
t
H
Hold Time HIGH or 2.0 — 1.5 — 1.5 — ns
LOW, A
N
, BN to
CPA, CPB
t
SU
Set-up Time HIGH or 3.0 — 3.0 — 3.0 — ns
LOW, CEA, CEB to
CPA, CPB
t
H
Hold Time HIGH or 2.0 — 2.0 — 2.0 — ns
LOW, CEA, CEB to
CPA, CPB
t
W
Pulse Width HIGH
(3)
or 3.0 — 3.0 — 3.0 — ns
LOW, CPA or CPB
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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