Datasheet PHX6ND50E Datasheet (Philips)

Philips Semiconductors Product specification

PowerMOS transistors PHX6ND50E
FREDFET, Avalanche energy rated

FEATURES SYMBOL QUICK REFERENCE DATA

• Repetitive Avalanche Rated V

d

• Fast switching

• Stable off-state characteristics I

• High thermal cycling performance

• Isolated package R

g

• Fast reverse recovery diode

s

GENERAL DESCRIPTION PINNING SOT186A

N-channel, enhancement mode PIN DESCRIPTION
field-effect power transistor,
incorporating a Fast Recovery 1 gate
Epitaxial Diode (FRED). This gives
improved switchingperformancein 2 drain
half bridge and full bridge
converters making this device 3 source
particularly suitable for inverters,
lighting ballasts and motor control case isolated
circuits.

The PHX6ND50Eissuppliedin the
SOT186A full pack, isolated
package.

= 500 V

DSS

= 3.1 A

D

≤ 1.5 Ω

DS(ON)

trr = 180 ns

case

123

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

I

DM

P

D

Tj, T

Drain-source voltage Tj = 25 ˚C to 150˚C - 500 V
Drain-gate voltage Tj = 25 ˚C to 150˚C; RGS = 20 kΩ - 500 V
Gate-source voltage - ± 30 V
Continuous drain current Ths = 25 ˚C; VGS = 10 V - 3.1 A

Ths = 100 ˚C; VGS = 10 V - 2 A
Ths = 25 ˚C - 24 A

Pulsed drain current

1

Total dissipation Ths = 25 ˚C - 35 W
Operating junction and - 55 150 ˚C

stg

storage temperature range

August 1998 1 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHX6ND50E
FREDFET, Avalanche energy rated

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

E

AR

IAS, I

ISOLATION LIMITING VALUE & CHARACTERISTIC

Ths = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

isol

C

isol

Non-repetitive avalanche Unclamped inductive load, IAS = 4 A; - 280 mJ
energy tp = 0.17 ms; Tj prior to avalanche = 25˚C;

VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer
to fig:17

Repetitive avalanche energy1IAR = 5.9 A; tp = 1 µs; Tj prior to - 10 mJ

avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V;
refer to fig:18

Repetitive and non-repetitive - 5.9 A

AR

avalanche current

R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal - 2500 V
three terminals to external waveform;
heatsink R.H. ≤ 65% ; clean and dustfree

Capacitance from T2 to external f = 1 MHz - 10 - pF
heatsink

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R
R

th j-hs

th j-a

Thermal resistance junction with heatsink compound - - 3.6 K/W
to heatsink
Thermal resistance junction - 55 - K/W
to ambient

1 pulse width and repetition rate limited by Tj max.

August 1998 2 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHX6ND50E
FREDFET, Avalanche energy rated

ELECTRICAL CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

∆V
∆T

R

DS(ON)

V

GS(TO)

g

fs

I

DSS

I

GSS

Q

g(tot)

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

d

L

s

C

iss

C

oss

C

rss

(BR)DSS

j

Drain-source breakdown VGS = 0 V; ID = 0.25 mA 500 - - V
voltage

/ Drain-source breakdown VDS = VGS; ID = 0.25 mA - 0.1 - %/K

voltage temperature
coefficient
Drain-source on resistance VGS = 10 V; ID = 3 A - 1.2 1.5 Ω
Gate threshold voltage VDS = VGS; ID = 0.25 mA 2.0 3.0 4.0 V
Forward transconductance VDS = 30 V; ID = 3 A 2 3.6 - S
Drain-source leakage current VDS = 500 V; VGS = 0 V - 1 25 µA

VDS = 400 V; VGS = 0 V; Tj = 125 ˚C - 30 250 µA

Gate-source leakage current VGS = ±30 V; VDS = 0 V - 10 200 nA
Total gate charge ID = 6 A; V

= 400 V; VGS = 10 V - 53 64 nC

DD

Gate-source charge - 4 6 nC
Gate-drain (Miller) charge - 28 34 nC

Turn-on delay time VDD = 250 V; RD = 39 Ω; - 10 - ns
Turn-on rise time RG = 12 Ω -33-ns
Turn-off delay time - 92 - ns
Turn-off fall time - 40 - ns

Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 610 - pF
Output capacitance - 96 - pF
Feedback capacitance - 54 - pF

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

I

rrm

Continuous source current Ths = 25˚C - - 5.9 A
(body diode)
Pulsed source current (body Ths = 25˚C - - 24 A
diode)
Diode forward voltage IS = 6 A; VGS = 0 V - - 1.5 V

Reverse recovery time IS = 6 A; VGS = 0 V; dI/dt = 100 A/µs - 180 - ns

IS = 6 A; VGS = 0 V; dI/dt = 100 A/µs; - 220 - ns
125˚C

Reverse recovery charge IS = 6 A; VGS = 0 V; dI/dt = 100 A/µs - 0.65 - µC

IS = 6 A; VGS = 0 V; dI/dt = 100 A/µs; - 2.6 - µC

125˚C
Peak reverse recovery IS = 6 A; VGS = 0 V; dI/dt = 100 A/µs; - 15 - A
current 125˚C

August 1998 3 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHX6ND50E
FREDFET, Avalanche energy rated

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Normalised Power Derating

with heatsink compound

Ths / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

with heatsink compound

Ths / C

= f(Ths)

D 25 ˚C

Normalised Current Derating

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Ths); conditions: VGS ≥ 10 V

D 25 ˚C

Zth j-hs, Transient thermal impedance (K/W)

10

D = 0.5

1

0.2

0.1

0.05

0.02

0.1

0.01
single pulse

0.001
1us

10us 100us

tp, pulse width (s)

P

D

1ms 1s

10ms 100ms

PHX2N60

t

p

t

D =

T

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-hs

ID, Drain current (Amps)

15

Tj = 25 C

10

5

0

0 5 10 15 20 25 30

VDS, Drain-Source voltage (Volts)

PHP4N50

7 V

VGS = 4.5 V

Fig.5. Typical output characteristics

ID = f(VDS); parameter V

GS

p

t

10 V

6.5 V

6 V

5.5 V

5 V

.

7 V

GS

PHP4N50
Tj = 25 C

10 V

.

ID, Drain current (Amps)

100

10

RDS(ON) = VDS/ID

1

DC

0.1

0.01
1 10 100 1000 10000

VDS, Drain-source voltage (Volts)

PHX4N50

tp = 10 us

100 us
1 ms

10 ms

100 ms

Fig.3. Safe operating area. Ths = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

RDS(on), Drain-Source on resistance (Ohms)

4

4.5 V

3

2

1

0

0 5 10 15

5.5 V

5 V

ID, Drain current (Amps)

VGS = 6 V

6.5 V

Fig.6. Typical on-state resistance

R

p

= f(ID); parameter V

DS(ON)

August 1998 4 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHX6ND50E
FREDFET, Avalanche energy rated

ID, Drain current (Amps)

15

VDS > ID x RDS(on)max

10

5

Tj = 150 C

0

0246810

VGS, Gate-Source voltage (Volts)

Tj = 25 C

PHP4N50

Fig.7. Typical transfer characteristics.

ID = f(VGS); parameter T

gfs, Transconductance (S)

6

VDS > ID x RDS(on)max

5

Tj = 25 C

4

3

2

1

150 C

j

PHP4N50

VGS(TO) / V

4

3

2

1

0

-60 -40 -20 0 20 40 60 80 100 120 140

max.

typ.

min.

Tj / C

Fig.10. Gate threshold voltage

V

= f(Tj); conditions: ID = 0.25 mA; VDS = V

GS(TO)

1E-01

1E-02

1E-03

1E-04

1E-05

ID / A

SUB-THRESHOLD CONDUCTION

2 %

typ

.

GS

98 %

0

0 5 10 15

Fig.8. Typical transconductance

a

2

1

0

-60 -40 -20 0 20 40 60 80 100 120 140

ID, Drain current (A)

gfs = f(ID); parameter T

Normalised RDS(ON) = f(Tj)

Tj / C

.

j

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj); ID = 3 A; VGS = 10 V

1E-06

0 1 2 3 4

VGS / V

Fig.11. Sub-threshold drain current.

ID = f(V

Junction capacitances (pF)

1000

100

10

1 10 100 1000

Fig.12. Typical capacitances, C

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

; conditions: Tj = 25 ˚C; VDS = V

GS)

Ciss

Coss

Crss

VDS, Drain-Source voltage (Volts)

, C

iss

PHP4N50

oss

, C

GS

rss

.

August 1998 5 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHX6ND50E
FREDFET, Avalanche energy rated

VGS, Gate-Source voltage (Volts)

15

ID = 6 A
Tj = 25 C

10

5

0

0 1020304050607080

Qg, Gate charge (nC)

250 V

100 V

PHP4N50

VDD = 400 V

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); parameter V

GS

Switching times (ns)

1000

VDD = 250 V
VGS = 10 V
RD = 39 Ohms
Tj = 25 C

100

td(off)

tf
tr

td(on)

10

1

0 102030405060

RG, Gate resistance (Ohms)

Fig.14. Typical switching times; t

d(on)

DS

, tr, t

PHP4N50

, tf = f(RG)

d(off)

IF, Source-Drain diode current (Amps)

20

VGS = 0 V

15

10

5

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4

VSDS, Source-Drain voltage (Volts)

150 C

PHP4N50

Tj = 25 C

Fig.16. Source-Drain diode characteristic.

IF = f(V

Non-repetitive Avalanche current, IAS (A)

10

Tj prior to avalanche = 125 C

1

VDS

tp

ID

0.1
1E-06 1E-05 1E-04 1E-03 1E-02

); parameter T

SDS

Avalanche time, tp (s)

j

25 C

PHP6N50E

Fig.17. Maximum permissible non-repetitive

avalanche current (IAS) versus avalanche time (tp);

unclamped inductive load

Normalised Drain-source breakdown voltage

1.15

V(BR)DSS @ Tj
V(BR)DSS @ 25 C

1.1

1.05

1

0.95

0.9

0.85

-100 -50 0 50 100 150
Tj, Junction temperature (C)

Fig.15. Normalised drain-source breakdown voltage

V

(BR)DSS/V(BR)DSS 25 ˚C

= f(Tj)

;

Maximum Repetitive Avalanche Current, IAR (A)

10

Tj prior to avalanche = 25 C

1

0.1

0.01
1E-06 1E-05 1E-04 1E-03 1E-02

Avalanche time, tp (s)

125 C

PHP6N50E

Fig.18. Maximum permissible repetitive avalanche

current (IAR) versus avalanche time (tp)

August 1998 6 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHX6ND50E
FREDFET, Avalanche energy rated

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

10.3

Recesses (2x)

2.5

0.8 max. depth

3 max.

not tinned

13.5
min.

0.4

M

max

3.2

3.0

123

5.08

2.8

2.54

15.8

max.

3

19

max.

seating

plane

0.5

2.5

4.6

max

2.9 max

6.4

0.6

2.5

15.8
max

Fig.19. SOT186A; The seating plane is electrically isolated from all terminals.

1.3

1.0 (2x)

0.9

0.7

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for F-pack envelopes.

3. Epoxy meets UL94 V0 at 1/8".

August 1998 7 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHX6ND50E
FREDFET, Avalanche energy rated

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

August 1998 8 Rev 1.100