Datasheet PHP87N03LT Datasheet (Philips)

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP87N03LT, PHB87N03LT
Logic level FET PHD87N03LT

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology V

d

= 25 V

DSS

• Very low on-state resistance

• Fast switching I

= 75 A

D

• Low thermal resistance

• Logic level compatible R

g

R

s

≤ 9.5 mΩ (VGS = 10 V)

DS(ON)

≤ 10.5 mΩ (VGS = 5 V)

DS(ON)

GENERAL DESCRIPTION

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-

• High frequency computer motherboard d.c. to d.c. converters

• High current switching
The PHP87N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB87N03LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD87N03LT is supplied in the SOT428 (DPAK)surface mounting package.

PINNING SOT78 (TO220AB) SOT404 (D2PAK) SOT428 (DPAK)

PIN DESCRIPTION

1 gate
2 drain

1

3 source

tab drain

tab

123

tab

2

13

tab

2

1

3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

V

GSM

I

D

I

DM

P

tot

Tj, T

1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.

October 1999 1 Rev 1.600

Drain-source voltage Tj = 25 ˚C to 175˚C - 25 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -25V
Gate-source voltage (DC) - ± 15 V
Gate-source voltage (pulse Tj ≤ 150 ˚C - ± 20 V
peak value)
Drain current (DC) Tmb = 25 ˚C - 75 A

Tmb = 100 ˚C - 61 A
Drain current (pulse peak Tmb = 25 ˚C - 240 A
value)
Total power dissipation Tmb = 25 ˚C - 142 W
Operating junction and - 55 175 ˚C

stg

storage temperature

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP87N03LT, PHB87N03LT

Logic level FET PHD87N03LT

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

R

th j-a

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

W

DSS

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

Thermal resistance junction - - 1.05 K/W
to mounting base
Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 or SOT428 package, pcb - 50 - K/W

mounted, minimum footprint

Drain-source non-repetitive ID = 45 A; VDD ≤ 15 V; - 200 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 25 - - V
voltage Tj = -55˚C 22 - - V

V

GS(TO)

Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V

R

DS(ON)

Drain-source on-state VGS = 5 V; ID = 25 A - 9 10.5 mΩ
resistance VGS = 10 V; ID = 25 A - 8.5 9.5 mΩ

VGS = 5 V; ID = 25 A; Tj = 175˚C - - 19.5 mΩ

g
I
I

fs
GSS
DSS

Forward transconductance VDS = 25 V; ID = 25 A 12 51 - S
Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA
Zero gate voltage drain VDS = 25 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA

Q
Q
Q

t
t
t
t

L
L

g(tot)
gs
gd

d on
r
d off
f

d

d

Total gate charge ID = 75 A; V

= 15 V; VGS = 5 V - 39 - nC

DD

Gate-source charge - 9 - nC
Gate-drain (Miller) charge - 18.5 - nC

Turn-on delay time VDD = 15 V; ID = 25 A; - 9 15 ns
Turn-on rise time VGS = 10 V; RG = 5 Ω -5470ns
Turn-off delay time Resistive load - 136 160 ns
Turn-off fall time - 85 100 ns

Internal drain inductance Measured tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)

L

s

Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

C

iss

C

oss

C

rss

Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 2304 - pF
Output capacitance - 620 - pF
Feedback capacitance - 448 - pF

October 1999 2 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP87N03LT, PHB87N03LT

Logic level FET PHD87N03LT

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current - - 75 A
(body diode)
Pulsed source current (body - - 240 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.85 1.2 V

IF = 40 A; VGS = 0 V - 0.9 -

Reverse recovery time IF = 20 A; -dIF/dt = 100 A/µs; - 109 - ns
Reverse recovery charge VGS = 0 V; VR = 25 V - 0.2 - µC

Normalised Power Derating, PD (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

Normalised Current Derating, ID (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

D 25 ˚C

= f(Tmb)

Peak Pulsed Drain Current, IDM (A)

1000

RDS(on) = VDS/ ID

100

10

1

1 10 100

D.C.

Drain-Source Voltage, VDS (V)

tp = 10 us

100 us

1 ms

10 ms
100 ms

Fig.3. Safe operating area

ID & IDM = f(VDS); IDM single pulse; parameter t

Transient thermal impedance, Zth j-mb (K/W)

10

1

D = 0.5

0.2

0.1

0.1

0.05

0.02

0.01

single pulse

1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00

Pulse width, tp (s)

P

D

D = tp/T

tp

T

p

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); VGS ≥ 5 V

D 25 ˚C

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

October 1999 3 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP87N03LT, PHB87N03LT
Logic level FET PHD87N03LT

Drain Current, ID (A)

50

VGS = 10V

45

5 V

40

4.5 V

35
30
25
20
15
10

5
0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

2.8 V

3 V

Drain-Source Voltage, VDS (V)

Tj = 25 C

2.6 V

2.4 V

2.2 V

2 V

Fig.5. Typical output characteristics, Tj = 25 ˚C

ID = f(VDS)

Drain-Source On Resistance, RDS(on) (Ohms)

0.05
2 V

0.045

0.04

0.035

0.03

0.025

0.02

0.015

0.01

0.005
0

2.2 V

0 5 10 15 20 25 30 35 40 45 50

2.4 V

Drain Current, ID (A)

2.6 V

5 V

Tj = 25 C

2.8V

3 V

4.5 V

VGS = 10V

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

= f(ID)

DS(ON)

Transconductance, gfs (S)

60
55
50
45
40
35
30
25
20
15
10

5
0

0 5 10 15 20 25 30 35 40

.

Fig.8. Typical transconductance, Tj = 25 ˚C

Tj = 25 C

175 C

Drain current, ID (A)

VDS > ID X RDS(ON)

.

gfs = f(ID)

Normalised On-state Resistance

2

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1
1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1
0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

.

Fig.9. Normalised drain-source on-state resistance.

Junction temperature, Tj (C)

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj)

Drain current, ID (A)

50

VDS > ID X RDS(ON)

45
40
35
30
25
20
15
10

5
0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

175 C

Tj = 25 C

Gate-source voltage, VGS (V)

Fig.7. Typical transfer characteristics.

ID = f(VGS)

Threshold Voltage, VGS(TO) (V)

2.25

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)

maximum

typical

minimum

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

GS

October 1999 4 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP87N03LT, PHB87N03LT
Logic level FET PHD87N03LT

Drain current, ID (A)

1.0E-01
VDS = 5 V

1.0E-02

1.0E-03

1.0E-04

1.0E-05

1.0E-06

minimum typical maximum

0 0.5 1 1.5 2 2.5 3

Gate-source voltage, VGS (V)

Fig.11. Sub-threshold drain current.

ID = f(V

; conditions: Tj = 25 ˚C; VDS = V

GS)

GS

Gate-source voltage, VGS (V)

15

ID = 75A

14
13

Tj = 25 C

12

VDD = 15 V

11
10

9
8
7
6
5
4
3
2
1
0

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

Gate charge, QG (nC)

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG)

GS

Capacitances, Ciss, Coss, Crss (pF)

10000

1000

100

0.1 1 10 100

Fig.12. Typical capacitances, C

Drain-Source Voltage, VDS (V)

, C

iss

oss

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

Ciss

Coss

Crss

, C

rss

100

IF / A

9510-30

80

60

Tj / C = 175 25

40

20

0

0 0.5 1 1.5 2

.

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

VSDS / V

= 0 V; parameter T

GS

j

October 1999 5 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP87N03LT, PHB87N03LT

Logic level FET PHD87N03LT

MECHANICAL DATA

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78

AE

P

A

1

D

1

D

(1)

L

2

b

1

L

DIMENSIONS (mm are the original dimensions)

b

A

UNIT

mm

Note

1. Terminals in this zone are not tinned.

OUTLINE
VERSION

SOT78 TO-220

A

1

4.5

1.39

4.1

1.27

b

c

1

0.9

0.7

IEC JEDEC EIAJ

0.7

1.3

0.4

1.0

123

e

e

0 5 10 mm

D

D

1

15.8

6.4

15.2

5.9

REFERENCES

q

L

1

Q

L

2

max.

3.0

(1)

c

qQ

P

3.8

3.0

3.6

2.7

EUROPEAN

PROJECTION

2.6

2.2

ISSUE DATE

97-06-11

b

scale

e

10.3

9.7

E

2.54

15.0

13.5

L

L

1

3.30

2.79

Fig.15. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to mounting instructions for SOT78 (TO220AB) package.

3. Epoxy meets UL94 V0 at 1/8".

October 1999 6 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP87N03LT, PHB87N03LT

Logic level FET PHD87N03LT

MECHANICAL DATA

Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)

base

A

1

L

p

c

Q

E

D

1

D

H

D

2

13

b

e e

0 2.5 5 mm

scale

mounting

SOT404

A

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

A

4.50

4.10

OUTLINE
VERSION

SOT404

b

1

1.40

0.85

1.27

0.60

IEC JEDEC EIAJ

0.64

0.46

max.

11

D

D

1

1.60

1.20

REFERENCES

10.30

9.70

E

eLpHDQc

2.60

15.40

2.90

2.54

2.10

14.80

2.20

EUROPEAN

PROJECTION

ISSUE DATE

98-12-14
99-06-25

Fig.16. SOT404 surface mounting package. Centre pin connected to mounting base.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.

3. Epoxy meets UL94 V0 at 1/8".

October 1999 7 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP87N03LT, PHB87N03LT

Logic level FET PHD87N03LT

MOUNTING INSTRUCTIONS

Dimensions in mm

11.5

9.0

17.5

2.0

3.8

5.08

Fig.17. SOT404 : soldering pattern for surface mounting

.

October 1999 8 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP87N03LT, PHB87N03LT

Logic level FET PHD87N03LT

MECHANICAL DATA

Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)

SOT428

seating plane

E

b

2

L

2

2

A

D

L

A

1

mounting

base

H

E

L

1

y

A

A

2

E

1

D

1

13

b

1

e

e

1

DIMENSIONS (mm are the original dimensions)

A

(1)

A

UNIT

mm

Note

1. Measured from heatsink back to lead.

A

1

max.

0.65

2.38

0.45

2.22

OUTLINE

VERSION

SOT428 98-04-07

b

2

0.89

0.71

max.

0.89

1.1

0.71

0.9

IEC JEDEC EIAJ

wA

M

bc

0 10 20 mm

scale

b

1

b

c

2

5.36

0.4

5.26

0.2

D

D

max.

max.

6.22

4.81

5.98

4.45

REFERENCES

E

E

max.

6.73

6.47

min.

4.0

1

2.285

ee

1

4.57

max.

1

H

10.4

9.6

E

L

L

min.

2.95

0.5

2.55

EUROPEAN

PROJECTION

1

L

2

0.7

0.5

w

max.

0.2 0.2

ISSUE DATE

y

Fig.18. SOT428 surface mounting package. Centre pin connected to mounting base.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.

3. Epoxy meets UL94 V0 at 1/8".

October 1999 9 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP87N03LT, PHB87N03LT

Logic level FET PHD87N03LT

MOUNTING INSTRUCTIONS

Dimensions in mm

7.0

7.0

2.15

2.5

4.57

1.5

Fig.19. SOT428 : soldering pattern for surface mounting

.

October 1999 10 Rev 1.600

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHP87N03LT, PHB87N03LT

Logic level FET PHD87N03LT

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

October 1999 11 Rev 1.600