Datasheet PHF9NQ20T, PHX9NQ20T Datasheet (Philips)

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology

• Low on-state resistance V

d

= 200 V

DSS

• Fast switching

• Low thermal resistance I

g

s

R

DS(ON)

= 5.2 A

D

≤ 400 mΩ

GENERAL DESCRIPTION

N-channel, enhancement mode field-effect power transistor using Trench technology, intended for use in off-line
switchedmodepowersupplies, T.V. andcomputermonitorpowersupplies, d.c. tod.c.converters,motor control circuits
and general purpose switching applications.

The PHX9NQ20T is supplied in the SOT186A (FPAK) conventional leaded package

PINNING SOT186A (FPAK) SOT186 (FPAK)

PIN DESCRIPTION

1 gate

case

2 drain
3 source

case

case isolated

123

123

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

I

DM

P

D

Tj, T

Drain-source voltage Tj = 25 ˚C to 175˚C - 200 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 200 V
Gate-source voltage - ± 20 V
Continuous drain current Ths = 25 ˚C; VGS = 10 V - 5.2 A

Ths = 100 ˚C; VGS = 10 V - 3.3 A
Pulsed drain current Ths = 25 ˚C - 21 A
Total power dissipation Ths = 25 ˚C - 25 W
Operating junction and - 55 150 ˚C

stg

storage temperature

November 2000 1 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

I

AS

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-hs

R

th j-a

Non-repetitive avalanche Unclamped inductive load, IAS = 7.2A; - 93 mJ
energy tp = 100 µs; Tj prior to avalanche = 25˚C;

VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer

to fig;15
Peak non-repetitive - 8.7 A
avalanche current

Thermal resistance junction - - 5 K/W
to mounting base
Thermal resistance junction SOT186A package, in free air - 55 - K/W
to ambient

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

R

DS(ON)

g

fs

I

GSS

I

DSS

Q

g(tot)

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

s

C

iss

C

oss

C

rss

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 200 - - V
voltage Tj = -55˚C 178 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 2 3 4 V

Tj = 150˚C 1 - - V

Tj = -55˚C - 6 V
Drain-source on-state VGS = 10 V; ID = 4.5 A - 300 400 mΩ
resistance Tj = 150˚C - - 0.94 Ω
Forward transconductance VDS = 25 V; ID = 4.5 A 3.8 6 - S
Gate source leakage current VGS = ± 10 V; VDS = 0 V - 10 100 nA
Zero gate voltage drain VDS = 200 V; VGS = 0 V - 0.05 10 µA
current Tj = 150˚C - - 500 µA

Total gate charge ID = 9 A; V

= 160 V; VGS = 10 V - 24 - nC

DD

Gate-source charge - 4 - nC
Gate-drain (Miller) charge - 12 - nC

Turn-on delay time VDD = 100 V; RD = 10 Ω;-8-ns
Turn-on rise time VGS = 10 V; RG = 5.6 Ω -19-ns
Turn-off delay time Resistive load - 25 - ns
Turn-off fall time - 15 - ns

Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 959 - pF
Output capacitance - 93 - pF
Feedback capacitance - 54 - pF

November 2000 2 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

ISOLATION LIMITING VALUE & CHARACTERISTIC

Ths = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

isol

V

isol

C

isol

Continuous source current - - 8.7 A
(body diode)
Pulsed source current (body - - 35 A
diode)
Diode forward voltage IF = 9 A; VGS = 0 V - 0.85 1.2 V

Reverse recovery time IF = 9 A; -dIF/dt = 100 A/µs; - 92 - ns
Reverse recovery charge VGS = -10 V; VR = 25 V - 0.5 - µC

R.M.S. isolation voltage from all SOT186A package; f = 50-60 Hz; - 2500 V
three terminals to external sinusoidal waveform; R.H. ≤ 65%;
heatsink clean and dustfree

Repetitive peak voltage from all SOT186 package; R.H. ≤ 65%; - 1500 V
three terminals to external clean and dustfree
heatsink

Capacitance from pin 2 to f = 1 MHz - 10 - pF
external heatsink

November 2000 3 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Normalised Power Derating

with heatsink compound

Ths / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Ths / C

= f(Tmb)

D 25 ˚C

Normalised Current Derating

with heatsink compound

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); VGS ≥ 10 V

D 25 ˚C

Transient thermal impedance, Zth j-a (K/W)

10

D = 0.5

0.2

1

0.1

0.05

0.1

0.01

0.02

single pulse

1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01

Pulse width, tp (s)

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

Drain Current, ID (A)

10

Tj = 25 C VGS = 10V

9
8
7
6
5
4
3
2
1
0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Drain-Source Voltage, VDS (V)

8 V

6 V

5.5 V

5 V

4.5 V

Fig.5. Typical output characteristics, Tj = 25 ˚C.

ID = f(VDS)

Peak Pulsed Drain Current, IDM (A)

100

RDS(on) = VDS/ ID

10

tp = 10 us

100us

1

D.C.

0.1
1 10 100 1000

Drain-Source Voltage, VDS (V)

1 ms
10 ms
100 ms

Fig.3. Safe operating area

ID & IDM = f(VDS); IDM single pulse; parameter t

p

Drain-Source On Resistance, RDS(on) (Ohms)

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

4.5 V

0

012345678910

5 V

Drain Current, ID (A)

8 V

Tj = 25 C

5.5 V
6 V

VGS = 10V

Fig.6. Typical on-state resistance, Tj = 25 ˚C.

R

= f(ID)

DS(ON)

November 2000 4 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T

Drain current, ID (A)

10

9
8
7
6
5
4
3
2
1
0

0123456

Gate-source voltage, VGS (V)

150 C

Tj = 25 C

Fig.7. Typical transfer characteristics.

ID = f(VGS)

Transconductance, gfs (S)

14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

012345678910

Tj = 25 C

150 C

ID / (A)

Fig.8. Typical transconductance, Tj = 25 ˚C.

gfs = f(ID)

Threshold Voltage, VGS(TO) (V)

4.5
4

3.5
3

2.5
2

1.5
1

0.5
0

-60 -40 -20 0 20 40 60 80 100 120 140 160

Junction Temperature, Tj (C)

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

Drain current, ID (A)

1.0E-01

1.0E-02

1.0E-03

1.0E-04

1.0E-05

1.0E-06
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

minimum

typical

Gate-source voltage, VGS (V)

Fig.11. Sub-threshold drain current.

ID = f(V

; conditions: Tj = 25 ˚C

GS)

GS

maximum

Normalised On-state Resistance

2.5

2

1.5

1

0.5

0

-60 -40 -20 0 20 40 60 80 100 120 140 160

Junction Temperature, Tj C

Fig.9. Normalised drain-source on-state resistance.

R

DS(ON)/RDS(ON)25 ˚C

= f(Tj)

Capacitances, Ciss, Coss, Crss (pF)

10000

1000

100

10

0.1 1 10 100

Fig.12. Typical capacitances, C

Drain-Source Voltage, VDS (V)

iss

, C

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

oss

Coss

, C

Ciss

Crss

.

rss

November 2000 5 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T

Gate-source voltage, VGS (V)

15
14

ID = 9 A

13

Tj = 25 C

12
11
10

9
8
7
6
5
4
3
2
1
0

0 5 10 15 20 25 30 35

VDD = 40 V

VDD = 160 V

Gate charge, QG (nC)

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG)

GS

Source-Drain Diode Current, IF (A)

10

9

VGS = 0 V

8
7
6
5
4
3
2
1
0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

Source-Drain Voltage, VSDS (V)

150 C

Tj = 25 C

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

= 0 V; parameter T

GS

j

Maximum Avalanche Current, I

10

1

0.1

0.001 0.01 0.1 1 10

Tj prior to avalanche = 150 C

Avalanche time, t

(A)

AS

25 C

(ms)

AV

Fig.15. Maximum permissible non-repetitive

avalanche current (IAS) versus avalanche time (tAV);

unclamped inductive load

November 2000 6 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220 SOT186A

E
P

q

D

1

D

L

2

b

1

L

b

2

23

1

b

e

e

1

T

L

1

w

M

A

A

1

j

K

Q

c

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

10.3

9.7

e

E

2.54

e

5.08

j

1

2.7

0.6

2.3

0.4

A

A

b

UNIT

mm

Notes

1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned.

2. Both recesses are ∅ 2.5 × 0.8 max. depth

OUTLINE
VERSION

SOT186A TO-220

4.6

4.0

2.9

2.5

1

b

1

1.1

0.9

0.9

0.7

IEC JEDEC EIAJ

1.4

1.2

c

b

2

0.7

0.4

15.8

15.2

D

D

1

6.5

6.3

REFERENCES

K

14.4

13.5

L

3.30

2.79

1

(1)

L

2

max.

3.2

3

3.0

EUROPEAN

PROJECTION

2.6

2.3

(2)

qQPL

T

3.0

2.5 0.4

2.6

ISSUE DATE

97-06-11

w

Fig.16. SOT186A; The seating plane is electrically isolated from all terminals.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for F-pack envelopes.

3. Epoxy meets UL94 V0 at 1/8".

November 2000 7 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

Plastic single-ended package; isolated heatsink mounted;
1 mounting hole; 3 lead TO-220 exposed tabs SOT186

E

E

1

P

D

1

D

b

1

L

L

2

23

1

b

e

e

1

m

q

L

1

w

M

A

A

1

Q

c

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

A

2.9

2.5

b

1

0.9

0.7

UNIT

4.4

mm

4.0

Note

1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned.

OUTLINE

VERSION

SOT186 TO-220

c

b

1

1.5

0.55

1.3

0.38

IEC JEDEC EIAJ

17.0

16.4

D

D

E

1

7.9

10.2

7.5

9.6

REFERENCES

e

E

1

5.7

5.3

2.54

e

5.08

1

14.3

13.5

(1)

L

1

4.8

4.0

m

L

2

3.2

0.9

10 0.4

3.0

0.5

EUROPEAN

PROJECTION

1.4

1.2

qQPL

w

4.4

4.0

ISSUE DATE

97-06-11

Fig.17. SOT186; The seating plane is electrically isolated from all terminals.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for F-pack envelopes.

3. Epoxy meets UL94 V0 at 1/8".

November 2000 8 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PHX9NQ20T , PHF9NQ20T

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 2000

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

November 2000 9 Rev 1.100