Datasheet PHD4ND40E, PHP4ND40E Datasheet (Philips)

Philips Semiconductors Product specification

PowerMOS transistors PHP4ND40E, PHB4ND40E
FREDFET, Avalanche energy rated

FEATURES SYMBOL QUICK REFERENCE DATA

• Repetitive Avalanche Rated V

DSS

= 400 V

• Fast switching

• Stable off-state characteristics I

D

= 4.4 A

• High thermal cycling performance

• Low thermal resistance R

DS(ON)

≤ 1.8 Ω

• Fast reverse recovery diode

trr = 180 ns

GENERAL DESCRIPTION

N-channel, enhancement mode field-effect power transistor, incorporating a Fast Recovery Epitaxial Diode (FRED).
This gives improved switching performance in half bridge ansd full bridge converters making this device particularly
suitable for inverters, lighting ballasts and motor control circuits.

The PHP4ND40E is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB4ND40E is supplied in the SOT404 surface mounting package.

PINNING SOT78 (TO220AB) SOT404

PIN DESCRIPTION

1 gate
2 drain

1

3 source

tab drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

Drain-source voltage Tj = 25 ˚C to 150˚C - 400 V

V

DGR

Drain-gate voltage Tj = 25 ˚C to 150˚C; RGS = 20 kΩ - 400 V

V

GS

Gate-source voltage - ± 30 V

I

D

Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 4.4 A

Tmb = 100 ˚C; VGS = 10 V - 2.7 A

I

DM

Pulsed drain current Tmb = 25 ˚C - 18 A

P

D

Total dissipation Tmb = 25 ˚C - 83 W

Tj, T

stg

Operating junction and - 55 150 ˚C
storage temperature range

d

g

s

123

tab

13

tab

2

August 1998 1 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP4ND40E, PHB4ND40E
FREDFET, Avalanche energy rated

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

Non-repetitive avalanche Unclamped inductive load, IAS = 1.5 A; - 190 mJ
energy tp = 0.3 ms; Tj prior to avalanche = 25˚C;

VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer
to fig:17

E

AR

Repetitive avalanche energy1IAR = 4.4 A; tp = 1 µs; Tj prior to - 5.5 mJ

avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V;
refer to fig:18

IAS, I

AR

Repetitive and non-repetitive - 4.4 A
avalanche current

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

Thermal resistance junction - - 1.5 K/W
to mounting base

R

th j-a

Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 package, pcb mounted, minimum - 50 - K/W

footprint

1 pulse width and repetition rate limited by Tj max.

August 1998 2 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP4ND40E, PHB4ND40E
FREDFET, Avalanche energy rated

ELECTRICAL CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

Drain-source breakdown VGS = 0 V; ID = 0.25 mA 400 - - V
voltage

∆V

(BR)DSS

/ Drain-source breakdown VDS = VGS; ID = 0.25 mA - 0.1 - %/K

∆T

j

voltage temperature
coefficient

R

DS(ON)

Drain-source on resistance VGS = 10 V; ID = 2.2 A - 1.3 1.8 Ω

V

GS(TO)

Gate threshold voltage VDS = VGS; ID = 0.25 mA 2.0 3.0 4.0 V

g

fs

Forward transconductance VDS = 30 V; ID = 2.2 A 1.3 2.2 - S

I

DSS

Drain-source leakage current VDS = 400 V; VGS = 0 V - 1 25 µA

VDS = 320 V; VGS = 0 V; Tj = 125 ˚C - 30 250 µA

I

GSS

Gate-source leakage current VGS = ±30 V; VDS = 0 V - 10 200 nA

Q

g(tot)

Total gate charge ID = 4.4 A; V

DD

= 320 V; VGS = 10 V - 26 30 nC

Q

gs

Gate-source charge - 2 4 nC

Q

gd

Gate-drain (Miller) charge - 14 17 nC

t

d(on)

Turn-on delay time VDD = 200 V; RD = 47 Ω; - 10 - ns

t

r

Turn-on rise time RG = 18 Ω -30-ns

t

d(off)

Turn-off delay time - 55 - ns

t

f

Turn-off fall time - 38 - ns

L

d

Internal drain inductance Measured from tab to centre of die - 3.5 - nH

L

d

Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

(SOT78 package only)

L

s

Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

C

iss

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 310 - pF

C

oss

Output capacitance - 60 - pF

C

rss

Feedback capacitance - 36 - pF

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

Continuous source current Tmb = 25˚C - - 4.4 A
(body diode)

I

SM

Pulsed source current (body Tmb = 25˚C - - 18 A
diode)

V

SD

Diode forward voltage IS = 4.4 A; VGS = 0 V - - 1.5 V

t

rr

Reverse recovery time IS = 4.4 A; VGS = 0 V; dI/dt = 100 A/µs - 180 - ns

IS = 4.4 A; VGS = 0 V; dI/dt = 100 A/µs; - 220 - ns
125˚C

Q

rr

Reverse recovery charge IS = 4.4 A; VGS = 0 V; dI/dt = 100 A/µs - 0.65 - µC

IS = 4.4 A; VGS = 0 V; dI/dt = 100 A/µs; - 2.6 - µC
125˚C

I

rrm

Peak reverse recovery IS = 4.4 A; VGS = 0 V; dI/dt = 100 A/µs; - 15 - A
current 125˚C

August 1998 3 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP4ND40E, PHB4ND40E
FREDFET, Avalanche energy rated

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

D 25 ˚C

= f(Tmb)

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

D 25 ˚C

= f(Tmb); conditions: VGS ≥ 10 V

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

p

Fig.4. Transient thermal impedance.

Z

th j-mb

= f(t); parameter D = tp/T

Fig.5. Typical output characteristics

.

ID = f(VDS); parameter V

GS

Fig.6. Typical on-state resistance

.

R

DS(ON)

= f(ID); parameter V

GS

0 20 40 60 80 100 120 140

Tmb / C

PD%

Normalised Power Derating

120
110
100

90
80
70
60
50
40
30
20
10

0

PHP2N60

1ms 1s

Zth j-mb, Transient thermal impedance (K/W)

1us

10us 100us

10ms 100ms

tp, pulse width (s)

0.001

0.01

0.1

1

10

D =

t

p

t

p

T

T

P

t

D

D = 0.5

0.2

single pulse

0.05

0.02

0.1

0 20 40 60 80 100 120 140

Tmb / C

ID%

Normalised Current Derating

120
110
100

90
80
70
60
50
40
30
20
10

0

0 5 10 15 20 25 30

0

2

4

6

8

10

PHP4N40

VDS, Drain-Source voltage (Volts)

ID, Drain current (Amps)

5 V

6 V

6.5 V

7 V

10 V

5.5 V

VGS = 4.5 V

Tj = 25 C

10 100 1000 10000

0.1

1

10

100

PHP4N40

VDS, Drain-source voltage (Volts)

ID, Drain current (Amps)

100 us

1 ms

10 ms

RDS(ON) = VDS/ID

DC

tp = 10 us

0246810

0

1

2

3

4

PHP4N40

5 V 5.5 V

10 V

ID, Drain current (Amps)

RDS(on), Drain-Source on resistance (Ohms)

4.5 V 6 V
Tj = 25 C

6.5 V VGS = 7 V

August 1998 4 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP4ND40E, PHB4ND40E
FREDFET, Avalanche energy rated

Fig.7. Typical transfer characteristics.

ID = f(VGS); parameter T

j

Fig.8. Typical transconductance

.

gfs = f(ID); parameter T

j

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj); ID = 2.2 A; VGS = 10 V

Fig.10. Gate threshold voltage

.

V

GS(TO)

= f(Tj); conditions: ID = 0.25 mA; VDS = V

GS

Fig.11. Sub-threshold drain current.

ID = f(V

GS)

; conditions: Tj = 25 ˚C; VDS = V

GS

Fig.12. Typical capacitances, C

iss

, C

oss

, C

rss

.

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

0246810

0

2

4

6

8

10

PHP4N40

VGS, Gate-Source voltage (Volts)

ID, Drain current (Amps)

Tj = 25 C

Tj = 150 C

VDS > ID x RDS(on)max

-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C

VGS(TO) / V

4

3

2

1

0

max.

typ.

min.

0246810

0

1

2

3

4

PHP4N40

ID, Drain current (A)

gfs, Transconductance (S)

Tj = 25 C

150 C

VDS > ID x RDS(on)max

0 1 2 3 4

VGS / V

ID / A

1E-01

1E-02

1E-03

1E-04

1E-05

1E-06

SUB-THRESHOLD CONDUCTION

typ

2 %

98 %

-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C

Normalised RDS(ON) = f(Tj)

2

1

0

a

1 10 100 1000

1

10

100

1000

PHP4N40

VDS, Drain-Source voltage (Volts)

Junction capacitances (pF)

Ciss

Coss

Crss

August 1998 5 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP4ND40E, PHB4ND40E
FREDFET, Avalanche energy rated

Fig.13. Typical turn-on gate-charge characteristics.

V

GS

= f(QG); parameter V

DS

Fig.14. Typical switching times; t

d(on)

, tr, t

d(off)

, tf = f(RG)

Fig.15. Normalised drain-source breakdown voltage

;

V

(BR)DSS/V(BR)DSS 25 ˚C

= f(Tj)

Fig.16. Source-Drain diode characteristic.

IF = f(V

SDS

); parameter T

j

Fig.17. Maximum permissible non-repetitive

avalanche current (IAS) versus avalanche time (tp);

unclamped inductive load

Fig.18. Maximum permissible repetitive avalanche

current (IAR) versus avalanche time (tp)

0 10203040

0

5

10

15

PHP4N40

Qg, Gate charge (nC)

VGS, Gate-Source voltage (Volts)

VDD = 320 V

200 V

80 V

ID = 4.4 A

Tj = 25 C

0 0.5 1 1.5

0

5

10

15

20

PHP4N40

VSDS, Source-Drain voltage (Volts)

IF, Source-Drain diode current (Amps)

VGS = 0 V

Tj = 25 C

150 C

0 102030405060

1

10

100

1000

tr

PHP4N40

RG, Gate resistance (Ohms)

Switching times (ns)

Tj = 25 C

RD = 47 Ohms

VDD = 200 V
VGS = 10 V

td(on)

td(off)

tf

PHP4N40E

0.1

1

10

1E-06 1E-05 1E-04 1E-03 1E-02

Avalanche time, tp (s)

Non-repetitive Avalanche current, IAS (A)

125 C

VDS

ID

tp

Tj prior to avalanche = 25 C

-100 -50 0 50 100 150

0.85

0.9

0.95

1

1.05

1.1

1.15

Tj, Junction temperature (C)

Normalised Drain-source breakdown voltage

V(BR)DSS @ Tj
V(BR)DSS @ 25 C

PHP4N40E

0.01

0.1

1

10

1E-06 1E-05 1E-04 1E-03 1E-02

Avalanche time, tp (s)

Maximum Repetitive Avalanche Current, IAR (A)

125 C

Tj prior to avalanche = 25 C

August 1998 6 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP4ND40E, PHB4ND40E
FREDFET, Avalanche energy rated

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

10,3
max

3,7

2,8

3,0

3,0 max

not tinned

1,3

max

(2x)

123

2,4

0,6

4,5
max

5,9

min

15,8

max

1,3

2,54 2,54

0,9 max (3x)

13,5

min

August 1998 7 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP4ND40E, PHB4ND40E
FREDFET, Avalanche energy rated

MECHANICAL DATA

Dimensions in mm
Net Mass: 1.4 g

Fig.20. SOT404 : centre pin connected to mounting base.

MOUNTING INSTRUCTIONS

Dimensions in mm

Fig.21. SOT404 : soldering pattern for surface mounting

.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

11 max

4.5 max

1.4 max

10.3 max

0.5

15.4

2.5

0.85 max
(x2)

2.54 (x2)

17.5

11.5

9.0

5.08

3.8

2.0

August 1998 8 Rev 1.100

Philips Semiconductors Product specification

PowerMOS transistors PHP4ND40E, PHB4ND40E
FREDFET, Avalanche energy rated

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

August 1998 9 Rev 1.100