function of gate-source voltage; P-channel
typical values.
1997 Oct 2212
Page 13
Philips SemiconductorsProduct specification
Complementary enhancement mode
MOS transistors
1.3
handbook, halfpage
k
1.2
1.1
1
0.9
0.8
0.7
−100
−50150050100
MGG349
Tj (°C)
1.3
handbook, halfpage
k
1.2
1.1
1
0.9
0.8
0.7
−100
PHC20512
MGG358
−50150050100
Tj (°C)
V
at T
GSth
k
=
-------------------------------------V
GSth
V
at VDS=VGS; ID= 1 mA.
GSth
j
at 25°C
Fig.20 Temperature coefficient of gate-source
threshold voltage as a function of junction
temperature; N-channel typical values.
V
at T
GSth
k
=
-------------------------------------V
GSth
V
at VDS=VGS; ID= −1 mA.
GSth
j
at 25°C
Fig.21 Temperature coefficient of gate-source
threshold voltage as function of junction
temperature; P-channel typical values.
1997 Oct 2213
Page 14
Philips SemiconductorsProduct specification
Complementary enhancement mode
MOS transistors
handbook, halfpage
2
k
1.5
1
0.5
0
−100
−50150
0
50100
MGG359
(1)
(2)
Tj (°C)
handbook, halfpage
2
k
1.5
1
0.5
0
−100
PHC20512
MGG359
(1)
(2)
−50150
0
50100
Tj (°C)
R
at T
k
=
----------------------------------------R
DSon
(1) R
DSon
(2) R
DSon
DSon
j
at 25 °C
at VGS= 10 V; ID= 3.2 A.
at VGS= 4.5 V; ID= 1.6 A.
Fig.22 Temperature coefficient of drain-source
on-resistance as a function of junction
temperature; N-channel typical values.
R
at T
DSon
k
=
----------------------------------------R
DSon
(1) R
DSon
(2) R
DSon
j
at 25 °C
at VGS= −10 V; ID= −2A.
at VGS= −4.5 V; ID= −1A.
Fig.23 Temperature coefficient of drain-source
on-resistance as a function of junction
temperature; P-channel typical values.
1997 Oct 2214
Page 15
Philips SemiconductorsProduct specification
Complementary enhancement mode
MOS transistors
PACKAGE OUTLINE
SO8: plastic small outline package; 8 leads; body width 3.9 mm
D
c
y
Z
8
5
PHC20512
SOT96-1
E
H
E
A
X
v M
A
A
pin 1 index
1
e
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
mm
A
max.
1.75
0.069
A
1
0.25
0.10
0.010
0.004
A2A
1.45
1.25
0.057
0.049
0.25
0.01
b
3
p
0.49
0.25
0.36
0.19
0.019
0.0100
0.014
0.0075
UNIT
inches
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
4
w M
b
p
02.55 mm
scale
(1)E(2)
cD
5.0
4.8
0.20
0.19
eHELLpQZywv θ
4.0
1.27
3.8
0.16
0.050
0.15
2
A
6.2
5.8
0.244
0.228
Q
3
A
θ
0.250.10.25
0.010.010.0410.004
(1)
0.7
0.3
0.028
0.012
o
8
o
0
L
p
L
0.7
0.6
0.028
0.024
(A )
1
detail X
1.0
1.05
0.4
0.039
0.016
OUTLINE
VERSION
SOT96-1
IEC JEDEC EIAJ
076E03S MS-012AA
REFERENCES
1997 Oct 2215
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-05-22
Page 16
Philips SemiconductorsProduct specification
Complementary enhancement mode
PHC20512
MOS transistors
DEFINITIONS
Data Sheet Status
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Oct 2216
Page 17
Philips SemiconductorsProduct specification
Complementary enhancement mode
MOS transistors
NOTES
PHC20512
1997 Oct 2217
Page 18
Philips SemiconductorsProduct specification
Complementary enhancement mode
MOS transistors
NOTES
PHC20512
1997 Oct 2218
Page 19
Philips SemiconductorsProduct specification
Complementary enhancement mode
MOS transistors
NOTES
PHC20512
1997 Oct 2219
Page 20
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands137107/00/03/pp20 Date of release: 1997 Oct 22Document order number: 9397 75002977
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