Datasheet PEF2015 Datasheet (Siemens)

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Page 1

ICs for Communications

Mini IOM®-2 Controller MICO

PEF 2015 Version 1.1

Data Sheet 12.97

DS 1

Page 2

PEF 2015 Revision History: Current Version: Data Sheet 12.97

Previous Version: Preliminary Data Sheet 05.97 Page

(in previous Version)

34, 58 34, 58 MFAIR: new reset value = 00xx xxxx 34, 60 34, 60 CIFIFO: new reset value = 0xxx xxxx

Page (in new Version)

Subjects (major changes since last revision)

34, 69, 70 34, 69, 70 VNSR register: Reset value corrected to 02H

(Version bits for MICO V1.1: 0010)

- 75, 78 New timing in Motorola mode: t )

77, 78, 80 75, 76, 78 Timing value and definition changed: t

xWR / CSxDS in write access)

to CS

= 10 ns max. (R/W hold time from

RWh

= 0 ns min. (Data set-up time

Edition 12.97

This edition was realized using the software system FrameMaker.

Publis he d by Si em ens AG , HL DT CE

All Rights Reserve d. Attention pleas e !

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circui ts imple m en te d with in co mp o ne nt s or ass emb li es .

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For qu est io ns on tec hnolo gy , del i very an d pr ic es pl ease con tact the Semi condu ct or G roup Offi ce s in G erma ny or the S ieme ns C ompa nies

and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer.

Packing

Please u se t he recycl in g opera to r s k n ow n t o you. W e can als o help yo u – get in touc h w it h yo u r nea rest s a les office. By agr ee m e nt we will take packing material back, if it is sorted. You must bear the costs of transport. For packi ng ma t er i al that is return ed to us u nsort ed or w hich we a r e no t obliged to a ccept, w e sh a ll have t o invoi ce y ou for a ny co st s incurred.

Compone nts used in life -s upp ort de vice s or syste m s mu st be exp res sl y authori ze d for such purpo se !

Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

Page 3

PEF 2015

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.2 Pinning Diagram (top view) 8

1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.4 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.5 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2 Functional Des cription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.1 Configurable Interface CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.2 Serial PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.3 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.4 Memory Str uct ure and S witching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5 Pre-processed Channels, Layer-1 Support . . . . . . . . . . . . . . . . . . . . . . . .17

2.6 Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3 Operational Descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.1 Microprocessor Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.2 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.4 MICO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.4.1 PCM-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.4.2 Configurable Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.4.3 Switching Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.4.4 Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

3.5 Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.5.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.5.2 MICO Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.5.2.1 Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.5.2.2 Control Memor y Re set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.5.2.3 Initialization of Pre-processed Channels . . . . . . . . . . . . . . . . . . . . .30

3.5.2.4 Initialization of the Upstream Data Memory (DM) Tristate Field . . . .31

3.5.3 Activation of the PCM - and CFI-Interfaces . . . . . . . . . . . . . . . . . . . . . . 32

4 Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.1 Register Address Arrangem ent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.2 Detailed Register Descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

4.2.1 PCM-Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

4.2.1.1 PCM-Mode Register (PMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

4.2.1.2 Bit Numb er per PCM -Fr ame (PBNR) . . . . . . . . . . . . . . . . . . . . . . . .3 6

4.2.1.3 PCM-Offset Downstream Register (POFD) . . . . . . . . . . . . . . . . . . .36

4.2.1.4 PCM-Offset Upstream Register (POFU) . . . . . . . . . . . . . . . . . . . . .37

4.2.1.5 PCM-Clock S hift Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . .38

4.2.1.6 PCM -Input Compar ison Mism atc h Register (PICM ) . . . . . . . . . . . . .38

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PEF 2015

4.2.2 Configurable Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.2.2.1 Conf igurable Inter face Mode Registe r 1 (CMD1) . . . . . . . . . . . . . . . 39

4.2.2.2 Conf igurable Inter face Mode Registe r 2 (CMD2) . . . . . . . . . . . . . . . 41

4.2.2.3 Conf igurable Inter face Bit Number Regist er (CBNR) . . . . . . . . . . . .44

4.2.2.4 Conf igurable Inter face Time Slot Adjustm ent Regist er (CTAR) . . . .44

4.2.2.5 Conf igur able Inter face Bit Shift Register (CB SR) . . . . . . . . . . . . . . .45

4.2.2.6 Configurable Inter face Subchannel Register (CSCR) . . . . . . . . . . .47

4.2.3 Memory Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

4.2.3.1 Me mory Access Contro l Register (MAC R) . . . . . . . . . . . . . . . . . . . . 48

4.2.3.2 Me mory Access Address Register (MAAR) . . . . . . . . . . . . . . . . . . .52

4.2.3.3 Memory Access Data Reg ister (MADR) . . . . . . . . . . . . . . . . . . . . . .53

4.2.4 Synchronous Transfer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

4.2.4.1 Synchronous Transfer Data Register (STDA) . . . . . . . . . . . . . . . . .54

4.2.4.2 Synchronous Transfer Data Register B (STDB) . . . . . . . . . . . . . . . .54

4.2.4.3 Synch ronou s Transf er Receive Address Regist er A (SARA) . . . . . . 55

4.2.4.4 Synch ronou s Transf er Receive Address Regist er B (SARB) . . . . . . 56

4.2.4.5 Synch ronou s Transf er Transm it Addre ss Reg ister A (SAXA) . . . . .56

4.2.4.6 Synch ronou s Transf er Transm it Addre ss Reg ister B (SAXB) . . . . .57

4.2.4.7 Synchronous Transfer Control Register (STCR) . . . . . . . . . . . . . . .57

4.2.5 Monitor/Feature Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

4.2.5.1 MF-Channel Active Indication Register (MFAIR) . . . . . . . . . . . . . . .58

4.2.5.2 MF -Channe l Subscriber Addr ess Registe r (MFSAR) . . . . . . . . . . . .59

4.2.5.3 Monitor/Feature Control Channel FIFO (MFFIFO) . . . . . . . . . . . . . .60

4.2.6 Status/Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

4.2.6.1 Signaling FIFO (CIFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

4.2.6.2 Timer Register (TIMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

4.2.6.3 Sta tus Regist er (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.2.6.4 Command Register (CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

4.2.6.5 In terrupt Stat us Registe r (ISTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.2.6.6 Mask Register MICO (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

4.2.6.7 Opera tion Mod e Register (OMDR) . . . . . . . . . . . . . . . . . . . . . . . . . .67

4.2.6.8 Version Number Status Register (VNSR) . . . . . . . . . . . . . . . . . . . .69

4.3 Register Changes com pare d to the EPIC . . . . . . . . . . . . . . . . . . . . . . . . .7 0

4.3.1 PMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3.2 PCSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3.3 PICM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3.4 CMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3.5 CSCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3.6 ISTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3.7 MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3.8 VSNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

5 Application Exampl es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

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PEF 2015

5.1 Access Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

7 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

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PEF 2015

Overview

1 Overview

The Mini IOM-2 Controller MICO (PEF 2015) is an interface controller optimized for small line card applications or Intelligent NTs. It is derived from the EPIC core. The MICO supports up to 16 analog subscriber s (up to 8 using the SLICOFI ) or up to 8 ISDN-BA subscribers.

The MICO is used as an interface device on linecards between the subscr iber circuits and the network. Therefore it p rovides one IOM-2 interface for connection of up to 8 ISDN-BA subscribers or up to 16 analog subscribers (up to 8 using the SLICOFI).The MICO a lso provides one P C M interface for connection to the m ain system. Additionally the MICO is used to cont rol the subscriber circuits via the C/I and monitor channel as specified in the IOM-2 specification. A parallel µP interface is provided for device programming.

Furthermore t he MICO contains a nonblocking switching unit with a flexible time slot assignme nt between the I OM- 2 and the PCM inter face.

The MICO may substit ute the EPIC (PEB 2055) or EPIC-S (PEB 2054) in applications that deal with a maximum number of 8 ISDN or 16 analog (8 using the SLICOFI) subscribe rs connecte d via one IOM-2 port.

The MICO is fabricated using SIEMENS advanced CMOS technology and is available in a P-DSO-28 package.

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Mini IOM®-2 Controller

PEF 2015

MICO

Data Sheet for the Version 1.1 CMOS

1.1 Features

Functions

• Interface controller between IOM-2 an d PCM f or up

to 8 ISDN-BA or 16 analog subscribers (up to 8 analog subscribers using the SLICOFI )

• B-channel (64 kbit/s) and D-channel (16 kbit/s)

switching

• Configurable Interface (1 port)

- Configurable for IOM-, SLD- and PCM-applications

- Programmable clock shift

- Single or double data clock

• PCM interface (1 port)

- Freely programmable time slot assign men t to up to 128 PCM time slots

- Tristate control signal for external driv er

- Single or double data clock

• C/I-channel Handler with a 9-Byte FIFO

• Buffered Monitor Handler with a 16-Byt e FIFO

• 7-bit hardware timer

P-DSO-28

General

• Siemens/Intel or M otor ola type µP in ter fa c e

• Supply Voltage: 5 V

• Extended temperatu re ran ge -40°C to +85°C

• P-DSO-28 package

Type Package

PEF 2015 P-DSO-28

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1.2 Pinning Diagram

(top view)

PEF 2015

Overview

ALE, A0

RxD

TSC

TxD

PFS

PDC

AD0

AD1

AD2

AD3

AD4

AD5

MICO

MIC_PINN.DRW

RES

A2A1

FSC

DCL

INT

WR, R/W

RD, DS

AD7

AD6

Figure 1 Pinning Diagra m

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1.3 Pin Description

PEF 2015

Overview

Pin No.

23 FSC I/O Frame Synchronizati on

22 DCL I/O Data Clock

24 DU, SIP4 I, I/O (OD) Data Upstream, Input IOM- or PCM-configuration.

25 DD, SIP0 O, I/O (OD) Data Downstream, Output IOM- or PCM-configuration

Symbol Input (I)

Output (O)

Function

Input or output in IOM-c onfigur at ion. Direction indication in SLD-mode.

Input or output in IOM-c onfigur at ion. Slave clock in SLD mode. Single or double data rate in IOM-configuration, single data rate in SLD-mode.

Serial Interface Port, SLD configuration.

Depending on the bit OMDR:COS this line has push-pull or open drain characteristic. For unused or unassigned channels or when bit OMDR:CSB is reset the pin is in the state high impedance.

7 PFS I PCM-Interface Frame Synchronization 8 PDC I PCM-Interface Data Clock

Single or double data rate.

6 TxD O Transmit PCM-Interface Data

Time-slot or ient ed dat a is shifted out of the MICOs upstream data memor y on this line. For time-slots

which are flagged in the tristate dat a mem ory or when bit OMDR:PSB is reset the pin is set in the state high impedance.

5 TSC

4 RxD I Receive PCM- Inter face Data

O Tristate Control

Supplies a control signal for an external driver. This line is ’low’ when corresponding TxD outputs are valid. During reset this line is high.

Time-slot orient ed dat a is received on this p in and forwarded into the downs tream data me mor y of the MICO.

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PEF 2015

Overview

Pin No.

9 10 11 12 13 14 16 17

2 3 26 27

Symbol Input (I)

Output (O)

AD0, D0 AD1, D1 AD2, D2 AD3, D3 AD4, D4 AD5, D5 AD6, D6 AD7, D7

A0/ALE A1 A2 A3

I/O Address/Data Bus; multiplexed bus mode.

I Address Bus, demultiplexed mode.

Function

Transfers addresses from the µP to the MICO and data between the µP and the MICO.

Data Bus; demultiplexed bus mode. Transfers data between the µP and the MICO.

When driving data the pins have push pull characteristic, otherwise they are in the state high impedance.

Transfers addresses f rom the µP to the MICO.

Address Latch Enable, multiplexed mode. ALE controls the on chip address latch in multiplexed bus mode. While ALE is ’high’ the latch is transparent. The falling edge latches the current address.

Note: During reset A0 and A1 are evaluated to

determ ine the bus mode.

18 R D, DS I Read, active low, Siem ens/ In tel bus mod e.

When ’low’ a read operation is indicated. Data Strobe, Motoro la bus mode.

A rising edge marks the end of a read or write operation.

19 W R

R/W

20 C S

I Write, active low, Siemens/ In tel bus mod e.

When ’low’ a write operation is indicated.

Read/Writ e, Motor ola bus mode . When ’high’ a valid µP access identifies a read operation, when ’low’ it identifies a write access.

I Chip Select, active ’low’.

A low on this line selects the MICO for a read/write operation.

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PEF 2015

Overview

Pin No.

Symbol Input (I)

Output (O)

Function

21 INT O (OD) Interrupt, active low.

This line is activated when the MICO requests an interrup t. Due to the open dr ain (OD) charac teristic of

multiple interrupt sources can be connected

INT together.

28 RES I Reset

A ’high’ forces the MICO into rese t state. 15 V 1V

SS DD

I Ground (0 V) I Supply Voltage (5 V +/- 5%)

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1.4 Logic Symbol

PEF 2015

Overview

FSC

DCL

MICO

PEF 2015

PFS

PDC

TxD

TSC

RxD

AD7..AD0

A3..A0

RD (DS)WR(R/W)

INT

RES

par_log1.drw

Figure 2 Logic Symbol

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1.5 Functional Block Diagram

µP interface

MICO

TxD

RxD

PCM

Interface

upstream

(TRANSMIT)

downstream

(RECEIVE)

access c ont rol

Monitor

Sync.

Transfer

Timer

Timing

FSC DCL

PFS PDC

RES

TSC

mic_blk3.drw

AD7..AD0

A3..A0

CFI

Interfa ce

C/I

RD (DS)WR(R/W)

INT

PEF 2015

Overview

Figure 3 Functional Block Diagr am

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PEF 2015

Functional Description

2 Functional Description

2.1 Configurable Interface CFI

The integrated CFI is a one port serial interface. It comprises two serial data lines (upstream DU and downstream DD), a data clock input or output DCL and a frame sync input or output FSC in IOM-applications. The clock frequency is either equ al to the data rate or twice the data rate. The CFI can be conf igu red to data rat es up to 8.192 Mbit/s.

The CFI is typically used in IOM-2 or SLD configuration to connect layer-1 devices.

Figure 4 shows the IOM-2 Interface st ruc ture in Line Card Mode:

Figure 4 IOM

-2 Frame Structure with 2.04 8 Mbi t/s Data Ra te

2.2 Serial PCM Interface

The PCM int erface forma ts the dat a transmitted or received at the PCM-highways. It consists of one port comprising a data receive (RxD), a data transmit (TxD) and an output tristat e indication line (TS C

). The PCM interface is supplied with a frame signal

(PFS) and a PCM clock (PDC). Data rates up to 8.192 Mbit/s are supported. To properly clock the PCM interface a PDC

signal with a frequency equal or twice the data rate has to be applied to the MICO.

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PEF 2015

Functional Description

2.3 Microprocessor Int erf ace

The MICO supports Siemens/ I nte l and Motorola type microprocessor s. In the Siemens/ Intel type µP interface either a multiplexed or a demultiplexed bus structure may be chosen.

The int erfac e type is sele cted by pulling up or down two address pins dur ing the reset state (refer to Table 1, “Selection of Bus Interface,” on page 18). Pulling-up the appropriate pins selects the Motor ola type µP interfac e, fixing them to ground c hooses the Siemens/I ntel type µP interfac e mode. In case of a multiplexed Siemens/Intel bus structure addr ess pin A0 takes over the ALE func tionality.

The microprocessor inter f ace consist s of the following lines:

• Data Bus, 8-bit wide, AD7..AD 0

• Address bus, 4-bit wide, A3.. A 0

• Chip select, CS

• Two read/write control lines: RD and WR (Intel mode) or DS and R/W (Motorola mode)

• Interr upt , INT

• Reset, RES

D0-7

MICO

0-3

with Motorola

Type Interface

W A

0-7

MICO

Interface,

0-3

with Siemens/Intel Type

Demultiplexed MultiplexedInterface,

Address/Data Bus

0-7AD

ALEWR WR

with Siemens/Intel Type

MICO

Address/Data Bus

BUS_INTF.DRW

Figure 5 Selectabl e Bus Inte rfa ce Struct ures

2.4 Memory Struct ure and Sw itching

The memory block of the MICO perf orm s the switc hing functionality. It consists of four sub blocks:

– Upstream data memory – Downstream data mem ory – Upstream control memory – Downstream control memory.

The PCM-interface reads periodically from the upstream (writes periodically to the downstream) data memory (cyclical access), see figure 6.

The CFI reads periodically the control memory and uses the extracted values as a pointers to write to the upstream (read from the downstream) data memory (random

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PEF 2015

Functional Description

access). In the case of C/I- or signaling channel applications the corr esponding data is stored in the control memory. In order to select the application of choice, the control memory pro vid es a code port io n.

The control memory is accessible via the µP-interface. In order to establish a connection between CFI time slot A and PCM-interface t ime slot B, the B-pointer has to be loaded into the control memor y location A.

CFI

Upstream

Downstream

Control Memory (CM)

DATA

Bits8

CODE

Bits4

Data Memory

DATA

Bits8

Control Memory (CM)

(DM)

DATA

8 Bits

CODE

4 Bits

Data Memory

DATA

Bits8

(DM)

CODE

Bits4

TxD

PCM

Rx D

µ P

Figure 6 MICO Memor y Struc ture

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2.5 Pre-processed Channels , Layer-1 Support

The MICO supports the monitor/feature control and control/signaling channels according to SLD- or IOM-2 interface prot ocol.

The monitor handler cont rols the data flow on the monitor/ feature contr ol channe l either with or without active handshake protoco l. To reduce the dynamic load of the CPU a 16-byte transm it/ rece ive FIFO is provided.

The signaling handler supports different schemes (D-channel + C/I-channel, 6-bit signaling, 8-bit signaling).

In downstream direction the relevant content of the control memory is transmitted in the appropriate CFI time slot. In the case of centralized ISDN D-channel handling, a 16-kbit/ s D-channel received at the PCM-interface is included.

In upstream direct ion the signaling handler monitors the received dat a. Upon a change it generates an interr upt, the channe l address is store d in the 9-byte deep C/I FIFO and the actual value is store d in the cont rol memor y. In 6-bit a nd 8-bit signaling schem es a double last look check is provided.

2.6 Special Functions

– Synchronous transfer.

This utility allows the synchr onous µP-ac cess t o two in depend ent c hannels o n the PCM- or CFI-interface. Interrupts are generat ed to indicate the appropr iate access windows.

– 7-bit hardware timer.

The MICO offers one hardware timer. It can be used to cyclically interrupt the CPU, to determine the double last look period or to generate a proper CFI-multiframe synchronization signal.

– Frame length checking.

The PFS-period is internally checked against the progr ammed f rame length.

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3 Operational Descripti o n

The MICO, designed as a flexible line-card controller, has the following main applications:

– Digital line cards, with the CFI typically configured as IOM-2, IOM-1 (MUX) or SLD. – Analog line cards, with the CFI typically configured as IOM -2 or SLD. – Intelligent NTs, where the MICO’s ability to configure the CFI as a PCM interface is

utilized.

To operate the MICO the user must be familiar with the device’s microprocessor interface, interr upt structu re and res et logic.

The device is derived from the EPIC core. With some restrictions it is therefore programmable like the EPIC.

3.1 Microprocessor Int erf ace O perat ion The MICO is programm ed via an 8-bit para llel interface that can be selected to be

(1) Motorola type, with control signals DS (2) Siemens / Intel non-multiplexed bus type, with contro l signals WR

and CS

(3) Siemens / Intel multiplexed address/ dat a bus type , with control sign als

ALE, WR

The selection is performed via supplying address pins A0 and A1 during reset as follows:

Table 1 Selection of Bus Interface A1, A0 during reset Bus Interface

11 Motorola type (1) 00 Siemens / Intel type, non-mu ltip lexed (2) 01 or 10 Siemens / Intel type, multiplexed (3)

, RD, and CS.

, R/W, and CS.

, RD ,

Pin A0 will take over the ALE functionality

Note: When selecting the multiplexed bus mode, it has to be ensured that during a MICO

device reset the A0/ALE p in receive s the appropr iate level and no AL E transf ers

by the

C affect the interface type selection (refer also to figure 18, page 75).

When using the Siemens / Intel multiplexed interface, the MICO is addressed with even addresses only (i.e. AD0 always 0), which allows data always to be transferred in the low data byte. This simplifies the use of 16 bit Siemens / Intel type proce ssor s.

For a non-multiplexed bus structure the OMDR:RBS bit is needed in addition to the address lines A3.. 0. OMDR:RBS (Register Bank Selec tion) selects one o f two register banks.

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RBS = ’1’ selects a set of registers used for device initialization (e.g. CFI and PCM interface initializat ion). RBS = ’0’ switches to a group of regist ers neces sary dur ing oper ation (e.g. con nection programm ing).

The OMDR register containing the RBS bit can be accessed with either value of RBS.

Interrupts

An interrupt of the MICO is indicated by activating the INT request can be determin ed by reading the ISTA register.

The INT serviced. If a new status bit is set while an interrupt is being serviced, the INT active. Howe ver, for the duration of a write access to the MASK- reg ister the INT deactivated. When using an edge-triggered interrupt controller, it is t hus recommended to rewrite the MASK-register at the end of any interr upt service routine.

Every interrupt source can be selectively masked by setting the respective bit of the MASK-register. Such masked interrupts will not be indicated in the ISTA-register, nor will they activate the INT

3.2 Clocking To operate properly , the MICO al ways requir es a PDC-cloc k.

To synchronize the PCM-side, the MICO should normally also be provided with a PFSstrobe. In most applications, the DCL and FSC will be output signals of the MICO, derived from the PDC via presca lers.

If the required CFI-data rate cannot be derived from the PDC, DCL and FSC can also be programmed as input signals. This is achieved by setting the MICO CMD1:CSS-bit. Frequency and phase of DCL and FSC may then be chosen almost independently of the frequency and phase of PDC and PFS. However, the CFI-clock source must still b e synchronous to the PCM-interface clock source; i.e. the clock source for the CFIinterface and the clock source for the PCM-interface must be derived from the s ame master clock.

-output is level active. It stays active until all interrupt sources have been

-line.

-line. The detailed cause of the

stays

-line is

3.3 Reset A reset pulse of at least 4 PDC clock cycles has to be applied at the RES pin. The reset

pulse sets all registers to their reset values descr ibe d in section 4. The MICO is now in CM-r eset m ode ( refer to 4. 2.6. 7 ). As the hard ware reset does not

affect the MICO memories CM and DM, a ’software reset’ of the CM has to be performed. Subsequently the MICO can be programmed to CM-in itialization, norma l operation or

test mode. During reset the addr ess pins A0 and A1 are evaluate d to determine the bus inter face type.

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3.4 MICO Operation

The MICO is principally an intelligent switch of PCM-data between two serial interfaces, the system interface (PCM-interface) and the configurable interface (CFI). Up to 128 channels per direction can be switched dynamically between the CFI and the PCMinterfaces. The MICO performs non-blocking space and time switching for these channels which may have a bandwidth of 16, 32, 64 or 128 kbit/s on a per device basis.

Both interfaces can be programmed to operate at different data rates of up to 8.192 Mbit/ s. The PCM-interface consists of one duplex port with a tristate control signal. The configurable interface can be selected to provide either one duplex port or two bidirectional (I/O) ports.

The configurable interface incor porat es a cont ro l block (layer-1 buffer) which allows the µP to gain access to the cont rol chan nels of an IOM- (ISDN-O r ie nted Modu lar) or SLD(Subscriber Line Data) int erface. The MICO can handle the layer-1 f unctions b uffering the C/I and monitor channels for IOM compatible devices and the featur e control and signaling channels for SLD compatible devices. The layer-1 and codec devices are connected to the CFI, which is then configured to operate as IOM-2, SLD or multiplexed IOM-1 interface.

The configurable interface of the MICO can also be configured as plain PCM-interface i.e. without IOM- or SLD-frame structure. Since it’s possible to operate the two seria l interfaces at different data rates, the MICO can then be used to adapt two different PCMsystems.

The MICO can handle up to 8 ISDN-subscribers with their 2B+D channel structure or up to 16 analog subscr ibers with their 1B channel structur e in IOM-configurat ion. In SLDconfiguration up to 4 analog subscribers can be accom mod ated .

The system interface is used for the connection to a PCM-back plane. On a typical digital line card, the MICO switches the ISDN B-channels and, if required, also the D-channels to the PCM-back plane. Due to its capability to dynamically switch the 16-kbit/s D-channel, the MICO is one of the funda men tal bu ilding block s for net wo rks w ith either central, decentral or mixe d signaling and packet data handling architecture.

3.4.1 PCM-Interface

The serial PCM-interface provides on e port consisting of a data transm it (TxD), a data receive (RxD) and a tristate con trol (TS C as the upstream direction, whereas the receive direction is referred to as the downstream direction.

) line. The transmit direct ion is also refe rre d to

Data is transm itted and rec e ived a t norm al TTL /CM OS-levels, the ou tput d river s being of the tristate type. Unassigned time slots may either be tristated, or programmed to transmit a defined idle value. The selection of the states "high impedance" and "idle value" can be per formed wit h a two bit reso lution. This tr istate c apability allows sever a l devices to be connected together for concentrator functions. If the output driver

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capability of the MICO should prove to be insufficient for a specific application, an external driver contro lled by the TSC

The PCM-s tandby function makes it possible to switch all PCM-output lines to high impedance with a single command. Internally, the device still works norm ally. Only the output driver s a re s w itched off.

The number of time slots per 8-kHz frame is pro grammable in a wide range (from 4 to

128). In other words, the PCM-data rate can range between 256 kbit/s up to

8.192 Mbit/s. For time s lot encoding refer to figure 7. The number of bits per frame is defined by the PCM-mode. There are three PCM-

modes. The timing characteristics at the PCM-interface (data rate, bit shift, etc.) can be varied in

a wide range. The PCM-interfac e has to be clocked with a PCM-Data Clock (PDC) signal having a

frequency equal to or twice the selected PCM-data rate. In single clock rate operation, a frame consisting of 32 time slots, for example, requires a PDC of 2048 kHz. In double clock rate operation, however, the same frame structure would require a PDC of 4096 kHz.

can be connected.

For the synchronizat ion of the time slot struct ure to an external PCM-syst em, a PCM- Framing Signal (PFS) must be applied. The MICO evalua tes the rising PFS edge to reset the int ernal time s lot count ers . In o rder to adap t the PFS-t im ing to diff er ent tim ing requirements, the MICO can latch the PFS-signal with either the rising or the falling PDCedge. The PFS-signal defines the position of the first bit of the internal PCM-frame. The actual position of the externa l upstream and downstream PC M-frames with respect to the framing signal PFS can still be adjusted using the PCM-offset function of the MICO. The offset can then be programmed such that PFS marks any bit number of the external frame.

Furthermore it is possible to select either the rising or falling PDC-clock edge for transmitting and sam p l ing the PCM-data .

Usually, the repetition rate of the applied framing pulse PFS is identical to the frame period (125 µs). If this is the case, the loss of synchronism indicati on functio n can be used to supervise the clock and framing signals for missing or additional clock cycles. The MICO checks the PFS-period internally against the duration expected from the programmed data rate. If, for example, double clock operation with 32 time slots per frame is programm ed, the MICO expects 512 clock periods within one PFS-period. The synchronous state is reached after the MICO has detected two consecutive correct frames. The synchronous state is lost if one bad clock cycle is found. The synchronization s tatus (gained or lost) can be read from an inter nal register and each status change generates an interrup t.

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CFI Mode 0

PCM Mode 0

1 Duplex Port

32 Time-Slots

CFI Mode 1

1 Duplex Port

64 Time-Slots

U/D

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Operational Description

Time-Slot # (0-31)

Time-Slot # (0-63)

PCM Mode 1

1 Duplex Port

64 Time-Slots

CFI Mode 2

PCM Mode 2

1 Duplex Port

128 Time-Slots

CFI Mode 3

2 Bidirectional Ports

16 Time-Slots/Port

U/D

Time-Slot # (0-63)

Time-Slot # (0-127)

Time-Slot # (0-15)

U/D: Upstream (1) / Downstream (0)

ITD08063mod

Figure 7 Time Slot Encoding for the Diff erent PCM and CFI Modes

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3.4.2 Configurable Interface

The serial configurable interface (CFI) can be operated either in duplex modes or in a bidirectional mode.

In duplex mode s the MICO provides one por t consisting of a data output (DD) and a data input (DU) line. The output pin is called "Data Downstream" pin and the input pin is called "Data Upstream" pin. These modes are especially suited to realize a standard serial PCM-interface (PCM-h ighway) or to implement an IOM (ISDN-Oriented Mo dular) interface. The IOM -interface gener at ed by t he M ICO o ffers all the f unction ality l ike C/ Iand monitor channel handling required for operating all kinds of IOM compatible layer-1 and codec devices.

In bi-directional mode the MICO provides two bi-directional ports (SIP). Each time slot at any of these ports can individually be progra mmed as input or ou tput. This m ode is mainly intended to realize an SLD-interface (Serial Line Data). In case of an SLDinterface the fr ame consists of eight time slots where the first four time slo ts serve as outputs (downstream d irection) and the last four serv e as inputs (upstream d irection). The SLD-interface gene rated by the M ICO offe rs signaling and featur e control cha nnel handling.

Data is transmitted and received at normal TTL/CMOS-levels at the CFI. Tristate or open-drain output drivers can be selected. In case of open-drain drivers, external pullup resistors are required. Unassigned output time slots may be switched to high impedance or be programmed t o transmit a defined idle value. The selection between the states "high impedanc e" or "idle value" can be perform ed on a per tim e slot basis.

The CFI-standby function switches all CFI-output lines to high impedance with a single command. Internally the device still works normally, only the output drivers are switched off.

The number of time slots per 8-kHz frame is programmable from 2 to 128. In other words, the CFI-dat a rate can range betw een 128 kbit/s up to 8.192 Mbit/s . Since the MICO offers one CFI-port the number of usable memory locations depends on the selected data rate. In duplex modes port ’0’ has to be programmed, in bi-directional mode I/O port ’0’ and ’4’ have to be programmed. For deta ils refe r to figure 7.

The timing ch aracteristics at the CFI ( data rate, bit shift, etc .) can be var ied in a w ide range.

The clock and fram ing signals necessary to operate the configurable inte rface may be derived either fr om the clock and fr aming signals of the PCM-interfac e (PDC and PFS pins), or may be fed in directly via the DCL- and FSC-pins.

In the first case, the CFI-data rate is obtained by internally dividing down the PCM-clock signal PDC. Several presca ler fact ors are ava ilable to ob tain the most commo nly used data rates. A CFI reference clock (CRCL) is generated out of the PDC-clock. The PCMframing signal PFS is used to synchronize the CFI-frame structure. Additionally, the MICO generates clock and framing signals as outputs to operate the connected

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subscriber circu its such as layer-1 and codec filter devices. The generated dat a clock DCL has a frequency equal to or twice the CFI -dat a r ate. The gener ated framing s igna l FSC can be chosen from a great variety of types to suit the different applications: IOM-2, multipl exed IOM-1, SLD, etc.

Note that if PFS is selected as the framing signal source, the FSC-signal is an output with a fixed timing relationship with respect to the CFI-data lines. The relationship between FSC and the CFI-frame depends only on the select ed FSC-output wave for m (CMD2-register). The CFI-offset function shifts both the frame and the FSC-output signal with respect to the PFS-sign al.

In the second case, the CFI-data rate is derived from the DCL-clock, which is now used as an input signal. The DCL-clock may also fir st be divided down by internal pres calers before it serves as the CFI reference clock CRCL and before defining the CFI-data rate. The framing signal FSC is used to synchronize the CFI- fram e struct ure.

3.4.3 Switching Functi on s

The major tasks of the MICO is to dynamically switch PCM-data between the serial PCM-interface, the ser ial con figurable interf ace (CFI) and the pa rallel µP- interfac e. All possible switching paths are shown in figure 8.

MICO

CFI

PCM

µP Interface

µP

Figure 8 Switch ing Paths Inside the MICO

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Note that the time s lot selections in upstream direction are completely independent of the time slot selections in downstream direction.

CFI – PCM Time Slot Assignment

Switching paths 1 and 2 of figure 8 can be realized for a total number of up to 128 channels per path, i.e. up to 128 time slots in upstream and up to 128 time slots in downstream direction. To establish a connection, the µP writes the addresses of the involved CFI and PCM time slots to the control memory. The actual transfer is then carried out frame by fram e wit hout further µP-intervention.

The switching pat hs 5 and 6 ca n be r ealized by pr ogramming time slot ass ignmen ts in the control memory. The total number for such loops is limited to the number of available time slots at the respective opposite interface, i.e. looping back a time slot from CFI to CFI requires a spare upstream PCM time slot and looping back a time slot from PCM to PCM requires a spare downstream and upstrea m CFI time s lot.

Time slot switching is always carried out on 8-bit time slots, the actual position and number of transfer red bits can however be limited to 4-bit or 2-bit sub time slots with in these 8-b it t im e slots. On t he CFI-side, o nly one sub time slot per 8-bit time slot c an be switched, whereas on the PCM-interface up to 4 independent sub time slots can be switched.

Examples are given in section 4 of the EPIC Application Manual 10.9 2.

Sub Time Slot Switchi ng

Sub time slot positions at the PCM-interface can be selected at random, i.e. each single PCM time slot may cont ain any mix ture of 2- an d 4-bit sub t ime slots . A PCM tim e slot may also contain more than one sub time slot. On the CFI however, two restrictions must be observed:

– Each CFI time slot may contain one and only one sub time slot. – The sub-slot position for a given bandwidth within the time slot is fixed on a per port

basis and therefor e on a per device basis.

For more deta iled information o n sub-channel switch ing please refer to chapt er 5.2 of the EPIC-1 Application Manual 10.92.

µP-Transfer

Switching paths 3 and 4 of figure 8 can be realized for a ll available time slots. Path 3 can be implem ented by defining the corresp onding CFI time slots a s "µP-channels" or as "pre-processed channels".

Each single time slot can individually be declared as "µP-channel". If this is the case, the µP can write a static 8-bit value to a downstream time slot which is then transm itted repeatedly in e ach fra me until a new value is loaded. In u pst ream direct ion, the µP can read the received 8-bit value whenever required, no interrupt s being genera ted.

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The "pre- processed channel " option must always be applied to two consecut ive time slots. The first of these time slots must have an even time slot number . If two time- slots are declared as "pre-processed channels", the first one can be accessed by the monitor/ feature control han dler, which gives access t o the fram e via a 16-byte FIFO . Although this function is mainly intended for IOM- or SLD-applications, it could also be used to transmit or receive a "burst" of data to or from a 64-kbit/s channel. The second preprocessed time slot, the odd one, is also accessed by the µP. In downstream direction a 4-, 6- or 8-bit static value can be tran smitted. In upstream direct ion the received 8-bit value can be read. Additionally, a change detection mechanism will generate an interrupt upon a change in any of the selected 4, 6 or 8 bits.

Pre-processed channels are usually programmed after Control Memory (CM) reset during device initialization. Resetting the CM sets all CFI time slots to unassigned channels (CM code '0000'). Of course, pre-processed channels can also be initialized or re-initialized in the operational phase of the device.

To program a pair of pre-processed channels the correct code for the selected handling scheme must be written to the CM. Figure 9 gives an overview of the available pre- processing codes and their application. For further detail, please refer to chapter 5.5 of the EPIC User’s Manual 02.97.

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Figure 9 Pre-proce ssed Channel Codes

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Synchronous Transfer

For two channels, all switching paths of figure 8 can also be realized using Synchronous Transfer. The working principle is that the µP specifies an input time slot (source) and an output time slot (destination). Both source and de stination time slots can be selected independently from each other at either the PCM- or CFI-interface s. In each frame, the MICO first tra nsfe rs t he se rial data from the s ourc e tim e slot t o an inter na l data regist er from where it can be read and if required overwritten or modified by the µP. This data is then fed forward to the destinat io n time slot.

Chapter 8 of the EPIC Application Manual 10.92 provides examples of such tr ansf ers.

3.4.4 Special Functio ns

Hardware Timer

The MICO provides one hardware timer which continuously interrupts the µP after a programmable tim e period. The tim er period can be selected in the range of 250 µs u p to 32 ms in multiples of 250 µs. Beside the interr upt generation, the timer can also be used to determ ine the last look period f or 6 and 8-bit signaling channels on IOM -2 and SLD-interfaces and for the generat ion of an FSC-multifram e signal (see chapter 9.1 of the EPIC Application Manual 10.92).

Power and Clock Supply Supervision

The Connection Memory CM is supervised to data falsfication due to clock or power failure. If such an inappropriate c lock in g or power failure occurs, the µP is r eques ted to reinitialize the device.

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3.5 Initialization Procedure

For proper initialization of the MICO the following procedure is recom mended:

3.5.1 Hardware Reset

A reset pulse can be ap plied at the RES-pin for at least 4 PDC-clock c ycles. The reset pulse sets all register s to their reset values (re fer to section 4.1 ). Note that in this state DCL and FSC do not deliver any clock signals.

3.5.2 MICO Initialization

3.5.2.1 Register Initialization

The PCM- and CFI-configuration registers (PMOD, PBNR, …, CMD1, CMD2, …) should be programmed to the values required for the application. The correct setting of the PCM- and CFI-register s is important in order to obtain a referen ce clock (RCL) which is consistent with the ext er nally applied clock signals. The state of the operation mode (OMDR:OMS1..0 bits) does not matter for this programm ing ste p.

PMOD = PCM-mode, timing characte ristics , etc. PBNR = Number of bits per PCM-frame POFD = PCM- of fse t downstrea m POFU = PCM-offse t upstrea m PCSR = PCM-timing CMD1 = CFI-mode, timing characteristics, etc. CMD2 = CFI-timing CBNR = Number of bits per CFI-frame CTAR = CFI-offset (tim e slots) CBSR = CFI-offset (bits) CSCR = CFI-sub channel positions

3.5.2.2 Control Memory Reset

Since the hardware reset does not affect the MICO memories (Control and Data Memories), it is mandatory to perform a "software reset" of the CM. The CM-code '0000' (unassigned channel) should be written to each location of the CM. The data writt en to the CM-data field is then don’t care, e.g. FF

OMDR:OMS1..0 must be to '00'

MADR = FF MACR = 70

for this procedure (reset value).

Wait for STAR:MAC = 0

The resetting of the complete CM takes 256 RCL-clock cycles. During this time, the STAR:MAC-bit is set to logical 1.

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3.5.2.3 Initialization of Pre-processed Channels

After the CM-reset, all CFI time slots are unassigned. If the CFI is used as a plain PCMinterface, i.e. containing only switched channels (B-channels), the initialization steps below are not required. The initialization of pre-processed channels applies only to IOMor SLD-applications.

An IOM- or SLD-"channel" consists of four consecutive time slots. The first two time slots, the B-channels need not be initialized since they are already set to unassigned channels by the CM-reset command. Later, in the application phase of the software, the B-channels can be dynamically switched according to system requirements. The last two time slots of such an IOM- or SLD-channel, the pre-processed channels must be initialized for the desired functionality. There are four options that can be selected:

Table 2 Pre-Processed Channel Options at the CFI Even CFI Time Slot Odd CFI Time Slot Main

Applicatio n

Monitor/feature control channel

Also refer to figure 9.

Example

4-bit C/I-channel, D-channel not switched (decentr al D-channe l handling)

4-bit C/I-channel, D-cha nnel switched (central D-ch. handling)

6-bit SIG-channel

8-bit SIG/channel

IOM-1 or IOM-2 digital subscriber

IOM-2, analog subscriber

SLD, analog subscriber

In CFI-mode 0 the CFI-port shall be initialized as IOM-2 port with a 4-bit C/I-field. CFI time slots 0, 1, 4, 5, 8, 9 … 28, 29 are B-channels and need not to be initialized. CFI time slots 2, 3, 6, 7, 10, 11, …, 30, 31 are pre-proces sed channels and need to be

initialized:

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CFI-port, time slot 2 (even), downstr eam

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Operational Description

MADR = FF MAAR = 08 MACR = 7A

; the C/I-value '1111' will be transmitted upon CFI-act ivat ion

; addresses ts 2 down

; CM-code '1010'

Wait for STAR:MAC = 0

CFI-port, time slot 3 (odd), downstream

MADR = FFH; don’t care MAAR = 09 MACR = 7B

; addresses ts 3 down

; CM-code '1011'

Wait for STAR:MAC = 0

CFI-port, time slot 2 (even), upstream

MADR = FFH; the C/I-value '1111' is expected upon CFI-act iv ation MAAR = 88 MACR = 78

; address ts 2 up

; CM-code '1000'

Wait for STAR:MAC = 0

CFI-port, time slot 3 (odd), upstrea m

MADR = FFH; don’t care MAAR = 89 MACR = 70

; address ts 3 up

; CM-code '0000'

Wait for STAR:MAC = 0 Repeat the above programm ing steps fo r the rema ining CFI-tim e slots. This procedure can be speeded up by selecting the CM-initialization mode

(OMDR:OMS1..0=10). If this selection is made, the access time to a single memory location is reduced to 2.5 RCL-cycles. The complete initialization time for 8 IOM-2 channels is then reduced to 32 × 0.61 µs = 19,5 µs

3.5.2.4 Initializati on of the Upstr eam Data Mem ory (DM ) Trista te Fie ld

For each PCM time slot the tristate field defines wh ether the contents of the DM-data field are to be transmitted (low impedance), or whether the PCM time slot shall be set to high impedance. The co nten t of the trist at e field is n ot mod if ied by a har dware rese t. In order to have all PCM time slots set to high impedance upon the activation of the PCMinterface, each location of the tristate field must be loaded with the value '0000'. For this purpose, the "tristat e res et" com man d can be used:

OMDR = C0

MADR = 00

MACR = 68

; OMS1..0 = 11, norma l mode

; code field value '0000'

; MOC-code to initialize all tristate locations (1101B)

Wait for STAR:MAC = 0

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The initialization of the complete tristat e field takes 1035 RCL-cycles.

Note: It is also possible to program the value '1111' to the tristate field in order to have

all time slots switched to low impedance upon the activation of the PCM-interface.

Note: While OMDR:PSB = 0, all PCM-output drivers are set to high impedance,

regardless of the values written to the tristate field.

3.5.3 Activation of the PCM- and CFI-Interface s

With the MICO configured to the system requirement s, the PCM- and CFI-int erface can be switched to the operationa l mode.

The OMDR:OMS1..0 bits must be set (if this has not already be done) to the normal operation mode (OMS1..0 = 11). When doing this, the PCM-framing interrupt (ISTA:PFI) will be enabled. If the applied clock and framing signals are in accordance with the values programm ed to the PCM-registers, the PFI-inter rupt will be generated (if not masked) . When reading the status register, the STAR:PSS-bit will be set to logical 1.

To enable the PCM-output drivers set OMDR:PSB = 1. The CFI-interface is activated by programm ing OM DR: CS B = 1. This enab les the o utpu t c lock a nd f ram ing s ign als ( DCL and FSC), if these have been programm ed as outputs. It also enables the CFI-output drivers. The outp ut d river type can be se lected between "open d rain" and "t rista te" with the OMDR:COS-bit.

Example: Activation of the MICO for a typical IOM-2 application: OMDR = EE

; Normal operation mode (O MS1 ..0 = 11)

PCM-interface active (PSB = 1) PCM-test loop disabled (PTL = 0) CFI-output drivers : open dra in (COS = 1) Monitor handshake prot ocol select ed (MFPS = 1) CFI active (CSB = 1) Access to MICO registers via addr ess p ins A3..A0, used in demultiplexed mode only, normal operation (RBS = 0)

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4 Registers Summary

4.1 Register Address Arrangement

PEF 2015

Registers Summary

Group Reg Name Access Address

mux AD7..0

1. MICO

PCM

2. MICO CFI

3. MICO

PMOD RD/WR 20 PBNR RD/WR 22 POFD RD/WR 24

POFU RD/WR 26

PCSR RD/WR 28 PICM RD 2A CMD1 RD/WR 2C CMD2 RD/WR 2E CBNR RD/WR 30 CTAR RD /WR 32

CBSR RD/WR 34 CSCR RD/WR 36 MACR RD/WR 00

H H H

H H

H H H H

H H H

memory access

MAAR RD/WR 02

Address demux OMDR:RBS/ A3..0

1/0

1/1

1/2

1/3

1/4

1/5

1/6

1/7

1/8

1/9

1/A

1/B

0/0

0/1

Reset Value

Comment refer to

page

PCM-mode re g. 35 PCM-bit number reg. 36 PCM-offset

downstream reg. PCM-offse t upstream

reg. PCM-clock shif t reg. 38 dummy 38 CFI-mode reg. 1 39 CFI-mode reg. 2 41 CFI-bit number reg. 44 CFI time slot

adjustment reg. CFI-bit shift reg. 45 CFI-subchannel reg. 47 memory access

control reg. memory access

address re g.

MADR RD/WR 04

0/2

memory access data

reg.

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PEF 2015

Registers Summary

Group Reg Name Ac ce s s Addre s s

mux AD7..0

4. MICO

STDA RD/WR 06

synchro nous

STDB RD/WR 08

transfer

SARA RD/WR 0A

SARB RD/WR 0C

SAXA RD/WR 0E

SAXB RD/WR 10

STCR RD/WR 12

Address demux OMDR:RBS/ A3..0

0/3

0/4

0/5

0/6

0/7

0/8

0/9

Reset

Comment refer to

Value

synchron tra nsfer

data reg. A

synchron tra nsfer

data reg. B

synchron tra nsfer

recei ve address reg. A

synchron tra nsfer

recei ve address reg. B

synchron tra nsfer

transmit address reg. A

synchron tra nsfer

transmit address reg. B

00xxxxxxsynchron tra nsfer

cont rol reg.

page

5. MICO monitor/ feature control

6. MICO status/ control

MFAIR RD 14

MFSAR WR 14

MFFIFO RD/WR 16 CIFIFO RD 18

TIMR WR 18 STAR RD 1A CMDR WR 1A ISTA RD 1C MASK WR 1C OMDR RD/WR 1E

VNSR RD 3A

0/A

00xxxxxxMF-channel active

indication reg.

0/A

MF-channel

59 subscriber address reg.

H H

0/B 0/C

H H

MF-channel FIFO 60

0xxxxxxxsigna lin g ch an n el

60 FIFO

H H

0/C 0/D 0/D 0/E 0/E x/F

1/D

H H H H H

00 05 00 00 04 00

timer re g. 61

status register 62

command reg. 63

inter rupt status 65

mask register 66

operation mode reg. 67

versi on numbe r stat us

69 regist er

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PEF 2015

Registers Summary

4.2 Detailed Register Description

Unused bits and registers are accessible as described below to facilitate software portation from existing EPIC designs. They have to be programmed to the specified values. Writing other than the specified values may cause undefined behaviour.

4.2.1 PCM-Interface Registers

4.2.1.1 PCM-Mode Register (PMOD)

Access in demultiplexed µP-interface mode: read/write address: 0H,

OMDR:RBS = 1 Access in multiplexed µP-interface mode: read/write address: 20 Reset value: 00H

bit 7 bit 0

PMD1 PMD0 P CR PSM 0 0 0 0

PMD1..0 PCM-Mode. Defines the actual number of PCM-ports, the data rate range

and the data rate stepping.

PMD1..0 PCM-Mode Data Rate

[kbit/s]

min. max.

00 01 10

0 1 2

256 512 1024

2048 4096 8192

Data Rate Stepping [kbit/s]

256 512 1024

PCR PCM-Clock Rate.

0…single clock rate, data rate is identical with the clock frequency supplied

on pin PDC.

1…double clock rate, data rate is half the clock frequency supp lied on pin

PDC.

Note: Only single clock rate is allowed in PCM-mode 2!

PSM PCM Synchronization Mode.

A rising edge on PFS synchronizes the PCM -frame. PFS is not eva luated directly but is sampled with PDC. 0…the external PFS is evaluated with the falling edge of PDC. The internal

PFS (internal frame start) occurs with the next rising edge of PDC.

1…the external PFS is evaluated with the rising edge of PDC. The internal

PFS (internal frame start) occurs with this rising edge of PDC.

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4.2.1.2 Bit Number per PCM-Frame (PBNR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: 1

OMDR:RBS = 1

Access in multiplexed µP-interface mode: read/write address: 22

Reset value: FFH bit 7 bit 0

BNF7 BNF6 BNF5 BNF4 BNF3 BNF2 BNF1 BNF0

BNF7..0 Bit Number per PCM Frame.

PCM-mode 0: BNF7..0 = number of bits – 1 PCM-mode 1: BNF7..0 = (number of bits – 2) / 2 PCM-mode 2: BNF7..0 = (number of bits – 4) / 4

The value programmed in PBNR is also used to check the PFS-period.

4.2.1.3 PCM-Offset Dow nstream Register (POFD)

Access in demultiplexed µP-interface mode: read/write address: 2

OMDR:RBS = 1

Access in multiplexed µP-interface mode: read/write address: 24

Reset value: 00H bit 7 bit 0

OFD9 OFD8 OFD7 OFD6 OFD5 OFD4 OFD3 OFD2

OFD9..2 Of fs et Downstream bit 9…2.

These bits together with PCSR:OFD1..0 deter mine the offset of the PCMframe in downstream direction. The following formulas apply for calculating the required registe r value. BND is the bit number in downstream direction marked by the rising internal PFS-edge. BPF denotes the actual number of bits constitut in g a frame.

PCM-mode 0: OFD9..2 = mod

(BND – 17 + BPF)

BPF

PCSR:OFD1..0 = 0

PCM-mode 1: PFD9..1 = mod

(BND – 33 + BPF)

BPF

PCSR: PFD0 = 0

PCM-mode 2: OFD9..0 = mod

(BND – 65 + BPF)

BPF

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4.2.1.4 PCM-Offset Upstream Registe r (POFU)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: 3

OMDR:RBS = 1 Access in multiplexed µP-interface mode: read/write address: 26

Reset value: 00H bit 7 bit 0

OFU9 OFU8 OFU7 OFU6 OFU5 OFU4 OFU3 OFU2

OFU9..2 Of fset Upstream bit 9…2 .

These bits together with PCSR:OFU1..0 determ ine the offset of the PCMframe in upstream direction. The following formulas apply for calculating the required register value. B NU is the bit number in upstre am direction m arked by the rising internal PFS-edge. BPF denotes the actual number of bits constituting a frame.

PCM-mode 0: OFU9..2 = mod

(BNU + 23)

BPF

PCSR:OFU1..00 = 0

PCM-mode 1: OFU9..1 = mod

(BNU + 47)

BPF

PCSR:OFU0 = 0

PCM-mode 2: OFU9..0 = mod

(BNU + 95)

BPF

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4.2.1.5 PCM-Clock Shift Register (PCSR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: 4

OMDR:RBS = 1

Access in multiplexed µP-interface mode: read/write address: 28

Reset value: 00H bit 7 bit 0

DRCS OFD1 OFD0 DRE ADSRO OFU1 OFU0 URE

DRCS Double Rate Clock Shift.

0...the PCM-in put and out put data are not delayed

1...the PCM-in put and out put data are delay ed by one PDC-clo ck cycle

OFD1..0 Offset Downstream bits 1…0, see POFD-regi st er. DRE Downstream Rising Edge.

0…the PCM-d ata is sam pled with the fal ling edge of PDC 1…the PCM-data is sampled with the rising edge of PDC

ADSRO Add Shift Register on Output.

0...the PCM- out put dat a are not de layed

1...the PCM-out put dat a are delayed by one PDC-cloc k cycle.

Note: If both DRCS and ADSRO are set to logical 1, the PCM-output data ar e delayed

by two PDC-clock cycles.

OFU1..0 Offset Upstream bits 1…0, see POF U-regi st er. URE Upstream Rising Edge.

0…the PCM-data is transmitted with the falling edge of PDC 1…the PCM-d ata is transm itte d with the rising edge of PDC

4.2.1.6 PCM-Input Compari son Mism atch Regi ster (PICM)

Access in demultiplexed µP-interface mode: read address: 5

OMDR:RBS = 1 Access in multiplexed µP-interface mode: read addre ss: 2A Reset value: xx

Note: This register does not provide valid values for operation. It is a dummy register to

facilitate softwar e port ation from the EPIC to the MICO.

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4.2.2 Configurable Interface Register s

4.2.2.1 Configurable Interface Mod e Registe r 1 (CMD1)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: 6

OMDR:RBS = 1

Access in multiplexed µP-interface mode: read/write address: 2C

Reset value: 00H bit 7 bit 0

CSS CSM CSP1 CSP0 CMD1 CMD0 0 0

CSS Clock Source Selection.

0…PDC and PFS are used as clock and framing source f or the CFI. Cloc k

and framing signals derived from these sourc es are out put on DCL and FSC.

1…DCL and FSC are selected as clock and framing source for the CFI.

CSM CFI-Synchronization Mode.

The rising FSC-edge synchronizes the CFI-fr am e. 0…FSC is evaluated with every falling edge of DCL. 1…FSC is evaluated with every rising edge of DCL.

Note: If CSS = 0 is selected, CSM and PMO D:PSM must be program med identical.

CSP1..0 Clock Source Prescaler 1, 0.

The clock source frequency is divided according to the following table to obtain the CFI-r ef eren ce clo ck CRC L (refe r to figures 10 and 11).

CSP1,0 Prescaler Divi sor

00 2 01 1.5 10 1 11 not allowed

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CMD1..0 CFI-Mode1,0.

Defines the actual conf ig urat ion of the CFI-por t.

PEF 2015

Registers Summary

CMD1..0 CFI

Mode

00 0 128 2048 32N/3 2xDR DR, 2xDR 01 1 128 4096 64N / 3 DR DR 10 2 128 8192 64N/3 0.5xDR DR 11 3 128 1024 16N/3 4xDR DR, 2xDR

CFI-Data Rate

[kbi t/s]

min. max.

Min. Required CFI-Data Rate [kbi t/ s] Relati v e to PCM-Data Rate

where N = number of time slots in a PCM-frame

Note: For time slot encoding refer to figure 7.

Necessary Reference Clock (RCL )

DCL-Ou tput Freque nci es CMD1:CSS= 0

Figure 10 MICO Clock Sources for the CFI and PCM Interfaces if CMD1:CSS = 0

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PEF 2015

Registers Summary

Figure 11

MICO Clock Sources for the CFI and PCM Int erf aces if CMD1:CSS = 1

4.2.2.2 Configurable Interface Mod e Registe r 2 (CMD2)

Access in demultiplexed µP-interface mode: read/write address: 7

OMDR:RBS = 1

Access in multiplexed µP-interface mode: read/write address: 2E

Reset value: 00H bit 7 bit 0

FC2 FC1 FC0 COC CXF CRR CBN9 CBN8

FC2..0 Framing output Control.

Given that CMD1:CSS = 0, these bits determine the position of the FSCpulse relative to the CFI-frame, as well as the type of FSC-pulse gene rated. The position and width of the FSC-sign al with respec t to the CFI- frame can be found in the following two figures 12 and 13.

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Registers Summary

Figure 12 Position of the FSC-Signal for FC-Modes 0, 1, 2, 3 and 6

Figure 13 Position of the FSC-Signal for FC-Modes 4 and 6

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Application examples:

FC2 FC1 FC0 FC-Mode Main Applications

PEF 2015

Registers Summary

0 0 0 0 1 1 1 1

For further details on the framing output control please refer to section 2.2.3 of the EPIC Application Manual 10.92.

COC CFI-Ou tput Clock rate.

0 0 1 1 0 0 1 1

0…the frequency of DCL is identical to the CFI-data rate (all CFI-modes), 1…the frequency of DCL is twice the CFI-data rate (CFI-modes 0 and 3 only!)

0 1 0 1 0 1 0 1

0 1 2 3 4 5 6 7

IOM-1 multiplexed (burst) mode general purpose general purpose general purpose 2 ISAC-S per SLD-port reserved IOM-2 or SLD-modes software timed multiplexed applications

Note:Applies only if CMD1:CSS = 0.

CXF CFI- Trans mit on Falling edge.

0…the data is transmitt ed w ith the rising CRCL edge, 1…the data is transmitt ed w ith the falling CRCL edge.

CRR CFI- Re ceive on Rising edge.

0…the data is received with the falling CRCL edge, 1…the data is received wit h the rising CRCL edge.

Note:CRR must be set to 0 in CFI mode 3.

CBN9..8 CFI B it Number 9..8

these bits, together with the CBNR:CBN7..0, hold the number of bits per CFI frame.

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4.2.2.3 Configurable Interface Bit Number Register (CBNR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: 8

OMDR:RBS = 1 Access in multiplexed µP-interface mode: read/write address: 30

Reset value: FFH bit 7 bit 0

CBN7 CBN6 CBN5 CBN4 CBN3 CBN2 CBN1 CBN0

CBN7..0 CFI-Bit Number 7..0.

The number of bits that constitute a CFI-frame must be programmed to CBNR:CBN7..0 as indicated below.

CBN7..0 = number of bits − 1 For a 8-kHz frame struct ure, the number of bits per frame can be derived

from the data rate by division with 8000.

4.2.2.4 Configurabl e Interf ace Tim e Slot Adjustm ent Register (CTAR)

Access in demultiplexed µP-interface mode: read/write address: 9

OMDR:RBS = 1 Access in multiplexed µP-interface mode: read/write address: 32

Reset value: 00H bit 7 bit 0

0 TSN6 TSN5 TSN4 TSN3 TSN2 TSN1 TSN0

TSN6..0 Time Slot Number.

The CFI-framing signal (PFS if CMD1: CSS = 0 or FSC if CMD1:CSS = 1) marks the CFI time slot called TSN according to the following formula:

TSN6..0 = TSN + 2 E.g.: If the framing signal is to mark time slot 0 (bit 7), CTAR must be set to

(CBSR to 20H).

Note: If CMD1:CSS = 0, the CFI-fra me will be shifted – together with the FSC-out put

signal – with respect to PFS. The position of the CFI-fram e relative to the FSCoutput signal is not affected by these settings, but is instead determined by CMD2:FC2..0. If CMD1:CSS = 1, the CFI-frame will be shifted with respect to the FSC-input signal.

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4.2.2.5 Configurable Interface Bit Shift Regist er (CBSR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: A

OMDR:RBS = 1

Access in multiplexed µP-interface mode: read/write address: 34

Reset value: 00H bit 7 bit 0

SFSC CDS2 CDS1 CDS0 CUS3 CUS2 CUS1 CUS0

SFSC Shift FSC

0...default (behavio ur like EPIC-1 PEB 2055)

1...with doub le clock rate the FSC input is delayed by one CFI clock cycle (IOM-2 compatibility)

If the bit CBSR:SFSC is set the internal FSC will be delayed by one DCL clock cycle. This enables synchronization in double clock mode with the rising DCL edge according to IOM-2. The position of the data bit can now be adjusted using the CFI bit shift functionality as desc ribed below.

CDS2..0 CFI-Downstream bit Shift 2..0.

From the zer o o ffset bit pos ition ( CBSR = 20

) the CFI-frame (downstream

and upstream) c an be shifted by up to 6 bits to the left (wit hin the time slot number TSN programmed in CTAR) and by up to 2 bits to the right (within the previous time slot TSN - 1) by programming the CBSR:CDS2.. 0 bits:

CBSR:CDS2..0 Time Slot No. Bit No.

000 001

010 011 100 101 110 111

TSN - 1 TSN - 1 TSN TSN TSN TSN

TSN TSN

The bit shift programmed t o CBSR:CDS2..0 affects bo th the upstream and downstream frame position in the same way.

CUS3..0 CFI-Upstream bit Shift 3..0.

These bits shift the upstream CFI-frame relative to the downstream frame by up to 15 bits. Fo r CUS3..0 = 0000, the upstream frame is aligned wit h the downstream frame (no bit shift ).

1 0

7 6 5 4 3 2

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DCL

Ext. FSC

PEF 2015

Registers Summary

MICO

External FSC

CBSR:SFSC

DCL

Internal FSC

IOM-2 Specification Requirement

CBSR: SFSC = 0 EPIC behavior

Int. delayed FSC (CBSR: SFSC = '1')

(CBSR: SFSC = '1')

DDU

1st Bit

1st

Internal Fr ame Start if CBSR:SFSC = 0

2nd

Bit 3rd Bit 4th Bit 5th Bit

1st

Bit 2nd Bit

Internal Frame Start if CBSR:S FSC = 1

1st Bit 2nd Bit

Bit5thBit4thBit3rdBit2ndBit

3rd

Bit 4th Bit

Bit2ndBit1st

3rd

Bit 4th Bit

Bit

Bit2ndBit1st

3rd

Bit4thBit

Bit

4th

CBSR:SFSC = 1 Shifted 1 Bit to the left CBSR:CDS2..0 = 011

1st Bit

1st

2nd

Bit 3rd Bit 4th Bit 5th Bit

Bit5thBit4thBit3rdBit2ndBit

iom_inco.drw

Figure 14 Internal FSC Shift to enable a Synchronization with the Rising Edge of

DCL

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4.2.2.6 Configurable Interface Subchannel Regist er (CSCR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: B

OMDR:RBS = 1

Access in multiplexed µP-interface mode: read/write address: 36

Reset value: 00H bit 7 bit 0

0 0 0 0 0 0 SC01 SC00

SC01..00 CFI-Subchan nel Control for the CFI port.

The subchannel control bits SC01..SC00 sp ecify the bit positions to be exchanged with the data memory (DM) when a connection with a channel bandwidth as defined by the CM-code has been established:

SC01 SC00 Bit Positions for CFI Subchannels

having a Bandwidth of

64 kbit/s 32 kbit/s 16 kbit/ s

0 0 1 1

0 1 0 1

7..0

7..4

3..0

7..4

3..0

7..6

5..4

3..2

1..0

Note: In CFI mode 3 SC01 and SC00 control ports 0 and 4.

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4.2.3 Memory Access Registers

4.2.3.1 Memory Access Control Register (MACR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: 0

OMDR:RBS = 0 Access in multiplexed µP-interface mode: read/write address: 00

Reset value: xxH bit 7 bit 0

RWS MOC3 MOC2 MOC1 MOC0

CMC2 CMC1 CMC0

CMC3

With the MACR the µP selects the type of memory (CM or DM), the type of field (data or code) and the a ccess mode (re ad or write) of th e register access. When writing t o the control memory co de field, MACR also contains the 4 bit code (CM C3..0) defining the function of the addressed CFI time slot.

RWS Read/Write Select.

0…write operation on control or data memories 1…read opera tion on cont rol or data mem ories

MOC3..0 Memory Operation Code.

These bits d etermine the type a nd destination of the m emory operation as shown below.

CMC3..0 Control Memory Code.

These bits d etermine the type a nd destination of the m emory operation as shown below.

Note: Prior to a new access to any memory location (i.e. writing to MACR) the

STAR:MAC bit must be polled for ’0’.

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Registers Summary

1. Writing data to the upstream DM- dat a field (e.g. PCM- idle code) .

Reading data from the upstream or downst ream DM- data fiel d.

MACR:

RWS MOC3 MOC2 MOC1 MOC0 0 0 0

MOC3..0 defines the bandwidth and the position of the subchannel as shown below:

MOC3..0 Transferred Bits Channel Bandwidth

0000 0001 0011 0010 0111 0110 0101 0100

– bits 7..0 bits 7..4 bits 3..0 bits 7..6 bits 5..4 bits 3..2 bits 1..0

– 64 kbit/s 32 kbit/s 32 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s

Note: When reading a DM-data field location, all 8 bits are read regardless of the

bandwidth selected by the MOC-bits.

2. Writing to the upst ream DM-code (tr ist at e) fiel d.

Control-readi ng the upstr eam DM-code (tri st ate) .

MACR:

RWS MOC3 MOC2 MOC1 MOC0 0 0 0

MOC = 1100 Read/write tristate info from/to single PCM time slot MOC = 1101 Write tristate info to all PCM time slots

Note: The tristate field is exchanged with the 4 least significant bits (LSBs) of the MADR.

MADR:MD3 controls the PCM interface function of the bits 7 and 6, MD2 of bits 5 and 4, MD1 of bits 3 and 2, MD0 of bits 1 and 0 (0 = high impedance, 1 = low impedance).

3. Writing data to the upstream or downstream CM-data field (e.g. signaling code).

Reading data from the upstr eam or downst ream CM-data fi el d.

MACR:

RWS1001000

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Registers Summary

4. Writing data to the upstream or downstream CM-data and code field

(e.g. switching a CFI to/ fr om PCM- connect io n).

MACR:

0 1 1 1 CMC3 CMC2 CMC1 CMC0

The 4-bit code field of the control memory (CM) defines the functionality of a CFI time slot and thus the meaning of the corresponding data field. This 4-bit code, writ ten to the MA CR:CMC3..0 bit posit ions, will be transf erred to the CM-code field. The 8-bit MA DR value is at the sam e time transfe rred to the CM-data field. There are codes for switching applications, pre-processed applications and for direct µP-access applications, as shown below:

a) Switc hing Appli cat ions

CMC = 0000 Unassigned channel (e.g. cancelling an assigned channel) CMC = 0001 Bandwidth 64 kbit/s PCM time slot bits transferr ed: 7..0 CMC = 0010 Bandwidth 32 kbit/s PCM time slot bits transferr ed: 3..0 CMC = 0011 Bandwidth 32 kbit/s PCM time slot bits transferr ed: 7..4 CMC = 0100 Bandwidth 16 kbit/s PCM time slot bits transferr ed: 1..0 CMC = 0101 Bandwidth 16 kbit/s PCM time slot bits transferr ed: 3..2 CMC = 0110 Bandwidth 16 kbit/s PCM time slot bits transferr ed: 5..4 CMC = 0111 Bandwidth 16 kbit/s PCM time slot bits transferr ed: 7..6

Note: The corresponding CFI time slot bits to be transferred are chosen in the

CSCR-register.

b)Pre-processed Applications

Downstream:

Application Even CM Address Odd CM Address

Decentral D-channel handling CMC = 1000 CMC = 1011 Central D-channel handling CM C = 1010 CM C = PCM-code for a

2-bit subtime slot 6-bit Signaling (e.g. analog IOM) CMC = 1010 CMC = 1011 8-bit Signaling (e.g. SLD) CMC = 1010 CMC = 1011

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Registers Summary

Upstream:

Application Even CM Address Odd CM Address

Decentral D-channel handling CMC = 1000 CMC = 0000 Central D-channel handling CMC = 1000 CMC = PCM-code for a

2-bit subtime slot 6-bit Signaling (e.g. analog IOM) CM C = 1010 CMC = 1010 8-bit Signaling (e.g. SLD) CMC = 1011 CMC = 1011

c) µP-access Appli cat ions

MACR:

01111001

Setting CMC = 1001, initializes the corresponding CFI time slot to be accessed by the µP. Concurrently, the datum in MADR is written (as 8-bit CFI-idle code) to the CM-data field. The content of the CM-data field is directly exchanged with the corresponding time slot.

Note that once the CM-code field has been initialized, the CM-dat a field can be written and read as described in subsecti on 3.

5. Control-reading the upstream or downstream CM-code. MACR:

11110000

The CM-code can then be read out of the 4 LSBs of the MADR-register.

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4.2.3.2 Memory Access Address Register (MAAR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: 1

OMDR:RBS = 0

Access in multiplexed µP-interface mode: read/write address: 02

Reset value: xxH bit 7 bit 0

U/D

MA6 MA5 MA4 MA 3 MA2 MA1 MA0

The Memory Access Address Register MAAR specifies the address of the memory access. This address encodes a CFI time slot for control memory (CM) and a PCM time slot for data memory (DM) accesses. Bit 7 of MAAR (U/D

-bit) selects between upstream and downstream memory blocks. Bits MA6..0 encode the CFI- or PCM-port and time slot number as in the following tables:

Table 3

Time Slot Encoding for Data Memory Accesse s

Data Memory Address

PCM-mode 0 bit U/D

bits MA6..MA3, MA0 bits MA2..MA1

direction selection time slot selection have to be ’0’ (refer to figure 7)

PCM-mode 1 bit U/D

bits MA6..MA3, MA1, MA0 bit MA2

PCM-mode 2 bit U/D

bits MA6..MA0

direction selection time slot selection has to be ’0’ (refer to figure 7)

direction selection time slot selection

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Table 4

PEF 2015

Registers Summary

Time Slot Encoding for Control Mem ory Accesse s

Control Memory Address

CFI-mode 0 bit U/D

bits MA6..MA3, MA0 bits MA2..MA1

direction selection time slot selection have to be ’0’ (r efe r to figure 7)

CFI-mode 1 bit U/D

bits MA6..MA3, MA2, MA0 bit MA1

direction selection time slot selection has to be ’0’ (refer to figure 7)

CFI-mode 2 bit U/D

bits MA6..MA0

CFI-mode 3 bit U/D

bits MA6..MA4, MA0 bits MA3..MA1

direction selection time slot selection

direction selection time slot selection have to be 000 or 100 as only I/O0 and I/O4 are supported

4.2.3.3 Memory Access Data Register (MADR)

Access in demultiplexed µP-interface mode: read/write address: 2

OMDR:RBS = 0 Access in multiplexed µP-interface mode: read/write address: 04 Reset value: xxH

bit 7 bit 0

MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0

The Memory Access Data Register MADR contains the data to be transferred from or to a memory location. The meaning and the structure of this data depends on the kind of memory being accessed.

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4.2.4 Synchronous Transfer Registers

4.2.4.1 Synchronous Transfer Data Register (STDA)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: 3

OMDR:RBS = 0

Access in multiplexed µP-interface mode: read/write address: 06

Reset value: xxH bit 7 bit 0

MTDA7 MTDA6 M T DA5 MTDA4 MTDA3 MTDA2 MTDA1 MTDA0

The STDA-register buffers the data transferred over the synchronous transfer channel A. MTDA7 to MTDA0 hold the bits 7 to 0 of the respective t ime s lot. MTDA7 (MSB) is the

bit transmitted/received first, MTDA0 (LSB) the bit transmitted/received last over the serial interface.

4.2.4.2 Synchronous Transfer Data Register B (STDB)

Access in demultiplexed µP-interface mode: read/write address: 4

OMDR:RBS = 0

Access in multiplexed µP-interface mode: read/write address: 08

Reset value: xxH bit 7 bit 0

MTDB7 MTDB6 M T DB5 MTDB4 MTDB3 MTDB2 MTDB1 MTDB0

The STDB-register buffers the data transferred over the synchronous transfer channel B. MTDB7 to MTDB0 hold the bits 7 to 0 of the respective t ime s lot. MTDB7 (MSB) is the

bit transmitted/received first, MTDB0 (LSB) the bit transmitted/received last over the serial interface.

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Registers Summary

4.2.4.3 Synchronous Transfer Receive Address Register A (SARA)

PEF 2015

Access in demultiplexed µP-interface mode: read/write address: 5

OMDR:RBS = 0 Access in multiplexed µP-interface mode: read/write address: 0A

Reset value: xxH bit 7 bit 0

ISRA MTRA6 MTRA5 MTRA4 MTRA3 MTRA2 MTRA1 MTRA0

The SARA-register specifies for synchronous transfer channel A from which input interface and time slot t he serial dat a is extracte d. This data can then be read from the STDA-register.

ISRA Interface Select Receive for channel A.

0…selects the PCM-interf ace as the input interfa ce for synchr onous

channel A.

1…selects the CFI-interf ace as the input interfac e for synchr onous channel A.

MTRA6..0 µP-Transfer Receive Address for channel A; selects the por t and time slot

number at the interface selected by ISRA according to tables 3 and 4: MTRA6..0 = MA6..0.

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Registers Summary

4.2.4.4 Synchronous Transfer Receive Address Re gist er B (SARB)

PEF 2015

Access in demultiplexed µP-interface mode: read/write address: 6

OMDR:RBS = 0

Access in multiplexed µP-interface mode: read/write address: 0C

Reset value: xxH bit 7 bit 0

ISRB MTRB6 MTRB5 MTRB4 MTRB3 MTRB2 M TRB1 MTRB0

The SARB-register specifies for synchronous transfer channel B from which input interface and tim e slot the serial data is extrac ted. This data can then be read from the STDB register.

ISRB Interface Select Receive for channel B.

0…selects the PCM-interface as the input interface for synchro nous

channel B.

1…selects the CFI-interface as the input inter face for synchron ous

channel B.

MTRB6..0 µP-Transf er Receive Address for channel B; selects the port and time slot

number at the interface selected by ISRB according to tables 3 and 4: MTRB6..0 = MA6..0.

4.2.4.5 Synchronous Transfer Transmit Address Register A (SAXA)

Access in demultiplexed µP-interface mode: read/write address: 7

OMDR:RBS = 0

Access in multiplexed µP-interface mode: read/write address: 0E

Reset value: xxH bit 7 bit 0

ISXA MTXA6 MTXA5 MTXA4 MTXA3 MTXA2 MTXA1 MTXA0

The SAXA-register specifies for synchronous transfer channel A to which output interface and time slot the serial data conta ined in the STDA-registe r is sent.

ISXA Interface Select Transm it for chann el A.

0…selects the PCM-interf ace as th e output inter fac e for syn chro nous

channel A.

1…selects the CFI-interf ace as th e output inter fac e for syn chro nous

channel A.

MTXA6..0 µP-Tr ansf er Transm it Addr ess f or channel A; select s the port and time slot

number at the interface selected by ISXA according to tables 3 and 4: MTXA6..0 = MA6..0.

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Registers Summary

4.2.4.6 Synchronous Transfer Transmit Address Register B (SAXB)

PEF 2015

Access in demultiplexed µP-interface mode: read/write address: 8

OMDR:RBS = 0

Access in multiplexed µP-interface mode: read/write address: 10

Reset value: xxH bit 7 bit 0

ISXB MTXB6 MTXB5 MTXB4 MTXB3 MTXB2 MTXB1 MTXB0

The SAXB-register specifies for synchronous transfer channel B to which output interface and time slot the seri a l data conta ined in the STDB-regist er is sent.

ISXB Interfa ce Select Transmit for channel B.

0…selects the PCM-interf ace as the output interfa ce for synchr onous

channel B.

1…selects the CFI-int erface as the output interfa ce for synchr onous

channel B.

MTXB6..0 µP-Transfer Trans mit Addr ess for channel B; select s the por t and time slot

number at the interface selected by ISXB according to tables 3 and 4: MTXB6..0 = MA6..0.

4.2.4.7 Synchronous Transfer Control Register (STCR)

Access in demultiplexed µP-interface mode: read/write address: 09

OMDR:RBS = 0 Access in multiplexed µP-interface mode: read/write address: 12

Reset value: 00xxxxxxB bit 7 bit 0

TBE TAE CTB2 CTB1 CTB0 CTA2 CTA1 CTA0

The STCR-register bits are used to enable or disable the synchronous transfer utility and to determine the sub time slot bandwidth and position if a PCM-interface time slot is involved.

TAE, TBE Transfer Channel A (B) Enable.

1… enables the µP transfer of the corresponding channel. 0… disables the µP transfer of the corresponding channel.

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PEF 2015

Registers Summary

CTA2..0 Channel Type A (B); these bits determ ine the bandwidth of the channel and CTB2..0 the position of the relev ant bits in the time slo t according to the table below.

Note: If a CFI time slot is select ed as receive or transm it time slot of the synchronous

transfer, the 64-kbit/ s bandwidt h must be sele cte d (CT#2..CT#0 = 001).

CT#2 CT#1 CT#0 Bandwi dth Transferred Bits

000 001 010 011 100 101 110 111

not allowed 64 kbit/s 32 kbit/s 32 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s

– bits 7..0 bits 3..0 bits 7..4 bits 1..0 bits 3..2 bits 5..4 bits 7..6

4.2.5 Monitor/Feature Control Registers

4.2.5.1 MF-Channel Active Indica tion Registe r (MFAIR)

Access in demultiplexed µP-interface mode: read address: A

OMDR:RBS = 0

Access in multiplexed µP-interface mode: read address: 14

Reset value: 00xx xxxxB bit 7 bit 0

0 SO SAD5 SAD4 SAD3 SAD2 SAD1 SAD0

This register is only used in IOM -2 applications (act ive han dshake protoc ol) in order to identify active monitor channels when the "Search for active monitor channels" command (CM D R:MFSO) has been execu ted.

SO MF Channel Search On.

0…the search is complet ed. 1…the MICO is still busy looking for an active channel.

SAD5..0 Subscriber Address 5..0; after an ISTA:MAC-interrupt these bits point to the

time slot where an active channel has been found. The coding is identical to MFSAR:SAD5..SAD0.

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4.2.5.2 MF-Channel Subscriber Address Registe r (MFSAR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: write address: A

OMDR:RBS = 0 Access in multiplexed µP-interface mode: write address: 14

Reset value: xxH bit 7 bit 0

MFTC1 MFTC0 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0

The exchange of monitor data norma lly takes place with only one subscriber circu it at a time. This register serves to point the MF-handler t o that particu lar CFI time slot.

MFTC1..0 MF Channel Transfer Control 1..0; these bits, in addition to CMDR:MFT1,0

and OMDR:MFPS contro l the MF-channel transf er as indicated in tabl e 5.

SAD5..0 Subscriber address 5..0; these bits def ine the addressed subscriber. The

CFI time slot encoding is similar to the one used for Control Memory accesses using the MAAR-register (tables 3 and 4):

CFI time slot encoding of MFSAR derived from MAAR:

MAAR: MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0

↓↓↓↓↓↓

MFSAR: MFTC1 MFTC0 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0

MAAR:MA7 selects betwee n upst ream and downstre am CM -block s. This information is not required since the transf er direction is defined by CMDR (t rans mit or receive).

MAAR:MA0 selects between even and odd time slots. This information is also not required since MF-channels are always lo cate d on even time slots.

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4.2.5.3 Monitor/Feature Control Channel FIFO (MFFIFO)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: B

OMDR:RBS = 0 Access in multiplexed µP-interface mode: read/write address: 16 Reset value: xx

bit 7 bit 0

MFD7 MFD6 MFD5 MFD4 MFD3 MFD2 MFD1 M F D0

The 16-byte bi-directional M FFIFO provides intermediate storage for data by tes to be transmitted or re ceived over the mon itor or feature contro l channel.

MFD7..0 MF Data bits 7. .0; MFD7 ( MSB) is the fir st b it to be sent over the ser ia l CFI,

MFD0 (LSB) the last.

Note: The byte n+1 of an n-byte tra nsm it message in monitor channel is not defined.

4.2.6 Status/Control Registers

4.2.6.1 Signaling FIFO (CIFIFO)

Access in demultiplexed µP-interface mode: read address: C

OMDR:RBS = 0 Access in multiplexed µP-interface mode: read address: 18

Reset value: 0xxxxxxxB bit 7 bit 0

SBV SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0

The 9 byte deep CIFIFO store s the ad dres ses of CFI time slo ts in which a C/I- and/or a SIG-value change has t aken place. This address info rmation c an then be use d to read the actual C/I- or SIG-value from the control memor y.

SBV Signaling Byte Valid.

0…the SAD6..0 bits are invalid. 1…the SAD6..0 bits indicate a valid subscriber address. The polarity of SBV

is chosen such that the whole 8 bits of t he CIFIFO can be copied to the MAAR reg ister in or der to rea d the upstr eam C/ I- or SIG -value f rom the control memory.

SAD6..0 Subscriber Address bits 6..0; The CM-address which corresponds to the CFI

time slot where a C/I- or SIG-value change has taken place is encoded in these bits. For C/I-channels SAD6..0 point to an even CM-address (C/

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I-value), for SIG-channels SAD6..0 point to an odd CM-address (stable SIGvalue).

4.2.6.2 Timer Register (TIMR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: write address: C

OMDR:RBS = 0

Access in multiplexed µP-interface mode: write address: 18

Reset value: 00H bit 7 bit 0

SSR TVAL6 TVAL5 TVAL4 TVAL 3 TVAL2 TVAL2 TVAL0

The MICO timer can be used for 3 different purposes: timer interrupt generation (ISTA:TIG), FSC multiframe generation (CMD2:FC2..0 = 111) and last look period generation.

SSR S igna ling Sampl ing Rate.

0… the last look period is defined by TVAL6..0. 1… the last look period is fixed to 125 µs.

TVAL6..0 Timer Value bits 6..0; the timer perio d, equal to (1+TVAL6..0) × 250 µs, is

programm ed here. It can thus be adjusted wit hin the range of 250 µs up to 32 ms.

The timer is started as soon as CMDR:ST is set to 1 and stopped by writing the TIMR-register or by selecting OMDR:OMS0 = 0.

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4.2.6.3 Status Register (STAR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read address: D

OMDR:RBS = 0 Access in multiplexed µP-interface mode: read addre ss: 1A

Reset value: 05H bit 7 bit 0

MAC TAC PSS MFTO MFAB MFAE MFRW MFFE

The status register STAR displays the current state of certain events within the MICO. The STAR register bits do not generate interrupts and are not modified by reading STAR.

MAC Memory Access

0…no memory access is in operation. 1…a memory acces s is in operation. Hence, the mem ory access regist ers

may not be used.

Note: MAC is also set and reset during synchronous tr ansf er s.

TAC Timer Active

0…the timer is stopped. 1…the timer is running.

PSS PCM-Sy nchr onization St atus .

1…the PCM-interface is synchronized. 0…the PCM-interface is not synchronized. There is a mismatch between the

PBNR-value and the applied clock and framing signals (PDC/PFS) or OMDR:OMS0 = 0.

MFTO MF-Channel Transfer in Operation.

0…no MF-channel tran sfer is in operation. 1…an MF-channel tran sfer is in operation.

MFAB MF-Channel Transfer Aborted.

0…the remote receiver did not abort a handshake messag e transfe r. 1…the remote receiver aborted a handshake message transfer.

MFAE MFFIFO-Acce ss Enable.

0…the MFFIFO may not be accessed. 1…the MFFIFO may be either read or writ ten to.

MFRW MFFIFO Read/Write.

0…the MFFIFO is ready to be written to. 1…the MFFIFO may be read.

MFFE MFFIFO Empty

0…the MFFIFO is not em pt y. 1…the MFFIFO is empty.

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4.2.6.4 Command Register (CMDR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: write address: D

OMDR:RBS = 0

Access in multiplexed µP-interface mode: write address: 1A

Reset value: 00H bit 7 bit 0

0 ST TIG CFR MFT1 MFT0 MFSO MFFR

Writing a logical 1 to a CMDR-register bit starts the res pect ive operat ion. ST Star t Timer.

0…no action. If the timer shall be stopped, the TIMR-register must simply be

written with a random value.

1…starts the timer to run cyclically from 0 to the value programmed in

TIMR:TVAL6..0.

TIG Timer Interrupt Generation.

0…setting the TIG-bit to logical 0 together with the CMDR:ST-bit set to

logical 1 disables the interrupt generation.

1…setting the TIG-bit to logical 1 together with CMDR:ST-bit set to logical 1

causes the MICO to generate a periodic interrupt (ISTA:TIN) each time the timer expires.

CFR CIFIFO Reset.

0…no action. 1… resets the signaling FIFO within 2 RCL-periods, i.e. all entries and the

ISTA:SFI-bit are cleared.

MFT1..0 MF-channel Transfer Control Bits 1,0; these bits sta rt the monitor transf er

enabling the contents of the M FFIFO to be exchanged with the subscriber circuits as specified in MFSAR. The function of some command s depends furthermore on the selected protocol (OMDR:MFPS). Table 5 summarizes all available MF-commands.

MFSO MF-channel Search On.

0…no action. 1… the MICO start s to search for active MF-channels. Active channels are

characterized by an active MX-bit (logical 0) sent by the remote transmitter. If such a channel is found, the corresponding address is stored in MFAIR and an ISTA:MAC-interrupt is generated. The search is stopped when an active MF-channel has been found or when OMDR:O MS 0 is set to 0.

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MFFR MFFIFO Reset.

0…no actio n 1… resets the MFFIFO and all operations associated with the MF-handler

(except for the search function) within 2 RCL-periods. The MFFIFO is set into the state "MFFIFO empty", write access enabled and any monitor data transf er cur rent ly in process w ill be aborted.

Table 5

Summary of MF-Channel Commands

PEF 2015

Registers Summary

Transfer Mode CMDR:

MFT1,MFT0

Inactive 00 xxxxxxxx HS, no HS idle state Transmit 01 00 SAD5..0 HS, no HS IOM-2, IOM-1, SLD Transmit broadc ast 01 0 1xxxx xx HS, no HS I OM- 2, IOM- 1, SLD Test operation 01 10------ HS, no HS IOM-2, IOM-1, SLD Transmit

continuous Transmit + receive

same time slot Any # of bytes 1 byte expected 2 bytes expected 8 bytes expected 16 bytes expected

Transmit + receive same line 1 byte expected 2 bytes expected 8 bytes expected 16 bytes expected

11 00 SAD5..0 HS IOM-2

10 10 10 10 10

11 11 11 11

MFSAR Protocol

Selection

00 SAD5..0 00 SAD5..0 01 SAD5..0 10 SAD5..0 11 SAD5..0

00 SAD5..0 01 SAD5..0 10 SAD5..0 11 SAD5..0

HS no HS no HS no HS no HS

no HS no HS no HS no HS

Application

IOM-2 IOM-1 (IOM-1) (IOM-1) (IOM-1)

SLD SLD SLD SLD

HS: handshake facility enabled (OMDR:MFPS = 1) no HS: han dshake facility disable (OMDR:MFPS = 0)

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4.2.6.5 Interrupt Status Regist er (ISTA)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read address: E

OMDR:RBS = 0

Access in multiplexed µP-interface mode: read address: 1C

Reset value: 00H bit 7 bit 0

TIN SFI MFF I MAC PFI 0 SIN SOV

The ISTA-re gister should be re ad after an interr upt in order to d etermine the int errupt source.

TIN Timer interrupt; a timer interrupt previously requested with

CMDR:ST,TIG = 1 has occurred. The TIN-bit is reset by reading ISTA. It should be noted that the interrupt gen erat ion is per io dic, i.e. u nle ss stopped by writing to TIMR, the ISTA:TIN will be generated each time the timer expires.

SFI Signaling FIFO-Inte rrupt; this interrupt is generated if there is at least one

valid entry in the CIFIFO indicating a change in a C/I- or SIG-channel. Reading ISTA does not clear the SFI-bit. Instead SFI is cleared if the CIFIFO is empty which can be accomplished by reading all valid entries of the CIFIFO or by resetting the CIFIFO by set ting CMDR: CFR to 1.

MFFI MFFIFO-Interrupt; the last MF-channel command (issued by

CMDR:MFT1,MFT0) has been executed and the MICO is ready to accept the next command. Additional information can be read from STAR:MFTO…MFFE. M FFI is reset by reading ISTA.

MAC Monitor channel Active interrupt; the MICO has found an active monitor

channel. A new search can be started by reissuing the CMDR:MFSOcommand. M AC is reset by reading I STA.

PFI PCM-Framing Interrupt; the STAR:PSS-bit has changed its polarity. To

determine whether the PCM-interface is synchronized or not, STAR must be read. The PFI-bit is reset by reading ISTA.

SIN Synchr onous Tr ansf er Inter rupt; The SIN-interr upt is e nabled if at least one

synchronous transfer channel (A and/or B) is enabled via the STCR:TAE, TBE-bits. The SIN-interrupt is generated when the access window for the µP opens. After the occurrence of the SIN-interrupt the µP can read and/or write the synchronous transfer data registers (STDA, STDB). The SIN-bit is reset by reading ISTA.

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Registers Summary

SOV Synchronous Transfer Overflow; The SOV-interrupt is generated if the µP

fails to access the data registers (STDA, STDB) within the access window. The SOV-b it is reset by re ading ISTA.

4.2.6.6 Mask Register MICO (MASK)

Access in demultiplexed µP-interface mode: write address: E

OMDR:RBS = 0 Access in multiplexed µP-interface mode: write address: 1C

Reset value: 00H bit 7 bit 0

TIN SFI MFFI MAC PFI 1 SIN SOV

A logical 1 disables the corresponding interrupt as descr ibed in the ISTA-reg ister. A masked interrupt is stored internally and reported in ISTA immediately if the mask is

released. However , an SFI-inter rupt is also repor ted in ISTA if masked. In this case no interrupt is genera ted. W hen wr itin g reg ister MASK wh ile ISTA indicates a non masked interrupt, INT

is temporarily set into the inactive state.

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4.2.6.7 Operation Mode Regist er (O M D R)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read/write address: F

OMDR:RBS = X

Access in multiplexed µP-interface mode: read/write address: 1E

/3E

Reset value: 00H bit 7 bit 0

OMS1 OMS0 PSB PTL COS MFPS CSB RBS

OMS1..0 Operational Mode Selection; these bits determine the operation mode of the

MICO is working in according to the following table:

OMS1..0 Function

00 The CM- res et mode is used to reset all locations of the control

memory code and data fields with a single command within only 256 RCL-cycles. A typical application is resetting the CM with the command MACR = 70

which writes the contents of MADR (xxH)

to all data field locations and the code '0000' (unassigned channel) to all code field locations. A CM-reset should be made after each hardware reset. In the CM-reset mode the MICO does not operate normally i.e. the CFI- and PCM- inter faces are not operational.

10 The CM-initialization mode allows fast progr amming of the

control memory since each memory access takes a maximum of only 2.5 RCL-cycles compare d to the 9.5 RCL-cyc les in the normal mode. Acce sses ar e perform ed on ind ividua l addresses specified by MAAR. The initialization of control/signaling channels in IOM- or SLD- applications can for example be carried out in this mode. In the CM- initialization mode the MICO does also not work normally.

11 In the normal operation mode the CFI- and PCM-interfaces are

operationa l. Memor y accesses perf orm ed on single addres ses (specified by MAAR) take 9.5 RCL-cycles. An initialization of the complete data memory tris tate field takes 1035 RCL-cycles.

01 I n test mod e the MICO sustains normal operation. However

memory accesses are no longer performed on a specific address defined by MAAR, but on all locations of the selected mem or y, the contents of MAAR (including the U/D-bit!) being ignored. A test mode access takes 2057 RCL- cyc les.

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PSB PCM-Standby.

0…the PCM-interface output pin TxD is set to high impedance and if the

-pin is actually used as tristate control signal it is set to logical 1

TSC (inactive).

1…the PCM-output pin transmits the contents of the upstream data memory

or may be set to high impedance via the data me mor y tris tate field.

PTL PCM -Te st Loop.

0…the PCM-test loop is disabled. 1…the PCM-test loop is enabled, i.e. the physical transmit pin TxD is

internally connected to the corresponding physical receive pin RxD, such that data transmitted over TxD are internally looped back to RxD and data externally received over RxD are ignored. The TxD pin still outputs the contents of the upstream data memory according to the setting of the tristate field (only modes 0 and 1; mode 1 with AIS-bit set ).

PEF 2015

Registers Summary

COS CFI-Output driver Selection.

0…the CFI-o utpu t drivers are trista te drivers. 1…the CFI-outpu t drivers are open drain drivers.

MFPS Monitor/Feature Control Channel Protocol Selection

0...handshake facility disabled (SLD and IOM-1 applications).

1...handshake facility enabled (IOM-2 applications).

CSB CFI-Standb y.

0…the CFI-interface output pins DD, DU, DCL and FSC are set to high

impedance.

1…the CFI-o utpu t pins are active.

RBS Register Bank Selection. Used in demultiplexed data/address modes only.

0…to access the regist ers used during device oper ation. 1…to access the regist ers used during device in itializat io n

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4.2.6.8 Version Number Status Register (VNSR)

PEF 2015

Registers Summary

Access in demultiplexed µP-interface mode: read address: D

OMDR:RBS = 1

Access in multiplexed µP-interface mode: read address: 3A

Reset value: 02H bit 7 bit 0

IR 0 0 0 VN3 VN2 VN1 VN0

The VN3..0 bits are read only bits. IR Initialization Request; this bit is set to logical 1 after an inappropriate clocking

or after a power failure. It is reset to logical 0 after a control memory reset command: O MDR: O MS1. .0 = 00, MA CR = 7X

VN3..0 Version status Number; these bits display the MICO chip version as follows

VN3..0 Chip Versions

0010 V1.1

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PEF 2015

Registers Summary

4.3 Register Changes compared to the EPIC

4.3.1 PMOD AIS1..0 Have to be programmed to ’00 ’

AIC1..0 Hav e to be program me d to ’00’ (no alternat e inp ut com par is on suppor ted ).

4.3.2 PCSR DRCS Added.

ADSRO Added.

4.3.3 PICM

Values are not valid for operation.

4.3.4 CMD 1 CIS1..0 Have to be programmed to ’00’ (in CFI modes 0, 1 and 2 always logical port

0 is selected).

4.3.5 CSCR SC31..30 Hav e to be program me d to ’00 ’ (only port 0 supporte d).

SC21..20 SC11..10

4.3.6 ISTA PIM Not valid for operation (PCM Input Mismatch not supported as only one PCM

input line is provided).

4.3.7 MASK PIM Has to be programmed to ’1’ (PIM interrupt masked, refer to 4.3.6).

4.3.8 VSNR VN3..0 Fixed to ’0010’ (MICO V1.1).

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PEF 2015

UIE

Main

HFCN: Hybrid Fiber-Coaxial Network

Master Headend

OLT

Digital

Local

Core Network

Exchange

HFCN

Frame

UIE: User Interface Equipment

OLT: Optical Line Termination

HFCN

Distribution

Application Exam ples

5 Application Exam ples

5.1 Access Network

Access Networks are used in order to connect subscribers to the telecom network quickly and at low cost.

One possibility is to use the existing cable TV network to provide telephony services. An existing hybrid fiber-coaxial network (HFCN) that has been upgraded for upstream communication is the basis for such an Access Network. Figure 15 illustrates the functional model of an optica l access networ k (Fiber In The Loop FITL).

Figure 15 Functional Model of an Optical Access Netw ork

The maste r headend will serve one or multiple main distribut ion fram es. Via the HFCN the UIE is provided. Depending on t he num ber of supported user port s and how f ar the fiber is available, the configuration is called Fiber To The Home (FTTH), Fiber To The Building (FTTB) or Fiber To The Curb (FTTC).

The MICO can be used in a configuration where a maximum of 16 POTS or 8 ISDN subscribers are needed, e.g. FTTH or FTTB applications. Figure 16 shows an example of an user interface equipme nt (UIE) pro v iding two POTS and one ISDN subscr iber.

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MICO

Tuner

Modulation

Interface

SLICOFI

SLIC

IEC-Q

IOM-2 PCM

2 POTS

ISDN

Application Exam ples

Figure 16 Example using the MICO in an UIE

The MICO will replace the EPIC in applications where only a few subscribers have to be supported. It connects the subscriber circuits to the HF unit providing switching capability. Additionally the subscriber circuits are controlled via the implemented C/I- and Monitor-Handlers.

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Electric al Character istics

6 Electrical Characteristics Absolute Maxi mum Ratin gs Parameter Symbol Limit Values Unit

Ambient temp erat ur e under bias: PEF Storage temperature Voltage on any pin with respect to ground Maximum voltage on any pin

T T V V

stg

max

− 40 to 85 °C

− 65 to 125 °C

− 0.4 to VDD + 0.4 V

Note: Stress es above those listed here may cause per manent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliabili ty. Maximum ratings are abs olute ratings; exceeding only one of these values may cause irreversible dama ge to the integrat ed circu it.

DC Cha racteristi cs

PEF:

= − 40 to 85 °C; V

= 5 V ± 5 %; V

= 0 V

Parameter Symbol Li mit Values Unit Test Condition

min. max .

L-input voltage

− 0.4 0.8 V H-input voltage L-output voltage

H-output voltage H-output voltage

operational Power supply current

Input leakage current Output leakage current

V V

I I

CC CC

2.2 VDD + 0.4 V

0.45 V IOL = 7 mA

2.4

3.5

9.5

6.5 1

V V

mA mA

µA µA

(pins DU, DD)

= 2 mA

(all other)

= − 400 µA

= − 200 µA

= 5 V,

inputs at 0 V or

, no output loads PDC > 4.096 MHz PDC ≤ 4.096 MHz

0 V < VIN < VDD to 0 V

0 V <

< VDD to 0 V

OUT

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Electric al Character istics

Note: The listed charact eristics are ensured over the operating range of the integrated

circuit. Typical characterist ics specify mean valu es expected ov er the production

spread. If not othe rwise specified, typ ical charact eristics apply a t the given supply voltage.

Capacitances

= 25 °C; VDD = 5 V ± 5 %, VSS = 0 V, fC = 1 MHz, unmeasured pins returned to VSS.

Parameter Symbol Limit Values Unit

min. max.

= 25°C and

Input capacitance, Output capacitance I/O capacitance

= 1 MHz C

C C

OUT

I/O

510pF 8

10 20 pF

AC-Characteristics

Ambient te mpe rat ure u nd er b ia s range,

= 5 V ± 5 %.

Inputs are driven to 2.4 V for a logical '1' and to 0.4 V for a logical '0'. Timing measureme nts are made at 2.0 V for a logical '1' and at 0.8 V for a logical '0'. The AC-testing input/o utpu t wave forms are shown below.

2.4 V

0.4 V

2.0 V Test Points

0.8 V 0.8 V

2.0 V Device

Under

Test

100 pF

ITS09737

Figure 17 I/O-Wave Form for AC-Test

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Electric al Character istics

Bus Interface Ti ming Parameter Symbol Limit Values Unit

min. max.

R or W R or W RD

set-up to DS t hold time from DS t

-pulse width t

-control interval t Data output delay from RD Data float delay from RD WR

-pulse width t

-control interval t

WR Data set-up tim e to W R Data hold time from WR

xCS, DSxCS t

xCS, DS xC S t ALE-pulse width Address set-u p time to ALE Address hold time from ALE ALE set-up time to WR Address set-u p time to WR

, RD t

t t

t t t

DSD

RWh

ALS

0ns

10 ns

80 ns 40 ns

80 ns

25 ns 45 ns 40 ns

0ns 15 ns 30 ns 10 ns 15 ns

8ns 10 ns

Address hold time from WR Address hold time after reset

, RD t

A1, A0

RES

AHR

0ns 10 ns

AHR

up_sel.drw

Figure 18 Microprocessor Interface Sele cti on: Addres s Hold Time afte r Reset

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P Read Cycle

CSx RD

D0D7

PEF 2015

Electric al Character istics

Data

ITT05854mod

Write Cycle

CS xWR

D0-

Address Timing Multiplexed Bus Mode

ALE

WRxCS

CSxRD

Data

ITT05855mod

ALS

AD0- AD7

Address

ITT05856mod

Figure 19 a Siemens/Intel Bus Mode

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xWR

RDxCS

PEF 2015

Electric al Character istics

A0 - A

Figure 19 b Siemens/Int el Bus Mode

Address

ITT05857mod

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P Read Cycle

R/W

DSD

RWh

PEF 2015

Electric al Character istics

CSx DS

D0 -D7

P Write Cycle

R / W

DSD

Data

RWh

T5858mod

D7-

Data

T5859mod

Address Tim ing

DSxCS

- 3A0A

Address

T5860mod

Figure 20 Motorola Bus Mode

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Electric al Character istics

PCM and Configurable Inter face Ti mi ng Parameter Symbol Limit Values Unit Test Condi ti ons

min. m ax.

Clock period Clock period low

Clock period high Clock period Clock period low Clock period high Frame set-up time to clock Frame hold time from clock Data clock delay Serial data input set-up time Serial data hold time Serial data input set-up time Serial data hold time Serial data input set-up time Serial data hold time

CPL

CPH

CPL

CPH

DCD

240 ns

80 ns

clock frequency ≤ 4096 kHz

100 ns 120 ns

50 ns

clock frequency > 4096 kHz

50 ns 25 ns 50 ns

125 ns

7ns 35 ns 15 ns 55 ns 20 ns 50 ns

PCM-input data frequency > 4096 kbit/s

PCM-input data frequency ≤ 4096 kbit/s

CFI- inp ut data frequency > 4096 kbit/s

Serial data input set-up time Serial data hold time PCM-serial data output delay Tristate cont rol dela y CFI-seria l data output delay CFI-seria l data output delay

CDF

CDR

0ns 75 ns

CFI- inp ut data frequency ≤ 4096 kbit/s

55 ns 60 ns 65 ns falling clock edge

– 90 ns rising clock edge

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Electric al Character istics

Figure 21 Configurable Interface Timing, CMD:CSP1,0 = 10 (prescalor divisor = 1)

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Electric al Character istics

Figure 22 Configurable Interface Tim i ng, CMD: CSP1 ,0 = 01

(prescalor div isor = 1,5)

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Electric al Character istics

Figure 23 Configurable Interface Timing, CMD:CSP1,0 = 00 (prescalor divisor = 2)

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PDC

PEF 2015

Electric al Character istics

CPL

CPH

PFS (PMOD:PSM=0)

(PMOD:PSM=1)PFS

(PCSR:URE=1)TxD

TSC (PCSR:URE=1)

(PCSR:DRE=0)RxD

TxD (PCSR:URE=0)

(PCSR:URE=0)TSC

RxD

(PCSR:DRE=1)

(PCSR:URE=1)TxD

(PCSR:URE=1)TSC

(PCSR:DRE=0)RxD

(PCSR:URE=0)TxD

TSC (PCSR:URE=0)

(PCSR:DRE=1)RxD

1 Bit of Framest2

FrameofBit

FrameofBit FrameofBit

FrameofBit1

PCR

Bit of Frame1

PMOD

Bit of Frame

1stBit of Frame

FrameofBit

Bitst1 of Frame

=PCR

FrameofBit

PMOD

1 Bit of Frame

Frameof1stBit

ITD05871

Figure 24 PCM-Interface Tim in g

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7 Package Outlines

P-DSO-28

(Plastic Dual Small Outline)

PEF 2015

Package Outlines

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our Data Book “Package Informati on”.

SMD = Surface Mounted Device

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Dimensions in mm

Datasheet PEF2015 Datasheet (Siemens)

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Overview

1.1 Features

1.3 Pin Description

1.4 Logic Symbol

1.5 Functional Block Diagram

2 Functional Description

2.1 Configurable Interface CFI

2.2 Serial PCM Interface

2.3 Microprocessor Int erf ace

2.4 Memory Struct ure and Sw itching

2.5 Pre-processed Channels , Layer-1 Support

2.6 Special Functions

3 Operational Descripti o n

3.1 Microprocessor Int erf ace O perat ion The MICO is programm ed via an 8-bit para llel interface that can be selected to be

3.2 Clocking To operate properly , the MICO al ways requir es a PDC-cloc k.

3.3 Reset A reset pulse of at least 4 PDC clock cycles has to be applied at the RES pin. The reset

3.4 MICO Operation

3.4.1 PCM-Interface

3.4.2 Configurable Interface

3.4.3 Switching Functi on s

3.4.4 Special Functio ns

3.5 Initialization Procedure

3.5.1 Hardware Reset

3.5.2 MICO Initialization

3.5.2.1 Register Initialization

3.5.2.2 Control Memory Reset

3.5.2.3 Initialization of Pre-processed Channels

3.5.3 Activation of the PCM- and CFI-Interface s

4 Registers Summary

4.1 Register Address Arrangement

4.2 Detailed Register Description

4.2.1 PCM-Interface Registers

4.2.1.1 PCM-Mode Register (PMOD)

4.2.1.2 Bit Number per PCM-Frame (PBNR)

4.2.1.3 PCM-Offset Dow nstream Register (POFD)

4.2.1.4 PCM-Offset Upstream Registe r (POFU)

4.2.1.5 PCM-Clock Shift Register (PCSR)

4.2.2 Configurable Interface Register s

4.2.3 Memory Access Registers

4.2.3.1 Memory Access Control Register (MACR)

4.2.3.2 Memory Access Address Register (MAAR)

4.2.3.3 Memory Access Data Register (MADR)

4.2.4 Synchronous Transfer Registers

4.2.4.1 Synchronous Transfer Data Register (STDA)

4.2.5 Monitor/Feature Control Registers

4.2.6 Status/Control Registers

4.2.6.1 Signaling FIFO (CIFIFO)

4.2.6.2 Timer Register (TIMR)

4.2.6.3 Status Register (STAR)

4.2.6.4 Command Register (CMDR)

4.2.6.5 Interrupt Status Regist er (ISTA)

4.2.6.6 Mask Register MICO (MASK)

4.2.6.7 Operation Mode Regist er (O M D R)

4.2.6.8 Version Number Status Register (VNSR)

4.3 Register Changes compared to the EPIC

4.3.1 PMOD AIS1..0 Have to be programmed to ’00 ’

4.3.2 PCSR DRCS Added.

4.3.3 PICM

4.3.4 CMD 1 CIS1..0 Have to be programmed to ’00’ (in CFI modes 0, 1 and 2 always logical port

4.3.5 CSCR SC31..30 Hav e to be program me d to ’00 ’ (only port 0 supporte d).

4.3.6 ISTA PIM Not valid for operation (PCM Input Mismatch not supported as only one PCM

4.3.7 MASK PIM Has to be programmed to ’1’ (PIM interrupt masked, refer to 4.3.6).

4.3.8 VSNR VN3..0 Fixed to ’0010’ (MICO V1.1).

5 Application Exam ples

5.1 Access Network

Electric al Character istics

7 Package Outlines