Datasheet PDSP16318A, PDSP16318GC1R, PDSP16318IG, PDSP16318MC Datasheet (MITEL)

PDSP16318/PDSP16318A

PDSP16318/16318A

Complex Accumulator

Advance Information

Supersedes version DS3708 - 2.4 September 1996 DS3708 - 3.1 November 1998

The PDSP16318/A contains two independent 20-bit
Adder/Subtractors combined with accumulator registers and
shift structures. The four port architecture permits full 20MHz
throughout in FFT and filter applications.

Two PDSP16318As combined with a single PDSP16112A
Complex Multiplier provide a complete arithmetic solution for
a Radix 2 DIT FFT Butterfly. A new complex Butterfly result
can be generated every 50ns allowing 1K complex FFTs to be
executed in 256µs.

FEATURES

GC100

■ Full 20MHz Throughout in FFT Applications

■ Four Independent 16-bit I/O Ports

■ 20-bit Addition or Accumulation

■ Fully Compatible with PDSP16112 Complex Multiplier

■ On Chip Shift Structures for Result Scaling

■ Overflow Detection

■ Independent Three-State Outputs and Clock

Enables for 2 Port 20MHz Operation

■ 1.4 micron CMOS

■ 500mW Maximum Power Dissipation

■ 100 CQFP package

APPLICATIONS

■ High speed Complex FFT or DFTs

■ Complex Finite Impulse Response (FIR) Filtering

■ Complex Conjugation

■ Complex Correlation/Convolution

A

REG DELAY

Fig.1 Pin connections - Top view (GC100)

ASSOCIATED PRODUCTS

PDSP16112 16 x 12 Complex Multiplier
PDSP16116 16 x 16 Complex Multiplier
PDSP1601 ALU and Barrel Shifter
PDSP16330 Pythagoras Processor

ORDERING INFORMATION

Industrial (-40°C to +85°C)

PDSP16318A/IG/GC1R (20MHz - QFP)

Military (-55°C to +125°C)

PDSP16318/MC/GC1R (10MHz - QFP

MIL STD 883C Screened)

N.B. Further details of the Military grade part are available

in a separate datasheet

B

SHIFT

REG

C

A

A

SHIFT

B

REG

B

Fig. 2 PDSP16318 simplified block diagram

REG

D

1

PDSP16318/16318A

16 16

A

CLK

B

A REG

REG

S2:0ASRDELCEA

8

CYCLE
DELAY

1616

MUX

MUX

MUX

20

B

20 16 16

SHIFT

A

20

20

20

MS

20

A

B

REG

REG

20

SHIFT

REG

CLR OVR

REG

OEC

D

1616

D

CEB ASI OED

Fig. 3 Block diagram

2

FUNCTIONAL DESCRIPTION

The PDSP16318 is a Dual 20-bit Adder/Subtractor
configured to support Complex Arithmetic. The device may be
used with each of the adders allocated to real or imaginary
data (e.g. Complex Conjugation), the entire device allocated
to Real or Imaginary Data (e.g. Radix 2 Butterflys) or each of
the adders configured as accumulators and allocated to real
or imaginary data (Complex Filters). Each of these modes
ensures that a full 20MHz throughput is maintained through
both adders, the first and last mode illustrating true Complex
operation, where both real and imaginary data is handled by
the single device.

Both Adder/Subtractors may be controlled
independently via the ASR and ASI inputs. These controls
permit A + B, A - B, B - A or pass A operations, where the A
input to the Adder is derived from the input multiplexer. The

CLR control line allows the clearing of both accumulator
registers. The two multiplexers may be controlled via the MS

inputs, to select either new input data, or fed-back data from

PDSP16318/16318A

the accumulator registers. The PDSP16318 contains an 8­cycle deskew register selected via the DEL control. This
deskew register is used in FFT applications to ensure correct
phasing of data that has not passed through the PDSP16112
Complex Multiplier.

The 16-bit outputs from the PDSP16318 are derived from
the 20-bit result generated by the Adders. The three bit S2:0
input selects eight different shifted output formats ranging
from the most significant 16 bits of the 20-bit data, to the least
significant 13 bits of the 20-bit data. In this mode the 14th, 15th
and 16th bits of the output are set to zero. The shift selected
is applied to both adder outputs, and determines the function
of the OVR flag. The OVR flag becomes active when either of
the two adders produces a result that has more significant
digits than the MSB of the 16-bit output from the device. In this
manner all cases when invalid data appears on the output are
flagged.

Symbol

A15:0
B15:0

C15:0
D15:0
CLK

CEA

CEB

OEC

OED

OVR

ASR1:0
ASI1:0

CLR

MS

S2:0

Type

Input
Input

Output
Output
Input
Input
Input
Input

Input

Output

Input
Input
Input

Input

Input

Description

Data presented to this input is loaded into the input register on the rising edge of CLK. A15 is the MSB.
Data presented to this input is loaded into the input register on the rising edge of CLK. B15 is the MSB

and has the same weighting as A15.
New data appears on this output after the rising edge of CLK. C15 is the MSB.
New data appears on this output after the rising edge of CLK. C15 is the MSB.

Common Clock to all internal registers
Clock enable: when low the clock to the A input register is enabled.
Clock enable: when low the clock to the B input register is enabled.
Output enable: Asynchronous 3-state output control: The C outputs are in a high impedance

state when this input is high.
Output enable: Asynchronous 3-state output control: The D outputs are in a high impedance

state when this input is high.
Overflow flag: This flag will go high in any cycle during which either the output data overflows the number

range selected or either of the adder results overflow. A new OVR appears after the rising edge of the
CLK.

Add/subtract Real: Control input for the 'Real' adder. This input is latched by the rising edge of clock.
Add/subtract Imag: Control input for the 'Imag' adder. This input is latched by the rising edge of clock.
Accumulator Clear: Common accumulator clear for both Adder/Subtractor units. This input is latched by

the rising edge of CLK.
Mux select: Control input for both adder multiplexers. This input is latched by the rising edge of CLK.

When high the feedback path is selected.
Scaling control: This input selects the 16-bit field from the 20-bit adder result that is routed to the outputs.

This input is latched by the rising edge of CLK.

DEL

VCC
GND

Input

Power
Ground

Delay Control: This input selects the delayed input to the real adder for operations involving the
PDSP16112. This input is latched by the rising edge of CLK.

+5V supply: Both Vcc pins must be connected.
0V supply: Both GND pins must be connected.

3

PDSP16318/16318A

DEL

0
1

Delay Mux Control

A port input
Delayed A port input

GC pin

77
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

5

Function

D7
D8
D9

D10
GND
VCC

D11

D12

D13

D14

D15

C15

C14

C13

C12
VCC
GND

C11

C10

C9
C8

GC pin

6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

Function

C7
C6
C5
C4
C3
C2
C1
C0

OED
OEC

S2
S1
S0

MS
ASI1
ASI0

DEL
CLR

ASR1
ASR0

A0

GC pin

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

Function

A1
A2
A3
A4
A5
A6
A7
A8

A9
A10
A11
A12
A13
A14
A15

CEA

B15
B14
B13
B12
B11

Device Pinout for ceramic QFP (GC100)

GC pin

56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76

Function

B10

B9
B8
B7
B6
B5
B4
B3
B2
B1
B0

CLK

CEB

OVR

D0
D1
D2
D3
D4
D5
D6

ASR or ASI

ASX1

S2:0 Adder result

S0

S1

S2

0

0

0
0
0
0
1
1
1
1

1

0

0

1

1

1

0

0

1

0

0

1

1

1

ASX0

0
0
1
1

191518

0
1
0
1

14
15

ALU Function

A + B

A
A - B
B - A

17

16

13

12

14

13

15

14
15

15

11
12
13
14
15

MS

Real and Imag' Mux Control

0

B port input/Del mux output

1

C accumulator/D accumualtor

11

12

13

14

7

8

9

10
11
12
13
14
15

10
11
12
13
14
15

10
11
12
13
14
15

8

9

9
10
11
12
13
14

10

6
7
8

9
10
11
12
13

10
11
12

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5
6
7
8
9

10
11

4

5

5

6

6

7

7

8

8

9

9

10

2

3

3

4

4

5

5

6

6

7

7

8

8

9

0

1
2
3
4
5
6
7

0

1
2
3
4
5
6

0

1
2
3
4
5

0

1

1

2

2

3

3

4

NOTE
the output data is padded with zeros.

4

This table shows the portion of the adder result passed to the D15:0 and C15:0 outputs. Where fewer than 16 adder bits are selected

PDSP16318/16318A

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply voltage VCC -0.5V to 7.0V
Input voltage VIN -0.9V to VCC +0.9V
Output voltage VOUT -0.9V to VCC +0.9V
Clamp diode current per pin Ik (see Note 2) 18mA
Static discharge voltage (HMB) VSTAT 500V
Storage temperature range TS -65°C to +150°C
Ambient temperature with
power applied Tamb

Industrial -40°C to +85°C

Military -55°C to +125°C
Junction temperature 150°C
Package power dissipation PTOT 1000mW

NOTES

1. Exceeding these ratings may cause permanent damage.
Functional operation under these conditions is not implied.

2. Maximum dissipation or 1 second should not be exceeded, only
one output to be tested at any one time.

3. Exposure to absolute maximum ratings for extended periods may
affect device reliability.

THERMAL CHARACTERISTICS

Package Type

GC

θ

JC °C/W

12

θ

JA °C/W

35

Test Waveform - measurement level

Delay from output
high to output
high impedance

Delay from output
low to output
high impedance

Delay from output
high impedance to
Output low

Delay from output
high impedance to
Output high

NOTES

1. V

- Voltage reached when output driven high

H

2. V

- Voltage reached when output driven low

L

V

V

1.5V

1.5V

H

L

I

OL

0.5V

0.5V

0.5V

0.5V

1.5V

DUT

100p

I

OH

5

PDSP16318/16318A

ELECTRICAL CHARACTERISTICS

Test conditions (unless otherwise stated):

T

(Commercial) = 0°C to +70°C, VCC = 5.0V ± 5%, GND = 0V

amb

T

(Industrial) =-40°C to +85°C, VCC = 5.0V ± 10%, GND = 0V

amb

T

(Military) =-55°C to +125°C, VCC = 5.0V ± 10%, GND = 0V

amb

STATIC CHARACTERISTICS

Value

Characteristic Symbol Units Conditions

Min. Typ. Max.

Output high voltage V
Output low voltage V
Input high voltage V
Input low voltage V
Input leakage current I
Output leakage current l
Output SC current I
Input capacitance C

OH

OL
IH

IL
IL
oz
OS

IN

SWITCHING CHARACTERISTICS

Characteristic

Clock period
Clock High Time
Clock Low Time
A15:0, B15:0 setup to clock rising edge
A15:0, B15:0 hold after clock rising edge
MS, S2:0, ASI setup to clock rising edge

DEL, ASR,
DEL, ASR, CLR, MS, S2:0, ASI hold after

clock rising edge

CEA, CEB setup to clock falling edge
CEA, CEB hold after clock rising edge

Clock rising edge to OVR, C15:0, D15:0

OEC/OED low to C15:0/D15:0 high data valid
OEC/OED low to C15:0/D15:0 low data valid
OEC/OED high to C15:0/D15:0 high impedance

Vcc current

CLR setup to clock rising edge

2.4 - V IOH = 3.2mA

- 0.4 V lOL=-3.2mA

3.5 - V

- 0.5 V

-10 +10 µA GND < VIN<V

-50 - +50 µA GND <V
20 - 200 mA Vcc = Max

OUT

< V

- 9 - pF

Value

Industrial

Min.

50
15
15

5
2

10

5
2

2
8
5

-

-

-

-

Max.

-

-

-

-

-

-

-

-

-

­30
30
30
30

110

Value

Military

PDSP16318PDSP16318A

Min.

100

20
20

8
2

10

8
2

2
8
5

-

-

-

-

Max.

-

-

-

-

-

-

-

-

-

­40
40
40
40
70

Units

ns
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns
ns
ns
ns

mA

CC

CC

Conditions

2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF

CC = max,

V
TTL input levels
Outputs unloaded,
fCLK = max

Vcc current

NOTES

1. LSTTL is equivalent to IOH = 20 microamps, IOL = -0.4mA

2. Current is defined as negative into the device

3. CMOS input levels are defined as:
VIL = 0.5
VIH = VDD - 0.5

6

VCC = max,

-

-

60

30

mA

CMOS input levels
Outputs unloaded,
fCLK = max

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