Datasheet PD488588FF-C60-53-DH1, PD488588FF-C71-45-DH1, PD488588FF-C80-45-DH1 Datasheet (ELPIDA)

DATA SHEET

288M bits Direct Rambus DRAM

µµµµ

PD488588 (512K words ×××× 18 bits ×××× 32s banks)

Description

The Direct Rambus DRAM (Direct RDRAM) is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required.

PD488588 is 288Mbits Direct Rambus DRAM

µ

The (RDRAM

The use of Rambus Signaling Level (RSL) technology permits 600MHz to 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25ns per two bytes (10ns per sixteen bytes).

The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM’s four banks support up to four simultaneous transactions.

System oriented features for mobile, graphics and large memory systems include power management, byte masking.

The package suitable for desktop as well as low-profile add-in card and mobile applications. Direct RDRAMs operate from a 2.5V



), organized as 16M words by 18 bits.

PD488588 is offered in a CSP horizontal

µ

supply.

Features

• Highest sustained bandwidth per DRAM device

— 1.6 GB/s sustained data transfer rate — Separate control and data buses for maximized

efficiency — Separate row and column control buses for easy

scheduling and highest performance — 32 banks: four transactions can take place

simultaneously at full bandwidth data rates

• Low latency features

— Write buffer to reduce read latency — 3 precharge mechanisms for controller flexibility — Interleaved transactions

• Advanced power management:

— Multiple low power states allows flexibility in power consumption versus time to active state

— Power-down self-refresh

• Overdrive current mode

• Organization: 2K bytes pages and 32 banks, x 18

• Uses Rambus Signaling Level (RSL) for up to

800MHz operation

• Package : 80-ball FBGA (

BGA

µ





) (17.16 × 10.2)

Document No. E0039N30 (Ver. 3.0) Date Published July 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2001-2002 NEC Corporation 2000

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

µµµµ

PD488588

Ordering Information

Part number

PD488588FF-C60-53-DH1 512K x 18 x 32s 600 53 80-ball FBGA (µBGA)

µ

PD488588FF-C71-45-DH1 711 45 (17.16 × 10.2)

µ

PD488588FF-C80-45-DH1 800 45

µ

Note: The “32s” designation indicates that this RDRAM core is composed of 32 banks which use a “split” bank

architecture

Organization*

words × bits × Internal

Banks

Clock frequency MHz (max.)

/RAS access time (ns)

Package

2

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

Pin Configuration

80-ball FBGA (

µµµµ

BGA) (17.16 ×

× 10.2)

××

Top View

10 O O O O

9 8 O O O O O O O O O O O O O O O O O O 7 O O O O O O O O O O O O O O O O O O 6 5 4 O O O O O O O O O O O O O O O O O O 3 O O O O O O O O O O O O O O O O O O 2 1 O O O O

A B C D E F G H J K L M N P R S T U

VDD

10

9

GND

8

VDD

7 6 5

GND GND DQA6 DQA4 DQA2 DQA0 CFM CFMN ROW1 COL4 COL2 COL0 DQB0 DQB2 DQB4 DQB6 GND GND

4

VDD

3 2 1

GND

VDD

CMD

DQA8 DQA7 DQA5 DQA3 DQA1 CTMN CTM ROW2 ROW0 COL3 COL1 DQB1 DQB3 DQB5 DQB7 DQB8

GND SCK VCMOS GND

VDD

GND GND

VDD

GND GNDa GNDa

VDD

GND

VDD VDD

VDDa

REF

V

GND GND

VDD

GND

VDD VDD

GND GND

GND GND VCMOS

VDD

GND

SIO0 SIO1 GND

VDD

A B C D E F G H J K L M N P R S T U

Note Some signals can be applied because this pin is not connected to the inside of the chip.

GND

VDD

Data Sheet E0039N30 (Ver. 3.0)

3

Pin Description

Signal Input / Output Type #pins Description

Note1

Note2

2 Serial input/output. Pi ns for reading from and writing to the c ont rol regi sters using

a serial access protocol. Also used for power management .

Note1

1 Command input. Pins used in conjunction with SIO0 and SIO1 for reading from

and writing to the control regis ters. Also used for power management.

Note1

1 Serial clock input. Cl ock source used for reading from and writing to the control

registers.

9 Data byte A. Nine pins whic h carry a byte of read or write data between the

Channel and the RDRAM.

1 Clock from master. Interface clock used for receiving RSL signals from the

Channel. Positive polarity.

1 Clock from master. Interface clock used for receiving RSL signals from the

Channel. Negative polarity.

1 Clock to master. I nt e rf ace clock used for trans m i tting RSL signals to the Channel .

Negative polarity.

1 Clock to master. I nt e rf ace clock used for trans m i tting RSL signals to the Channel .

Positive polarity.

3 Row access control. Three pi ns containing control and address i nformation for

row accesses.

5 Column access control. Five pins containing cont rol and address information for

column accesses.

9 Data byte B. Nine pins whic h carry a byte of read or write data between the

Channel and the RDRAM.

SIO0, SIO1 Input / Output

CMD Input

SCK Input

CMOS

VDD 18 Supply voltage f or the RDRAM core and interface logic . V

1 Supply voltage for the RDRAM anal og circuitry.

DDa

V

2 Supply voltage for CMOS input /output pins.

CMOS

GND 22 Ground reference for RDRAM core and i nterface. GNDa 2 Ground reference for RDRAM analog circui try. DQA8..DQA0 Input / Output

CFM Input

CFMN Input

V

1 Logic threshold reference voltage f or RS L signals.

REF

CTMN Input

CTM Input

ROW2..ROW0 Input

COL4..COL0 Input

DQB8..DQB0 Input / Output

RSL

Total pin count per package 80

µµµµ

PD488588

Notes 1. All CMOS signals are high-true ; a high voltage is a logic one and a low voltage is logic zero.

2. All RSL signals are low-true ; a low voltage is a logic one and a high voltage is logic zero.

4

Data Sheet E0039N30 (Ver. 3.0)

Block Diagram

RQ7..RQ5 or

ROW2..ROW0

9 9

3

CTMDQB8..DQB0 DQA8..DQA0CTMN

RCLK

SCK, CMD2SIO0, SIO1

2

CFM CFMN

1:8 Demux

RQ4..RQ0 or

COL4..COL0

5

1:8 Demux

µµµµ

PD488588

RCLK

Packet Decode

ROWR ROWA

11 5 5 9

ROPAVDR BR R CMBMACOPSDC BCXOPMDX BX

Internal DQB Data Path

9

RCLK

9

1:8 Demux

DM

Row Decode

9

Write Buffer

Mux

Sense Amp

64x72

72

PRER

ACT

DRAM Core

64x72

0

SAmp

0/1

SAmp

1/2

SAmp

•

13/14

SAmp

14/15

SAmp

15

SAmp

TCLK

512x128x144

Control Registers

Power Modes

Bank 0

Bank 1

Bank 2

•

Bank 13

Bank 14

Bank 15

RCLK

Packet Decode

6

5

DEVIDREFR

XOP Decode

PREX

64x72

0

0/1

1/2

13/14

SAmp

•

SAmp

5

72

5

MatchMatch Match

72

5

Buffer

Mux Mux Column Decode & Mask

PREC RD, WR

Internal DQA Data Path

9

Write Buffer

SAmp

14/15

SAmp

15

Write

7

9

COLMCOLCCOLX

8

RCLK

1:8 Demux

9

SAmp

16

SAmp

16/17

SAmp

TCLK

17/18

SAmp

•

9

•

8:1 Mux

29/30

SAmp

30/31

SAmp

31

SAmp

Bank 16

Bank 17

Bank 18

•

Bank 29

Bank 30

Bank 31

16

16/17

17/18

•

29/30

30/31

31

SAmp

99

TCLK

8:1 Mux

9

Data Sheet E0039N30 (Ver. 3.0)

5

µµµµ

PD488588

CONTENTS

1. General Description.................................................................................................................................................8

2. Packet Format........................................................................................................................................................10

3. Field Encoding Summary......................................................................................................................................12

4. DQ Packet Timing..................................................................................................................................................14

5. COLM Packet to D Packet Mapping...................................................................................................................... 14

6. ROW-to-ROW Packet Interaction..........................................................................................................................16

7. ROW-to-COL Packet Interaction...........................................................................................................................18

8. COL-to-COL Packet Interaction............................................................................................................................19

9. COL-to-ROW Packet Interaction...........................................................................................................................20

10. ROW-to-ROW Examples......................................................................................................................................21

11. Row and Column Cycle Description ..................................................................................................................22

12. Precharge Mechanisms.......................................................................................................................................23

13. Read Transaction - Example...............................................................................................................................25

14. Write Transaction - Example...............................................................................................................................26

15. Write/Retire - Examples.......................................................................................................................................27

16. Interleaved Write - Example................................................................................................................................29

17. Interleaved Read - Example................................................................................................................................30

18. Interleaved RRWW - Example.............................................................................................................................31

19. Control Register Transactions............................................................................................................................32

20. Control Register Packets ....................................................................................................................................33

21. Initialization..........................................................................................................................................................34

22. Control Register Summary..................................................................................................................................38

23. Power State Management....................................................................................................................................47

24. Refresh..................................................................................................................................................................52

25. Current and Temperature Control......................................................................................................................54

26. Electrical Conditions ...........................................................................................................................................55

27. Timing Conditions ...............................................................................................................................................56

28. Electrical Characteristics....................................................................................................................................58

29. Timing Characteristics ........................................................................................................................................58

30. RSL Clocking........................................................................................................................................................59

31. RSL - Receive Timing ..........................................................................................................................................60

32. RSL - Transmit Timing.........................................................................................................................................61

33. CMOS - Receive Timing.......................................................................................................................................62

34. CMOS - Transmit Timing.....................................................................................................................................64

35. RSL - Domain Crossing Window........................................................................................................................65

36. Timing Parameters...............................................................................................................................................66

37. Absolute Maximum Ratings................................................................................................................................67

6

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

38. IDD - Supply Current Profile .................................................................................................................................67

39. Capacitance and Inductance ..............................................................................................................................68

40. Interleaved Device Mode.....................................................................................................................................70

41. Glossary of Terms ...............................................................................................................................................74

42. Package Drawing.................................................................................................................................................76

43. Recommended Soldering Conditions................................................................................................................77

Data Sheet E0039N30 (Ver. 3.0)

7

µµµµ

PD488588

1. General Description

The figure on page 5 is a block diagram of the banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core at up to 1.6 GB/s.

Control Registers: The CMD, SCK, SIO0, and SIO1 pins appear in the upper center of the block diagram. They are used to write and read a block of control registers. These registers supply the RDRAM configuration information to a controller and they select the operating modes of the device. The nine bit REFR value is used for tracking the last refreshed row. Most importantly, the five bits DEVID specifies the device address of the RDRAM on the Channel.

Clocking: The CTM and CTMN pins (Clock-To-Master) generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-From-Master) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins.

DQA, DQB Pins: These 18 pins carry read (Q) and write (D) data across the Channel. They are multiplexed / de- multiplexed from / to two 72-bit data paths (running at one-eighth the data frequency) inside the RDRAM.

Banks: The 32 Mbyte core of the RDRAM is divided into 32 one-Mbyte banks, each organized as 512 rows, with each row containing 128 dualocts (2K bytes), and each dualoct containing 16 bytes. A dualoct is the smallest unit of data that can be addressed.

Sense Amps: The RDRAM contains 34 sense amps. Each sense amp consists of 1,024 bytes of fast storage (512 for DQA and 512 for DQB) and can hold one-half of one row of one bank of the RDRAM. The sense amp may hold any of the 512 half-rows of an associated bank. However, each sense amp is shared between two adjacent banks of the RDRAM (except for numbers 0, 15, 30, and 31). This introduces the restriction that adjacent banks may not be simultaneously accessed.

RQ Pins: These pins carry control and address information. They are broken into two groups. RQ7..RQ5 are also called ROW2..ROW0, and are used primarily for controlling row accesses. RQ4..RQ0 are also called COL4..COL0, and are used primarily for controlling column accesses.

ROW Pins: The principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the RDRAM. These pins are de-multiplexed into a 24-bit ROWA (row-activate) or ROWR (row-operation) packet.

COL Pins: The principle use of these five pins is to manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM. These pins are de-multiplexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet.

ACT Command: An ACT (activate) command from an ROWA packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 512 byte sense amps for DQA and two for DQB).

PRER Command: A PRER (precharge) command from an ROWR packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated.

PD488588. It consists of two major blocks : a “core” block built from

µ

8

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

RD Command: The RD (read) command causes one of the 128 dualocts of one of the sense amps to be transmitted

on the DQA/DQB pins of the Channel.

WR Command: The WR (write) command causes a dualoct received from the DQA/DQB data pins of the Channel to be loaded into the write buffer. There is also space in the write buffer for the BC bank address and C column address information. The data in the write buffer is automatically retired (written with optional bytemask) to one of the 128 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD, WR, or NOCOP to another device, or during a WR or NOCOP to the same device. The write buffer will not retire during a RD to the same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turnaround.

PREC Precharge: The PREC, RDA and WRA commands are similar to NOCOP, RD and WR, except that a precharge operation is performed at the end of the column operation. These commands provide a second mechanism for performing precharge.

PREX Precharge: After a RD command, or after a WR command with no byte masking (M=0), a COLX packet may be used to specify an extended operation (XOP). The most important XOP command is PREX. This command provides a third mechanism for performing precharge.

Data Sheet E0039N30 (Ver. 3.0)

9

µµµµ

PD488588

2. Packet Format

Figure 2-1 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 2-1 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM. The AV (ROWA/ROWR packet selection) bit distinguishes between the two packet types. Both the ROWA and ROWR packet provide a five bit device address and a four bit bank address. An ROWA packet uses the remaining bits to specify a nine bit row address, and the ROWR packet uses the remaining bits for an eleven bit opcode field. Note the use of the “RsvX” notation to reserve bits for future address field extension. Figure 2-1 also shows the formats of the COLC, COLM, and COLX packets on the COL pins. Table 2-2 describes the fields which comprise these packets. The COLC packet uses the S (Start) bit for framing. A COLM or COLX packet is aligned with this COLC packet, and is also framed by the S bit. The 23 bit COLC packet has a five bit device address, a four bit bank address, a six bit column address, and a four bit opcode. The COLC packet specifies a read or write command, as well as some power management commands. The remaining 17 bits are interpreted as a COLM (M=1) or COLX (M=0) packet. A COLM packet is used for a COLC write command which needs bytemask control. The COLM packet is associated with the COLC packet from a time t device address, a four bit bank address, and a five bit opcode. The COLX packet may also be used to specify some housekeeping and power management commands. The COLX packet is framed within a COLC packet but is not otherwise associated with any other packet.

earlier. An COLX packet may be used to specify an independent precharge command. It contains a five bit

RTR

Table 2-1 Field Description for ROWA Packet and ROWR Packet

Field Description

DR4T, DR4F Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bi t. DR3..DR0 Device address for ROWA or ROWR pac ket. BR4..BR0 Bank address for ROWA or ROWR pack et. RsvB denotes bits i gnored by the RDRAM. AV Selects between ROWA packet (AV=1) and ROWR packet (AV=0). R8..R0 Row address for ROWA packet. RsvR denotes bits reserved for future row address ext ension. ROP10..ROP0 Opcode field for ROWR packet. Specifies precharge, refres h, and power m anagement functions.

Table 2-2 Field Description for COLC Packet, COLM Packet, and COLX Packet

Field Description

S Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets. DC4..DC0 Device address for COLC packet. BC4..BC0 Bank address for COLC packet . RsvB denotes bits reserved for future extension (controller drivers 0's). C6..C0 Column address for COLC packet. COP3..COP0 Opcode field for COLC packet. S pecifies read, write, precharge, and power management functions. M Selects between COLM pack et (M=1) and COLX packet (M=0). MA7..MA0 Bytemask write c ontrol bits. 1=write, 0=no-write. MA0 controls the earlies t byte on DQA8..0. MB7..MB0 Bytemask write c ontrol bits. 1=write, 0=no-write. MB0 controls the earlies t byte on DQB8..0. DX4..DX0 Device address for COLX pac ket. BX4..BX0 Bank address for COLX pack et. RsvB denotes bits reserved for future extension (controller drivers 0's). XOP4..XOP0 Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions.

10

Data Sheet E0039N30 (Ver. 3.0)

Figure 2-1 Packet Formats

µµµµ

PD488588

CTM/CFM

ROW2

ROW1

ROW0

CTM/CFM

COL4

COL3

COL2

COL1

T

0

DR2 BR0 BR3 RsvR R8 R5

DR4T

DR1 BR1 BR4 RsvR R7 R4 R1

DR4F

DR0 BR2 RsvB AV=1 R6 R3 R0

DR3

T

1

T

2

ROWA Packet

T

0

S=1

DC4

DC3

COP1 RsvB BC2 C2

DC2

COP0 BC4 BC1 C1

DC1

T

1

T

2

T

3

R2

T

3

C4

C6

C5 C3

CTM/CFM

ROW2

ROW1

ROW0

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0 DQB8..0

T

8

DR2 BR0 BR3 ROP10ROP8ROP5

DR4T

DR1 BR1 BR4 ROP9ROP7ROP4ROP1

DR4F

DR0 BR2 RsvB AV=0 ROP6ROP3ROP0

DR3

T

9

T

10

ROWR Packet

T

0

T

1

ACT a0

WR b1

T

4

2

3

T

5

6

t

PACKET

T

7

T

8

PRER c0

T

11

ROP2

T

9

10

T

11

T

12

13

14

15

PREX d0MSK (b1)

COL0

CTM/CFM

COL4

COL3

COL2

COL1

COL0

COP2 COP3 BC3 BC0 C0

DC0

COLC Packet

T

8

T

9

T

10

T

11

T

12

T

13

CTM/CFM

Note1

MA7 MA5 MA3 MA1

S=1

M=1 MA6 MA4 MA2 MA0

MB7 MB4 MB1

MB6 MB3 MB0

MB5 MB2

COL4

COL3

COL2

COL1

COL0

COLM Packet

Notes 1. The COLM is associated with a previous COLC, and is aligned with the present COLC, indicated by the Start bit (S=1) position.

2. The COLX is aligned with the present COLC, indicates by the Start bit (S=1) position.

Note2

DX4 XOP4 RsvB BX1

S=1

M=0 DX3 XOP3 BX4 BX0

DX2 XOP2 BX3

DX1 XOP1 BX2

DX0 XOP0

COLX Packet

T

14

T

15

Data Sheet E0039N30 (Ver. 3.0)

11

µµµµ

PD488588

3. Field Encoding Summary

Table 3-1 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a broadcast operation is indicated when both bits are set. Broadcast operation would typically be used for refresh and power management commands. If the device is selected, the DM (DeviceMatch) signal is asserted and an ACT or ROP command is performed.

Table 3-1 Device Field Encodings for ROWA Packet and ROWR Packet

DR4T DR4F Device Selection Device Match signal (DM)

1 1 All devices (broadcas t ) DM is set to 1 0 1 One device selected DM is set to 1 if {DEVID4..DEVID0} == {0, DR3..DR0} else DM is set to 0 1 0 One device selected DM is set to 1 if {DEVID4..DEVID0} == {1, DR3..DR0} else DM is set to 0 0 0 No packet present DM is set t o 0

Table 3-2 shows the encodings of the remaining fields of the ROWA and ROWR packets. An ROWA packet is specified by asserting the AV bit. This causes the specified row of the specified bank of this device to be loaded into the associated sense amps. An ROWR packet is specified when AV is not asserted. An 11 bit opcode field encodes a command for one of the banks of this device. The PRER command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. The REFA (refresh-activate) command is similar to the ACT command, except the row address comes from an internal register REFR, and REFR is incremented at the largest bank address. The REFP (refresh-precharge) command is identical to a PRER command. The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing the power dissipation of the RDRAM and are described in more detail in “23. Power State Management”. The TCEN and TCAL commands are used to adjust the output driver slew rate and they are described in more detail in “25. Current and Temperature

Control”.

Table 3-2 ROWA Packet and ROWR Packet Field Encodings

DM AV ROP10..ROP0 Field Name Command Description

Note1

10 9 8 7 6 5 4 3 2 : 0 — — — — — — — — — --- — No operation. 1 1 Row address ACT Acti vate row R8..R0 of bank BR4..B R0 of device and move device to

1 0 1 1 0 0 0 x 1 0 0 0 0 1 1 0 0 x 000 REFA Refresh (activate) row REFR8..REFR0 of bank BR3..BR0 of device.

1 0 1 0 1 0 1 0 0 x 000 REFP Precharge bank BR4..BR0 of this device after RE FA (see Figure 24-1). 1 0 x x 0 0 0 0 1 x 000 PDNR Move this device into t he powerdown (P DN) power state (see figure 23-3). 1 0 x x 0 0 0 1 0 x 000 NAPR Move this device into the nap (NAP ) power state (see Figure 23-3). 1 0 x x 0 0 0 1 1 x 000 NAPRC Move this device into the nap (NAP) power state conditionally. 1 0 x x x x x x x 0 000 1 0 x x x x x x x 1 000 RLXR Move this device into the standby (STBY) power state (see Figure 23-2). 1 0 0 0 0 0 0 0 0 x 001 TCAL Temperature calibrate this dev i ce (see figure 25-2). 1 0 0 0 0 0 0 0 0 x 010 TCEN Temperature calibrate/enable this device (see Figure 25-2). 1 0 0 0 0 0 0 0 0 0 000 NOROP No operation.

Notes 1. The DM (Device Match s i gnal ) value is determined by the DR4T, DR4F, DR3..DR0 field of the ROWA and ROWR packet s. See Table 3-1.

2. The ATTN command does not cause a RLX-to-A TTN transition for a broadcast operati on (DR4T/ DR4F=1/1).

3. An “x” entry indicates which com m ands may be combined. For instance, the three commands PRER/ NA PRC/RLXR may be specified in one ROP value (011000111000).

Note3

x x 000 PRER Precharge bank BR4..BR0 of t hi s device.

0

Note2

ATTN

Note2

ATTN

Increment REFR if BR4.. B R0=11111 (see Figure 24-1).

Move this device int o the attention (ATTN) power state (see Fi gure 23-1).

.

12

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

Table 3-3 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 15-1 for a more detailed description. The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps. The RDA/WRA commands are equivalent to a combining RD/WR with a PREC. RLXC (relax) performs a power mode transition. See 23. Power State Management.

Table 3-3 COLC Packet Field Encodings

S DC4..DC0

(select device)

0 - - - - - - - - - — No operation. 1 /= (DEVID4. .0) - - - - - — Retire write buffer of this device. 1 == (DEVID4..0) 1 == (DEVID4..0) x001 WR Retire write buffer of this device, then wri te column C6..C0 of bank

1 == (DEVID4..0) x010 RSRV Reserved, no operation. 1 == (DEVID4..0) x011 RD Read column C6.. C0 of bank BC4..BC0 of this dev i ce. 1 == (DEVID4..0) x100 PREC Retire write buffer of this device, then precharge bank BC4..BC0 (see

1 == (DEVID4..0) x101 WRA Same as WR, but precharge bank B C4..BC0 after write buffer (wit h new

1 == (DEVID4..0) x110 RSRV Reserved, no operation. 1 == (DEVID4.. 0) x111 RDA Same as RD, but precharge bank BC4..BC0 afterward. 1 == (DEVID4..0) 1xxx RLXC Move this device into the standby (STBY) power state (see Figure 23-2).

COP3..0 Name Command Description

Note1

Note2

x000

NOCOP Retire wri te buffer of this devic e.

BC4..BC0 to write buffer.

Figure 12-2).

data) is retired.

Notes 1. “/=” means not equal, “==” means equal.

2. An “x” entry indicates which commands may be combined. For instance, the two commands WR/RLXC

may be specified in one COP value(1001).

Table 3-4 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8 bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge) command to be specified without consuming control bandwidth on the ROW pins. It is also used for the CAL (calibrate) and SAM (sample) current control commands (see 25. Current and Temperature Control), and for the RLXX power mode command (see 23. Power State Management).

Table 3-4 COLM Packet and COLX Packet Field Encodings

M DX4..DX0

(select device)

1 - - - - - MSK MB/MA bytemasks used by WR/WRA. 0 /= (DEVID4..0) - — No operation. 0 == (DEVID4..0) 00000 NOXOP No operation. 0 == (DEVID4..0) 0 == (DEVID4.. 0) x10x0 CAL Calibrate (drive) IOL current for this devic e (see Figure 25-1). 0 == (DEVID4..0) x11x0 CAL / SAM Cal i brate (drive) and Sample (update) IOL current for this devic e (see Figure 25-1). 0 == (DEVID4..0) xxx10 RLXX Move this device into t he standby (STBY) power state (s ee Fi gure 23-2). 0 == (DEVID4..0) xxxx1 RSRV Reserved, no operation.

XOP4..0 Name Command Description

Note

1xxx0

PREX Precharge bank BX4.. B X0 of this device (see Figure 12-2).

Note An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).

Data Sheet E0039N30 (Ver. 3.0)

13

µµµµ

PD488588

4. DQ Packet Timing

Figure 4-1 shows the timing relationship of COLC packets with D and Q data packets. This document uses a specific convention for measuring time intervals between packets: all packets on the ROW and COL pins (ROWA, ROWR, COLC, COLM, COLX) use the trailing edge of the packet as a reference point, and all packets on the DQA/DQB pins (D and Q) use the leading edge of the packet as a reference point. An RD or RDA command will transmit a dualoct of read data Q a time t cycles of round-trip propagation delay on the Channel. The t of values (7, 8, 9, 10, 11, or 12 t

). The value chosen depends upon the number of RDRAM devices on the

CYCLE

parameter may be programmed to a one of a range

CAC

Channel and the RDRAM timing bin. See Figure 22-1(5/7) “TPARM Register” for more information. A WR or WRA command will receive a dualoct of write data D a time t the round-trip propagation time of the Channel since the COLC and D packets are traveling in the same direction. When a Q packet follows a D packet (shown in the left half of the figure), a gap (t between them because the t

value is always less than the t

CWD

value. There will be no gap between the two COLC

CAC

packets with the WR and RD commands which schedule the D and Q packets. When a D packet follows a Q packet (shown in the right half of the figure), no gap is needed between them because the t

value is less than the t

CWD

value. However, a gap of t

CAC

- t

CWD

COLC packets with the RD WR commands by the controller so the Q and D packets do not overlap.

Figure 4-1 Read (Q) and Write (D) Data Packet - Timing for t

later. This time includes one to five

CAC

later. This time does not need to include

CWD

CAC-tCWD

) will automatically appear

or greater must be inserted between the

CAC

= 7,8,9,10,11 or 12 tCYCLE

T

1

2

3

0

4

T

5

6

7

T

8

T

9

T

10

11

T

12

16

T

13

14

15

T

17

18

19

20

T

21

22

23

T

24

T

25

T

26

27

T

28

32

T

29

30

31

T

33

34

35

36

T

37

38

39

T

41

40

T

42

43

T

45

46

47

44

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0

This gap on the DQA/DQB pins appears automatically

t

CAC-tCWD

t

CWD

RD b1WR a1

D (a1)

•••

Q (b1)

This gap on the COL pins must be inserted by the controller

t

CAC-tCWD

•••

RD c1

WR d1

t

CWD

Q (c1)

D (d1)

DQB8..0

t

CAC

•••

t

CAC

5. COLM Packet to D Packet Mapping

Figure 5-1 shows a write operation initiated by a WR command in a COLC packet. If a subset of the 16 bytes of write data are to be written, then a COLM packet is transmitted on the COL pins a time t containing the WR command. The M bit of the COLM packet is set to indicate that it contains the MA and MB mask fields. Note that this COLM packet is aligned with the COLC packet which causes the write buffer to be retired. See Figure 15-1 for more details. If all 16 bytes of the D data packet are to be written, then no further control information is required. The packet slot that would have been used by the COLM packet (t

after the COLC packet) is available to be used as an COLX

RTR

packet. This could be used for a PREX precharge command or for a housekeeping command (this case is not shown). The M bit is not asserted in an COLX packet and causes all 16 bytes of the previous WR to be written unconditionally. Note that a RD command will never need a COLM packet, and will always be able to use the COLX packet option (a read operation has no need for the byte-write-enable control bits). The figure 5-1 also shows the mapping between the MA and MB fields of the COLM packet and bytes of the D packet on the DQA and DQB pins. Each mask bit controls whether a byte of data is written (=1) or not written (=0).

after the COLC packet

RTR

14

Data Sheet E0039N30 (Ver. 3.0)

Figure 5-1 Mapping between COLM Packet and D Packet for WR Command

µµµµ

PD488588

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0 DQB8..0

CTM/CFM

COL4

COL3

COL2

T

0

T

1

2

3

T

5

6

7

4

T

9

8

T

10

T

11

T

12

16

T

13

14

15

T

17

18

19

20

T

21

22

23

T

25

24

T

26

T

29

30

27

31

28

PRER a2

t

RTR

retire (a1)WR a1 MSK (a1)

t

CWD

D (a1)

Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a3 = {Da,Ba}

COLM Packet

T

17

T

18

T

19

T

20

T

19

CTM/CFM

MA7 MA5 MA3 MA1

M=1 MA6 MA4 MA2 MA0

MB7 MB4 MB1

DQB8

DQB7

•

DB17 DB26 DB35 DB45 DB53 DB62

DB8

DB16 DB25 DB34 DB44 DB52 DB61 DB70

DB7

T

32

ACT b0ACT a0

T

33

34

D Packet

T

20

T

35

36

T

37

38

39

40

T

21

T

41

42

T

43

T

45

46

47

44

T

22

DB71

COL1

COL0

When M=1, the MA and MB fields control writing of individual data bytes. When M=0, all data bytes are written unconditionally.

MB6 MB3 MB0

MB5 MB2

Each bit of the MB7..MB0 field controls writing (=1) or no writing (=0) of the indicated DB bits when the M bit of the COLM packet is one.

Each bit of the MA7..MA0 field controls writing (=1) or no writing (=0) of the indicated DA bits when the M bit of the COLM packet is one.

DQB1

DQB0

DQA8

DQA7

•

DQA1

DQA0

DB10 DB19 DB28 DB37 DB46 DB55 DB64

DB1

DB9 DB18 DB27 DB36 DB45 DB54 DB63

DB0

MB0

MB1

MB2

MB3

MB4

MB5

DA17 DA26 DA35 DA45 DA53 DA62

DA8

DA16 DA25 DA34 DA44 DA52 DA61 DA70

DA7

DA10 DA19 DA28 DA37 DA46 DA55 DA64

DA1

DA9 DA18 DA27 DA36 DA45 DA54 DA63

DA0

MA0

MA1

MA2

MA3

MA4

MA5

MB6

MA6

MB7

DA71

MA7

Data Sheet E0039N30 (Ver. 3.0)

15

µµµµ

PD488588

6. ROW-to-ROW Packet Interaction

Figure 6-1 shows two packets on the ROW pins separated by an interval t contents. No other ROW packets are sent to banks {Ba, Ba+1, Ba-1} between packet “a” and packet “b” unless noted otherwise.

Figure 6-1 ROW-to-ROW Packet Interaction - Timing

which depends upon the packet

RRDELAY

T

0

T

1

2

3

4

T

5

6

7

8

T

9

T

10

T

11

T

12

16

T

13

14

15

T17T18T

T

19

CTM/CFM

t

ROW2

ROPa a0 ROPb b0

RRDELAY

..ROW0 COL4

..COL0

DQA8..0

DQB8..0

Transaction a: ROPa Transaction b: ROPb

Table 6-1 summarizes the t

RRDELAY

values for all possible cases. Cases RR1 through RR4 show two successive ACT commands. In case RR1, there is no restriction since the ACT commands are to different devices. In case RR2, the t

RR

banks. Cases RR3 and RR4 are illegal (as shown) since bank Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1 is inserted, t

RRDELAY

is tRC (t

to the PRER command, and tRP to the next ACT).

RAS

Cases RR5 through RR8 show an ACT command followed by a PRER command. In cases RR5 and RR6, there are no restrictions since the commands are to different devices or to non-adjacent banks of the same device. In cases RR7 and RR8, the t

restriction means the activated bank must wait before it can be precharged.

RAS

Cases RR9 through RR12 show a PRER command followed by an ACT command. In cases RR9 and RR10, there are essentially no restrictions since the commands are to different devices or to non-adjacent banks of the same device. RR10a and RR10b depend upon whether a bracketed bank (Ba+-1) is precharged or activated. In cases RR11 and RR12, the same and adjacent banks must all wait t being activated. Cases RR13 through RR16 summarize the combinations of two successive PRER commands. In case RR13 there is no restriction since two devices are addressed. In RR14, t RR15 and RR16, the same bank or an adjacent bank may be given repeated PRER commands with only the t restriction. Two adjacent banks can’t be activate simultaneously. A precharge command to one bank will thus affect the state of the adjacent banks (and sense amps). If bank Ba is activate and a PRER is directed to Ba, then bank Ba will be precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If bank Ba+1 is activate and a PRER is directed to Ba, then bank Ba+1 will be precharged along with sense amps Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a PRER is directed to Ba, then bank Ba-1 will be precharged along with sense amps Ba/Ba-1 and Ba-1/Ba-2. A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, NAPRC, PDNR, RLXR, ATTN, TCAL, and TCEN commands are discussed in later section (see Table 3-2 for cross-ref).

a0 = {Da,Ba,Ra}

b0= {Db,Bb,Rb}

restriction applies to the same device with non-adjacent

for the sense amp and bank to precharge before

RP

applies, since the same device is addressed. In

PP

16

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

Table 6-1 ROW-to-ROW Packet Interaction - Rules

Case # ROPa Da Ba Ra ROPb Db Bb Rb t RR1 ACT Da Ba Ra ACT /= Da xxxx x..x t

Example

RRDELAY

Figure 10-2

PACKET

RR2 ACT Da Ba Ra ACT == Da /= {Ba, Ba+1, Ba-1} x..x tRR Figure 10-2 RR3 ACT Da Ba Ra ACT == Da == {Ba+1, Ba-1} x..x t RR4 ACT Da Ba Ra ACT == Da == {Ba} x..x t RR5 ACT Da Ba Ra PRER /= Da xxxx x..x t RR6 ACT Da Ba Ra PRER == Da /= {B a, Ba+1, Ba-1} x..x t RR7 ACT Da Ba Ra PRER == Da == {Ba+1, Ba-1} x..x t RR8 ACT Da Ba Ra PRER == Da == {Ba} x..x t RR9 PRER Da Ba Ra ACT /= Da xxxx x..x t RR10 PRER Da Ba Ra ACT == Da /= {Ba, Ba+-1, Ba+-2} x..x t RR10a PRER Da Ba Ra ACT == Da == {Ba+2} x..x t RR10b PRER Da Ba Ra ACT == Da == {Ba-2} x..x t

- illegal unless PRER to Ba / Ba+1 / Ba-1 Figure 10-1

RC

- illegal unless PRER to Ba / Ba+1 / Ba-1 Figure 10-1

RC

Figure 10-2

PACKET

Figure 10-2

PACKET

Figure 10-1

RAS

Figure 13-1

RAS

Figure 10-3

PACKET

Figure 10-3

PACKET

PACKET/tRP

if Ba+1 is precharged/acti vated.

if Ba-1 is precharged/activated. RR11 PRER Da B a Ra ACT == Da == {Ba+1, Ba-1} x..x tRP Figure 10-1 RR12 PRER Da Ba Ra ACT == Da == {Ba} x..x tRP Figure 10-1 RR13 PRER Da Ba Ra PRER /= Da xxxx x..x t

Figure 10-3

PACKET

RR14 PRER Da Ba Ra PRER == Da /= {Ba, Ba+1, Ba-1} x..x tPP Figure 10-3 RR15 PRER Da Ba Ra PRER == Da == {Ba+1, Ba-1} x..x tPP Figure 10-3 RR16 PRER Da Ba Ra PRER == Da == {Ba} x..x tPP Figure 10-3

Data Sheet E0039N30 (Ver. 3.0)

17

7. ROW-to-COL Packet Interaction

Figure 7-1 shows two packets on the ROW and COL pins. They must be separated by an interval t depends upon the packet contents.

Figure 7-1 ROW-to-COL Packet Interaction- Timing

µµµµ

PD488588

RCDELAY

which

T

0

T

1

2

3

4

T

5

6

7

8

T

9

T

10

T

11

T

12

16

T

13

14

15

T17T18T

T

19

CTM/CFM

t

ROW2

ROPa a0

RCDELAY

..ROW0 COL4

COPb b1

..COL0

DQA8..0 DQB8..0

Transaction a: ROPa

Transaction b: COPb

Table 7-1 summarizes the t

RCDELAY

values for all possible cases. Note that if the COL packet is earlier than the ROW packet, it is considered a COL-to-ROW packet interaction. Cases RC1 through RC5 summarize the rules when the ROW packet has an ACT command. Figure 13-1 and Figure 14-1 show examples of RC5 - an activation followed by a read or write. RC4 is an illegal situation, since a read or write of a precharged banks is being attempted (remember that for a bank to be activated, adjacent banks must be precharged). In cases RC1, RC2, and RC3, there is no interaction of the ROW and COL packets. Cases RC6 through RC8 summarize the rules when the ROW packet has a PRER command. There is either no interaction (RC6 through RC9) or an illegal situation with a read or write of a precharged bank (RC9). The COL pins can also schedule a precharge operation with a RDA, WRA, or PREC command in a COLC packet or a PREX command in a COLX packet. The constraints of these precharge operations may be converted to equivalent PRER command constraints using the rules summarized in Figure 12-2.

Table 7-1 ROW-to-COL Packet Interaction - Rules

a0 = {Da,Ba,Ra}

b1= {Db,Bb,Cb1}

Case # ROPa Da B a Ra COPb Db Bb Cb1 t

RCDELAY

Example RC1 ACT Da Ba Ra NOCOP, RD, retire /= Da xxxx x..x 0 RC2 ACT Da Ba Ra NOCOP == Da xxxx x..x 0 RC3 ACT Da Ba Ra RD, ret i re == Da /= {Ba, Ba+1, Ba-1} x..x 0 RC4 AC T Da Ba Ra RD, retire == Da == {Ba+1, B a-1} x..x Illegal RC5 ACT Da Ba Ra RD, retire == Da == {Ba} x..x t

Figure 13-1

RCD

RC6 PRER Da Ba Ra NOCOP, RD, retire /= Da xxxx x..x 0 RC7 PRER Da Ba Ra NOCOP == Da xxxx x..x 0 RC8 PRER Da Ba Ra RD, retire == Da /= {Ba, Ba+1, Ba-1} x..x 0 RC9 PR ER Da Ba Ra RD, retire == D a == {Ba+1, Ba- 1} x..x Illegal

18

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

8. COL-to-COL Packet Interaction

Figure 8-1 shows three arbitrary packets on the COL pins. Packets “b” and “c” must be separated by an interval t

CCDELAY

which depends upon the command and address values in all three packets. Table 8-1 summarizes the t

CCDELAY

values for all possible cases. Cases CC1 through CC5 summarize the rules for every situation other than the case when COPb is a WR command and COPc is a RD command. In CC3, when a RD command is followed by a WR command, a gap of t

CAC - tCWD

must be inserted between the two COL packets. See Figure 4-1 for more explanation of why this gap is needed. For cases CC1, CC2, CC4, and CC5, there is no restriction (t

CCDELAY

is tCC). In cases CC6 through CC10, COPb is a WR command and COPc is a RD command. The t between these two packets depends upon the command and address in the packet with COPa. In particular, in case CC6 when there is WR-WR-RD command sequence directed to the same device, a gap will be needed between the packets with COPb and COPc. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place. Figure 15-2 (right) provides a more detailed explanation of this case. In case CC10, there is a RD-WR-RD sequence directed to the same device. If a prior write to the same device is unretired when COPa is issued, then a gap will be needed between the packets with COPb and COPc as in case CC6. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place. Cases CC7, CC8, and CC9 have no restriction (t

CCDELAY

For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation PREC to take place. This precharge may be converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure 12-2.

Table 8-1 COL-to-COL Packet Interaction - Rules

Figure 8-1 COL-to-COL Packet Interaction- Timing

T

0

T

1

2

3

4

T

5

6

7

T

9

8

T

10

T

11

T

13

14

15

12

CTM/CFM

ROW2

..ROW0

t

CCDELAY

COL4

COPa a1

COPb b1

COPc c1

..COL0

DQA8..0

DQB8..0

is tCC).

Transaction a: COPa Transaction b: COPb Transaction c: COPc

a1 = {Da,Ba,Ca1} b1 = {Db,Bb,Cb1}

c1 = {Dc,Bc,Cc1}

CCDELAY

value needed

T

T17T18T

16

T

19

Case # COPa Da Ba Ca1 COPb Db Bb Cb1 COPc Dc Bc Cc1 t

Example

CCDELAY

CC1 xxxx xxxxx x..x x..x NOCOP Db Bb Cb1 xxxx xxxxx x..x x..x tCC CC2 xxxx xxxxx x..x x..x RD, WR Db Bb Cb1 NOCOP xxxxx x..x x..x tCC CC3 xxxx xxxxx x..x x..x RD Db Bb Cb1 WR xxxxx x..x x..x t

CC + tCAC - tCWD

Figure 4-1 CC4 xxxx xxxxx x..x x..x RD Db Bb Cb1 RD xxxxx x..x x..x tCC Figure 13-1 CC5 xxxx xxxxx x..x x..x WR Db Bb Cb1 WR xxxxx x..x x..x tCC Figure 14-1 CC6 WR == Db x x..x WR Db Bb Cb1 RD == Db x. . x x..x t

Figure 15-1

RTR

CC7 WR == Db x x..x WR Db Bb Cb1 RD /= Db x..x x..x tCC CC8 WR /= Db x x..x WR Db Bb Cb1 RD == Db x..x x..x tCC CC9 NOCOP == Db x x..x WR Db Bb Cb1 RD == Db x..x x..x tCC CC10 RD == Db x x..x WR Db Bb Cb1 RD == Db x..x x..x tCC

Data Sheet E0039N30 (Ver. 3.0)

19

µµµµ

PD488588

9. COL-to-ROW Packet Interaction

Figure 9-1 shows arbitrary packets on the COL and ROW pins. They must be separated by an interval t

CRDELAY

which depends upon the command and address values in the packets. Table 9-1 summarizes the t

CRDELAY

value for all possible cases. Cases CR1, CR2, CR3, and CR9 show no interaction between the COL and ROW packets, either because one of the commands is a NOP or because the packets are directed to different devices or to non-adjacent banks. Case CR4 is illegal because an already-activated bank is to be re-activated without being precharged. Case CR5 is illegal because an adjacent bank can’t be activated or precharged until bank Ba is precharged first. In case CR6, the COLC packet contains a RD command, and the ROW packet contains a PRER command for the same bank. The t

parameter specifies the required spacing.

RDP

Likewise, in case CR7, the COLC packet causes an automatic retire to take place, and the ROW packet contains a PRER command for the same bank. The t

parameter specifies the required spacing.

RTP

Case CR8 is labeled “Hazardous” because a WR command should always be followed by an automatic retire before a precharge is scheduled. Figure 15-3 shows an example of what can happen when the retire is not able to happen before the precharge. For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation to take place. This precharge may converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure 12-2.

A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent

to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, PDNR, and RLXR

commands are discussed in a later section.

Table 9-1 COL-to-ROW Packet Interaction - Rules

Figure 9-1 COL-to-ROW Packet Interaction- Timing

T

1

2

3

0

T

5

6

7

4

T

9

8

T

10

T

13

11

12

T17T18T

14

15

16

CTM/CFM

t

CRDELAY

ROW2

ROPb b0

..ROW0 COL4

COPa a1

..COL0

DQA8..0 DQB8..0

Transaction a: COPa Transaction b: ROPb

a1= {Da,Ba,Ca1} b0= {Db,Bb,Rb}

T

19

Case # COPa Da Ba Ca1 ROPb Db Bb Rb t

CRDELAY

Example CR1 NOCOP Da Ba Ca1 x..x xxxxx xxxxx x..x 0 CR2 RD/WR Da Ba Ca1 x..x /= Da xxxxx x..x 0 CR3 RD/WR Da Ba Ca1 x..x == Da /= {Ba, Ba +1, Ba-1} x..x 0 CR4 RD/WR Da Ba Ca1 ACT == Da == {B a} x..x Illegal CR5 RD/WR Da Ba Ca1 ACT == Da == {B a+1, Ba-1} x..x Illegal CR6 RD Da Ba Ca1 PRER == Da == {B a, Ba+1, Ba-1} x..x t

Note 1

CR7 CR8

retire WR

Da Ba Ca1 PRER == Da == {Ba, Ba+1, Ba-1} x..x t

Note 2

Da B a Ca1 PRER == Da == {Ba, Ba+1, Ba-1} x..x 0 Figure 15-3

Figure 13-1

RDP

Figure 14-1

RTP

CR9 xxxx Da Ba Ca1 NOROP xxxxx xxxxx x..x 0

Notes 1. This is any command which permits the write buffer of device Da to retire (see Table 3-3). “Ba” is the bank address in the write buffer.

2. This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure 15-3.

20

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

10. ROW-to-ROW Examples

Figure 10-1 shows examples of some of the ROW-to-ROW packet spacings from Table 6-1. A complete sequence of activate and precharge commands is directed to a bank. The RR8 and RR12 rules apply to this sequence. In addition to satisfying the t must also satisfy the t

RC

RAS

timing parameter (RR4).

and t

timing parameters, the separation between ACT commands to the same bank

RP

When a bank is activated, it is necessary for adjacent banks to remain precharged. As a result, the adjacent banks will also satisfy parallel timing constraints; in the example, the RR11 and RR3 rules are analogous to the RR12 and RR4 rules.

Figure 10-1 Row Packet Example

a0 = {Da,Ba,Ra}

Same Device Adjacent Bank RR7

Same Device Adjacent Bank RR11

T

0

T

1

2

3

4

T

5

6

7

T

8

T

9

T

10

T

11

15

12

T

13

14

T

17

18

19

16

20

T

21

22

23

T

24

T

25

T

26

27

T

28

32

T

29

30

31

T

33

T

34

T

37

35

36

a1 = {Da,Ba+1}

b0 = {Da,Ba+1,Rb}Same Device Adjacent Bank RR3

b0 = {Da,Ba,Rb}Same Device Same Bank RR4

b0 = {Da,Ba+1,Rb}

b0 = {Da,Ba,Rb}Same Device Same Bank RR12

T

41

38

42

39

40

T

45

46

43

47

44

CTM/CFM

ROW2

ACT a0 PRER a1

ACT b0

..ROW0 COL4

..COL0

t

RAS

t

RP

DQA8..0 DQB8..0

t

RC

Figure 10-2 shows examples of the ACT-to-ACT (RR1, RR2) and ACT-to-PRER (RR5, RR6) command spacings from Table 6-1. In general, the commands in ROW packets may be spaced an interval t

apart unless they are

PACKET

directed to the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device.

Figure 10-2 Row Packet Example

Different Device Any Bank

Same Device Non-adjacent Bank

Different Device Any Bank

Same Device Non-adjacent Bank

T

0

T

1

2

3

T

5

6

7

4

T

8

T

9

T

10

T

11

15

12

16

T

13

14

T

17

18

19

T

21

22

23

20

T

24

T

25

T

26

T

27

31

28

32

T

29

30

T

33

T

37

34

35

36

RR1 RR2 RR5 RR6

T

38

T

39

a0 = {Da,Ba,Ra}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

T

41

42

43

40

44

T

45

46

CTM/CFM

T

47

ROW2

..ROW0 COL4

..COL0

DQA8..0 DQB8..0

ACT a0 PRER b0

t

PACKET

t

RR

ACT c0

ACT a0ACT a0ACT b0 PRER c0

t

PACKET

Data Sheet E0039N30 (Ver. 3.0)

ACT a0

t

PACKET

21

µµµµ

PD488588

Figure 10-3 shows examples of the PRER-to-PRER (RR13, RR14) and PRER-to-ACT (RR9, RR10) command spacings from Table 6-1. The RR15 and RR16 cases (PRER-to-PRER to same or adjacent banks) are not shown, but are similar to RR14. In general, the commands in ROW packets may be spaced an interval t

PACKET

apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device.

Figure 10-3 Row Packet Example

Different Device Any Bank

Same Device Non-adjacent Bank

RR13 RR14

a0 = {Da,Ba,Ra} b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc} c0 = {Da,Ba,Rc}Same Device Ajacent Bank RR15

Different Device

Any Bank

Same Device Non-adjacent Bank

T

0

T

1

2

3

4

T

5

6

7

T

8

T

9

T

10

T

11

15

12

T

13

14

T

17

18

19

16

20

T

21

22

23

T

24

T

25

26

T

27

31

28

T

29

30

T

33

34

35

32

36

RR9

RR10

T

37

c0 = {Da,Ba+1Rc}Same Device Same Bank RR16

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

T

41

38

39

40

T

42

43

T

45

46

47

44

CTM/CFM

ROW2

..ROW0

PRER a0 ACT b0

t

PACKET

PRER c0

t

PP

PRER a0PRER a0PRER b0 ACT c0

t

PACKET

PRER a0

t

PACKET

COL4

..COL0

DQA8..0 DQB8..0

11. Row and Column Cycle Description

Activate: A row cycle begins with the activate (ACT) operation. The activation process is destructive; the act of

sensing the value of a bit in a bank’s storage cell transfers the bit to the sense amp, but leaves the original bit in the storage cell with an incorrect value.

Restore: Because the activation process is destructive, a hidden operation called restore is automatically performed. The restore operation rewrites the bits in the sense amp back into the storage cells of the activated row of the bank.

Read/Write: While the restore operation takes place, the sense amp may be read (RD) and written (WR) using column operations. If new data is written into the sense amp, it is automatically forwarded to the storage cells of the bank so the data in the activated row and the data in the sense amp remain identical.

Precharge: When both the restore operation and the column operations are completed, the sense amp and bank are precharged (PRE). This leaves them in the proper state to begin another activate operation.

to complete. The hidden restore operation requires the

Intervals: The activate operation requires the interval t interval t t

RCD,MIN

- t

RAS,MIN

interval (if more than about four column operations are performed, this interval must be increased). The

precharge operation requires the interval t

to complete. Column read and write operations are also performed during the t

RCD,MIN

RP,MIN

Adjacent Banks: An RDRAM with a “s” designation (512K

RCD,MIN

to complete.

-

RAS,MIN

x 18 x 32s) indicates it contains “split banks”. This means the sense amps are shared between two adjacent banks. The only exception is that sense amp 0, 15, 30, and 31 are not shared. When a row in a bank is activated, the two adjacent sense amps are connected to (associated with) that bank and are not available for use by the two adjacent banks. These two adjacent banks must remain precharged while the selected bank goes through its activate, restore, read/write, and precharge operations. For example (referring to the block diagram), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will both be loaded with one of the 512 rows (with 1,024 bytes loaded into each sense amp from the 2K byte row – 512 bytes to the DQA side and 512 bytes to the DQB side). While this row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of the sense amp sharing.

22

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

12. Precharge Mechanisms

Figure 12-1 shows an example of precharge with the ROWR packet mechanism. The PRER command must occur a time t

after the ACT command, and a time t

RAS

before the next ACT command. This timing will serve as a

RP

baseline against which the other precharge mechanisms can be compared.

Figure 12-1 Precharge via PRER Command in ROWR Packet

a0 = {Da,Ba,Ra}

a5 = {Da,Ba}

b0 = {Da,Ba,Rb}

T

0

T

1

2

3

4

T

5

6

7

T

8

T

9

T

10

11

T

13

14

15

12

T

17

18

19

16

20

T

21

22

23

T

24

T

25

T

26

27

T

28

32

T

29

30

31

T

33

34

35

T

37

38

39

36

T

40

T

41

T

42

T

45

46

43

47

44

CTM/CFM

ROW2

ACT a0 PRER a5

ACT b0

..ROW0 COL4

..COL0

t

RAS

t

RP

DQA8..0 DQB8..0

t

RC

Figure 12-2 (top) shows an example of precharge with a RDA command. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these commands is a RDA, which causes the bank to automatically precharge when the final read has finished. The timing of this automatic precharge is equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time t

from the COLC packet with the RDA command. The RDA command should be treated

OFFP

as a RD command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets. Figure 12-2 (middle) shows an example of precharge with a WRA command. As in the RDA example, a bank is activated with an ROWA packet on the ROW pins. Then, two dualocts are written with WR commands in COLC packets on the COL pins. The second of these commands is a WRA, which causes the bank to automatically precharge when the final write has been retired. The timing of this automatic precharge is equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time t

from the COLC packet that causes the

OFFP

automatic retire. The WRA command should be treated as a WR command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets. Note that the automatic retire is triggered by a COLC packet a time t

after the COLC packet with the WR command

RTR

unless the second COLC contains a RD command to the same device. This is described in more detail in Figure 15-

1. Figure 12-2 (bottom) shows an example of precharge with a PREX command in an COLX packet. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these COLC packets includes an COLX packet with a PREX command. This causes the bank to precharge with timing equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time t

from the COLX packet with the PREX command.

OFFP

Data Sheet E0039N30 (Ver. 3.0)

23

Figure 12-2 Offsets for Alternate Precharge Mechanisms

COLC Packet: RDA Precharge Offset

CTM/CFM

ROW2

..ROW0 COL4

..COL0

T

0

T

1

2

3

4

T

5

6

7

T

8

T

9

T

13

10

14

11

12

The RDA precharge is equivalent to a PRER command here

ACT a0

RD a1

RD a2

µµµµ

PD488588

T

15

T

17

18

19

16

20

RD a3

T

21

RDA a4

T

22

23

T

25

24

PRER a5

T

26

27

T

29

30

31

28

32

T

33

34

35

T

37

38

39

36

T

40

T

41

T

42

T

45

46

43

47

44

ACT b0

t

OFFP

DQA8..0

DQB8..0

Transaction a: RD a0 = {Da,Ba,Ra}

COLC Packet: WDA Precharge Offset

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0

DQB8..0

T

0

T

1

2

3

4

T

5

6

7

T

8

T

9

T

10

11

T

13

14

15

12

The WRA precharge (triggered by the automatic retire) is equivalent to a PRER command here

WR a1

WRA a2 retire (a2)

Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a5 = {Da,Ba}

COLX Packet: PREX Precharge Offset

CTM/CFM

ROW2

..ROW0 COL4

..COL0

T

0

The PREX precharge command is equivalent to a PRER command here

T

1

ACT a0

T

2

3

4

T

5

6

7

T

8

T

9

RD a1

T

10

11

T

13

14

15

12

RD a2

T

16

retire (a1)

T

16

T

17

T

17

RD a3

Q (a2)Q (a1)

Q (a4)Q (a3)

a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2}

T

37

T

37

T

38

39

T

38

39

a5 = {Da,Ba}

T

41

42

43

40

T

41

42

43

40

T

45

46

47

44

T

45

46

47

44

a3 = {Da,Ba,Ca3} a4 = {Da,Ba,Ca4}

T

18

19

20

T

18

19

20

T

21

22

t

RTR

MSK (a2)MSK (a1)

T

21

22

RD a4

PREX a5

T

23

T

25

24

PRER a5

T

26

27

T

29

30

31

28

32

T

33

T

34

35

36

ACT b0ACT a0

t

OFFP

D (a2)D (a1)

T

23

T

25

24

PRER a5

T

26

27

T

29

30

31

28

32

T

33

T

34

35

36

ACT b0

t

OFFP

DQA8..0

DQB8..0

24

Transaction a: RD a0 = {Da,Ba,Ra}

Data Sheet E0039N30 (Ver. 3.0)

Q (a2)Q (a1)

Q (a4)Q (a3)

a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a3 = {Da,Ba,Ca3} a4 = {Da,Ba,Ca4}

a5 = {Da,Ba}

µµµµ

PD488588

13. Read Transaction - Example

Figure 13-1 shows an example of a read transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time t includes the device, bank, and row address (abbreviated as a0) while the RD command includes device, bank, and column address (abbreviated as a1). A time t the device. Note that the packets on the ROW and COL pins use the end of the packet as a timing reference point, while the packets on the DQA/DQB pins use the beginning of the packet as a timing reference point. A time t

after the first COLC packet on the COL pins a second is issued. It contains a RD a2 command. The a2

CC

address has the same device and bank address as the a1 address (and a0 address), but a different column address. A time t

after the second RD command a second read data dualoct Q(a2) is returned by the device.

CAC

Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. The a3 address includes the same device and bank address as the a0, a1, and a2 addresses. The PRER command must occur a time t

RAS

and the contents of the selected row must be restored from the two associated sense amps of the bank during the t

interval). The PRER command must also occur a time t

RAS

t

value shown is greater than the t

RDP

two dualocts, but there is actually enough time to read three dualocts before t rather than t

. If four dualocts were read, the packet with PRER would need to shift right (be delayed) by one t

RAS

(note-this case is not shown). Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT command must occur a time t

or more after the first ACT command and a time t

RC

that the bank and its associated sense amps are precharged. This example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. Transaction b may not be started until transaction a has finished. However, transactions to other banks or other devices may be issued during transaction a.

later a RD a1 command is issued in a COLC packet. Note that the ACT command

RCD

after the RD command the read data dualoct Q (a1) is returned by

CAC

or more after the original ACT command (the activation operation in any DRAM is destructive,

or more after the last RD command. Note that the

RDP

specification in “36.Timing Parameters”. This transaction example reads

RDP,MIN

becomes the limiting parameter

RDP

CYCLE

or more after the PRER command. This ensures

RP

Figure 13-1 Read Transaction Example

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0 DQB8..0

T

0

T

1

2

3

4

T

5

6

7

T

8

T

9

T

10

T

11

15

12

T

13

14

T

17

18

19

16

20

t

RC

T

21

T

22

T

25

26

23

24

ACT a0 PRER a3

t

RAS

t

RCD

RD a1

RD a2

t

CC

t

CAC

t

RDP

t

Q (a1)

CAC

Q (a2)

T

27

T

28

32

T

29

30

31

T

33

34

35

T

37

38

39

36

ACT b0

t

RP

Transaction a: RD a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a3 = {Da,Ba}

Transaction b: xx b0 = {Da,Ba,Rb}

Data Sheet E0039N30 (Ver. 3.0)

T

40

T

41

T

42

T

45

46

43

47

44

25

µµµµ

PD488588

14. Write Transaction - Example

Figure 14-1 shows an example of a write transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time t measured to the end of the COLC packet with the first retire command). Note that the ACT command includes the device, bank, and row address (abbreviated as a0) while the WR command includes device, bank, and column address (abbreviated as a1). A time t the packets on the ROW and COL pins use the end of the packet as a timing reference point, while the packets on the DQA/DQB pins use the beginning of the packet as a timing reference point. A time t

after the first COLC packet on the COL pins a second COLC packet is issued. It contains a WR a2

CC

command. The a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. A time t A time t

after each WR command an optional COLM packet MSK (a1) is issued, and at the same time a COLC

RTR

packet is issued causing the write buffer to automatically retire. See Figure 15-1 for more detail on the write/retire mechanism. If a COLM packet is not used, all data bytes are unconditionally written. If the COLC packet which causes the write buffer to retire is delayed, then the COLM packet (if used) must also be delayed. Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. The a3 address includes the same device and bank address as the a0, a1, and a2 addresses. The PRER command must occur a time t

RAS

and the contents of the selected row must be restored from the two associated sense amps of the bank during the t

interval).

RAS

A PRER a3 command is issued in an ROWR packet on the ROW pins. The PRER command must occur a time t or more after the last COLC which causes an automatic retire. Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT command must occur a time t

or more after the first ACT command and a time t

RC

that the bank and its associated sense amps are precharged. This example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. Transaction b may not be started until transaction a has finished. However, transactions to other banks or other devices may be issued during transaction a.

- t

RCD

or more after the original ACT command (the activation operation in any DRAM is destructive,

later a WR a1 command is issued in a COLC packet (note that the t

RTR

after the WR command the write data dualoct D(a1) is issued. Note that

CWD

after the second WR command a second write data dualoct D(a2) is issued.

CWD

or more after the PRER command. This ensures

RP

interval is

RCD

Figure 14-1 Write Transaction Example

RTP

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0

DQB8..0

26

T

1

0

ACT a0

T

2

3

T

5

6

7

4

T

8

T

9

t

T

10

RCD

T

13

11

12

WR a2

t

Transaction a: WR Transaction b: xx b0 = {Da,Ba,Rb}

a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a3 = {Da,Ba}

T

14

t

RTR

CC

t

T

15

t

RAS

CWD

T

17

16

retire (a1)WR a1 MSK (a1)

T

18

t

CWD

19

t

T

20

RC

retire (a2) MSK (a2)

21

t

T

22

RTR

T

23

24

D (a2)D (a1)

Data Sheet E0039N30 (Ver. 3.0)

T

25

26

27

PRER a3

T

28

32

T

29

30

31

t

RTP

T

RP

T

33

34

ACT b0

T

35

T

37

38

39

36

T

40

T

41

T

42

T

45

46

43

47

44

µµµµ

PD488588

15. Write/Retire - Examples

The process of writing a dualoct into a sense amp of an RDRAM bank occurs in two steps. The first step consists of transporting the write command, write address, and write data into the write buffer. The second step happens when the RDRAM automatically retires the write buffer (with an optional bytemask) into the sense amp. This two-step write process reduces the natural turn-around delay due to the internal bidirectional data pins. Figure 15-1 (left) shows an example of this two step process. The first COLC packet contains the WR command and an address specifying device, bank and column. The write data dualoct follows a time t information is loaded into the write buffer of the specified device. The COLC packet which follows a time t will retire the write buffer. The retire will happen automatically unless (1) a COLC packet is not framed (no COLC packet is present and the S bit is zero), or (2) the COLC packet contains a RD command to the same device. If the retire does not take place at time t

after the original WR command, then the device continues to frame COLC

RTR

packets, looking for the first that is not a RD directed to itself. A bytemask MSK(a1) may be supplied in a COLM packet aligned with the COLC that retires the write buffer at time t

after the WR command.

RTR

The memory controller must be aware of this two-step write/retire process. Controller performance can be improved, but only if the controller design accounts for several side effects. Figure 15-1 (right) shows the first of these side effects. The first COLC packet has a WR command which loads the address and data into the write buffer. The third COLC causes an automatic retire of the write buffer to the sense amp. The second and fourth COLC packets (which bracket the retire packet) contain RD commands with the same device, bank and column address as the original WR command. In other words, the same dualoct address that is written is read both before and after it is actually retired. The first RD returns the old dualoct value from the sense amp before it is overwritten. The second RD returns the new dualoct value that was just written.

Figure 15-1 Normal Retire (left) and Retire/Read Ordering (right)

later. This

CWD

RTR

later

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0 DQB8..0

T

0

Transaction a: WR a1= {Da,Ba,Ca1}

T

1

2

3

4

Retire is automatic here unless: (1) No COLC packet (S=0) or

T

5

6

7

T

8

T

9

T

13

10

11

12

(2) COLC packet is RD to device Da

WR a1

t

CWD

t

RTR

retire (a1) MSK (a1)

D (a1)

T

14

15

T

17

18

19

16

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0 DQB8..0

T

21

22

23

20

0

T

1

2

3

T

5

6

7

4

T

8

T

9

10

T

13

11

12

T

14

15

17

16

This RD gets the old data This RD gets the new data

t

WR a1

RD b1 RD c1

t

CWD

Transaction a: WR Transaction b: RD

Transaction c: RD

RTR

CAC

retire (a1) MSK (a1)

D (a1)

a1= {Da,Ba,Ca1} b1= {Da,Ba,Ca1}

c1= {Da,Ba,Ca1}

Q (b1)

T

18

T

t

CAC

T

21

22

19

23

20

Figure 15-2 (left) shows the result of performing a RD command to the same device in the same COLC packet slot that would normally be used for the retire operation. The read may be to any bank and column address; all that matters is that it is to the same device as the WR command. The retire operation and MSK(a1) will be delayed by a time t

as a result. If the RD command used the same bank and column address as the WR command, the old

PACKET

data from the sense amp would be returned. If many RD commands to the same device were issued instead of the single one that is shown, then the retire operation would be held off an arbitrarily long time. However, once a RD to another device or a WR or NOCOP to any device is issued, the retire will take place. Figure 15-2 (right) illustrates a situation in which the controller wants to issue a WR-WR-RD COLC packet sequence, with all commands addressed to the same device, but addressed to any combination of banks and columns. The RD will prevent a retire of the first WR from automatically happening. But the first dualoct D(a1) in the write

Q (

Data Sheet E0039N30 (Ver. 3.0)

27

µµµµ

PD488588

buffer will be overwritten by the second WR dualoct D(b1) if the RD command is issued in the third COLC packet. Therefore, it is required in this situation that the controller issue a NOCOP command in the third COLC packet, delaying the RD command by a time of t

CCDELAY

is equal to t

RTR

.

t

. This situation is explicitly shown in Table 8-1 for the cases in which

PACKET

Figure 15-2 Retire Held Off by Read (left) and Controller Forces WWR Gap (right)

T

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0 DQB8..0

T

1

2

3

0

4

The retire operation for a write can be

held off by a read to the same device

WR a1

T

5

6

7

T

8

RD b1

T

9

10

11

12

retire (a1) MSK (a1)

t

+ t

RTR

PACKET

D (a1)

t

Transaction a: WR Transaction b: RD

CWD

a1= {Da,Ba,Ca1} b1= {Da,Bb,Cb1}

T

13

14

15

T

17

16

T

18

T

19

T

21

22

23

20

T

1

2

3

0

T

5

6

7

4

T

8

T

9

T

10

T

11

15

12

T

13

14

T17T18T

16

T

19

20

CTM/CFM

The controller must insert a NOCOP to retire (a1)

ROW2

to make room for the data (b1) in the write buffer

..ROW0

t

CAC

COL4

..COL0

Q (b1)

DQA8..0

WR a1

WR b1

t

RTR

retire (a1) MSK (a1)

RD c1

D (a1)

D (b1)

t

CAC

DQB8..0

t

Transaction a: WR Transaction b: WR

CWD

a1= {Da,Ba,Ca1} b1= {Da,Bb,Cb1}

Transaction c: RD c1= {Da,Bc,Cc1}

Figure 15-3 shows a possible result when a retire is held off for a long time (an extended version of Figure 15-2-left). After a WR command, a series of six RD commands are issued to the same device (but to any combination of bank and column addresses). In the meantime, the bank Ba to which the WR command was originally directed is precharged, and a different row Rc is activated. When the retire is automatically performed, it is made to this new row, since the write buffer only contains the bank and column address, not the row address. The controller can insure that this doesn’t happen by never precharging a bank with an unretired write buffer. Note that in a system with more than one RDRAM, there will never be more than two RDRAMs with unretired write buffers. This is because a WR command issued to one device automatically retires the write buffers of all other devices written a time t

RTR

before or earlier.

Figure 15-3 Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0

DQB8..0

28

T

0

T

1

2

T

5

6

3

4

ACT a0

Transaction a: WR Transaction b: RD

Transaction c: WR

T

t

T

7

RCD

T

9

8

T

10

11

T

12

t

RAS

t

16

RTR

T

13

14

15

T

17

18

19

20

t

RC

D (a1)

t

CWD

a0 = {Da,Ba,Ra} b1 = {Da,Bb,Cb1} b2 = {Da,Bb,Cb2} b4 = {Da,Bb,Cb4}

a1 = {Da,Ba,Ca1} a2 = {Da,Ba} b5 = {Da,Bb,Cb5}

c0 = {Da,Ba,Rc}

Data Sheet E0039N30 (Ver. 3.0)

T

21

22

23

PRER a2

T

24

T

25

T

26

T

27

31

28

32

T

29

30

T

33

T

37

34

35

36

The retire operation puts the

write data in the new row

ACT c0

t

RP

RD b2 RD b3 RD b4 RD b5 RD b6

t

CAC

Q (b1)

Q (b2) Q (b3) Q (b4) Q (b5)

WARNING

b3= {Da,Bb,Cb3} b6 = {Da,Bb,Cb6}

This sequence is hazardous and must be used with caution

T

38

39

T

40

T

41

T

42

T

45

46

43

47

44

retire (a1)RD b1WR a1 MSK (a1)

µµµµ

PD488588

16. Interleaved Write - Example

Figure 16-1 shows an example of an interleaved write transaction. Transactions similar to the one presented in Figure 14-1 are directed to non-adjacent banks of a single RDRAM. This allows a new transaction to be issued once every t

interval rather than once every t

RR

this sequence. With two dualocts of data written per transaction, the COL, DQA, and DQB pins are fully utilized. Banks are precharged using the WRA autoprecharge option rather than the PRER command in an ROWR packet on the ROW pins. In this example, the first transaction is directed to device Da and bank Ba. The next three transactions are directed to the same device Da, but need to use different, non-adjacent banks Bb, Bc, Bd so there is no bank conflict. The fifth transaction could be redirected back to bank Ba without interference, since the first transaction would have completed by then (t

has elapsed). Each transaction may use any value of row address (Ra, Rb, ...) and column

RC

address (Ca1, Ca2, Cb1, Cb2, ...).

Figure 16-1 Interleaved Write Transaction with Two Dualoct Data Length

interval (four times more often). The DQ data pin efficiency is 100% with

RC

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0 DQB8..0

T

1

2

3

0

T

5

6

7

4

8

ACT a0

MSK (y1)

WRA z2

MSK (y2)

D (x2) D (y1) D (y2)

T

9

T

10

T

11

15

12

T

13

14

T

17

18

19

16

T

21

22

23

20

t

RC

T

24

T

25

T

26

T

29

30

27

31

28

32

ACT b0 ACT c0 ACT d0 ACT e0

t

RCD

WR a1WR z1

MSK (z1)

WRA a2

MSK (z2)

t

CWD

D (z2)D (z1)

MSK (a1)

WRA b2

MSK (a2)

D (a2)D (a1)

WR c1WR b1

MSK (b1)

WRA c2

MSK (b2)

D (b2)D (b1)

T

33

34

35

t

RR

WR d1

MSK (c1)

T

36

T

37

same bank as transaction a

T

38

T

41

42

39

43

40

Transaction e can use the

ACT f0

D(c1)

WR d2

MSK (c2)

WR e1

MSK (d1)

D (c2) D (d1)

y3 = {Da,Ba+4}Transaction y: WR y0 = {Da,Ba+4,Ry} y1 = {Da,Ba+4,Cy1} y2= {Da,Ba+4,Cy2} z3 = {Da,Ba+6}Transaction z: WR z0 = {Da,Ba+6,Rz} z1 = {Da,Ba+6,Cz1} z2= {Da,Ba+6,Cz2}

a3 = {Da,Ba}Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2= {Da,Ba,Ca2} b3 = {Da,Ba+2}Transaction b: WR b0 = {Da,Ba+2,Rb} b1 = {Da,Ba+2,Cb1} b2= {Da,Ba+2,Cb2} c3 = {Da,Ba+4}Transaction c: WR c0 = {Da,Ba+4,Rc} c1 = {Da,Ba+4,Cc1} c2= {Da,Ba+4,Cc2} d3 = {Da,Ba+6}Transaction d: WR d0 = {Da,Ba+6,Rd} d1 = {Da,Ba+6,Cd1} d2= {Da,Ba+6,Cd2}

e3 = {Da,Ba}Transaction e: WR e0 = {Da,Ba,Re} e1 = {Da,Ba,Ce1} e2= {Da,Ba,Ce2}

f3 = {Da,Ba+2}Transaction f: WR f0 = {Da,Ba+2,Rf} f1 = {Da,Ba+2,Cf1} f2= {Da,Ba+2,Cf2}

T

44

T

45

46

WR e2

MSK (d2)

47

Q (

Data Sheet E0039N30 (Ver. 3.0)

29

µµµµ

PD488588

17. Interleaved Read - Example

Figure 17-1 shows an example of interleaved read transactions. Transactions similar to the one presented in Figure 13-1 are directed to non-adjacent banks of a single RDRAM. The address sequence is identical to the one used in the previous write example. The DQ data pins efficiency is also 100%. The only difference with the write example (aside from the use of the RD command rather than the WR command) is the use of the PREX command in a COLX packet to precharge the banks rather than the RDA command. This is done because the PREX is available for a readtransaction but is not available for a masked write transaction.

Figure 17-1 Interleaved Read Transaction with Two Dualoct Data Length

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0

DQB8..0

T

0

T

1

T

2

3

T

5

6

4

ACT a0

RD z1 RD z2

PREX y3

Q (x2) Q (y1) Q (y2)

T

7

T

8

T

9

T

10

T

11

15

12

T

13

14

T

17

18

19

16

T

21

22

23

20

t

RC

T

24

T

25

29

26

27

28

ACT b0 ACT c0 ACT d0 ACT e0

t

RCD

RD a1 RD a2

PREX z3

t

CAC

PREX a3

PREX b3

T

30

31

T

33

34

35

32

T

37

38

39

36

Transaction e can use the

same bank as transaction a

T

41

42

43

40

44

T

45

46

47

ACT f0

t

RR

RD c2RD c1RD b1 RD b2

RD d1 RDd2

PREX c3

RD e1 RD e2

PREX d3

Q (b2)Q (b1)Q (a2)Q (a1) Q (c1) Q (c2) Q (d1)Q (z2)Q (z1)

y3 = {Da,Ba+4}Transaction y: RD y0 = {Da,Ba+4,Ry} y1 = {Da,Ba+4,Cy1} y2= {Da,Ba+4,Cy2} z3 = {Da,Ba+6}Transaction z: RD z0 = {Da,Ba+6,Rz} z1 = {Da,Ba+6,Cz1} z2= {Da,Ba+6,Cz2}

a3 = {Da,Ba}Transaction a: RD a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2= {Da,Ba,Ca2} b3 = {Da,Ba+2}Transaction b: RD b0 = {Da,Ba+2,Rb} b1 = {Da,Ba+2,Cb1} b2= {Da,Ba+2,Cb2} c3 = {Da,Ba+4}Transaction c: RD c0 = {Da,Ba+4,Rc} c1 = {Da,Ba+4,Cc1} c2= {Da,Ba+4,Cc2} d3 = {Da,Ba+6}Transaction d: RD d0 = {Da,Ba+6,Rd} d1 = {Da,Ba+6,Cd1} d2= {Da,Ba+6,Cd2}

e3 = {Da,Ba}Transaction e: RD e0 = {Da,Ba,Re} e1 = {Da,Ba,Ce1} e2= {Da,Ba,Ce2}

f3 = {Da,Ba+2}Transaction f: RD f0 = {Da,Ba+2,Rf} f1 = {Da,Ba+2,Cf1} f2= {Da,Ba+2,Cf2}

30

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

18. Interleaved RRWW - Example

Figure 18-1 shows a steady-state sequence of 2-dualoct RD/RD/WR/WR.. transactions directed to non-adjacent banks of a single RDRAM. This is similar to the interleaved write and read examples in Figure 16-1 and Figure 17-1 except that bubble cycles need to be inserted by the controller at read/write boundaries. The DQ data pin efficiency for the example in Figure 18-1 is 32/42 or 76%. If there were more RDRAMs on the Channel, the DQ pin efficiency would approach 32/34 or 94% for the two-dualoct RRWW sequence (this case is not shown). In Figure 18-1, the first bubble type t pins. This bubble accounts for the round-trip propagation delay that is seen by read data, and is explained in detail in Figure 4-1. This bubble appears on the DQA and DQB pins as t dualoct Q. This bubble also appears on the ROW pins as t The second bubble type t

is inserted (as a NOCOP command) by the controller between a WR and RD

CBUB2

command on the COL pins when there is a WR-WR-RD sequence to the same device. This bubble enables write data to be retired from the write buffer without being lost, and is explained in detail in Figure 15-2. There would be no bubble if address c0 and address d0 were directed to different devices. This bubble appears on the DQA and DQB pins as t as t

RBUB2

between a write data dualoct D and read data dualoct Q. This bubble also appears on the ROW pins

DBUB2

.

Figure 18-1 Interleaved RRWW Sequence with Two Dualoct Data Length

is inserted by the controller between a RD and WR command on the COL

CBUB1

between a write data dualoct D and read data

DBUB1

.

RBUB1

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0 DQB8..0

T

1

2

0

t

CBUB2

RD z1 RD z2

t

DBUB1

D (y2)

T

3

ACT a0

T

5

6

7

4

t

DBUB2

T

9

10

11

8

RD a1 RD a2

T

13

12

t

RBUB1

T

14

15

T

16

T

17

21

18

19

20

ACT b0 ACT c0

t

CBUB1

PREX z3

MSK (y2)

Q (z2)Q (z1)

T

22

T

23

24

WRA b2 PREX a3

T

25

T

26

Q (a2)Q (a1)

T

27

28

WR c1WR b1

MSK (b1)

29

T

30

T

31

32

t

RBUB2

WRA c2

MSK (b2)

T

33

T

34

T

37

38

35

36

Transaction e can use the same bank as transaction a

ACT d0

t

CBUB2

NOCOP

MSK (c1)

D (b2)D (b1)

D (c1)

T

39

T

41

42

43

40

ACT e0

NOCOP RDd0

MSK (c2)

t

DBUB1

D (c2)

y3 = {Da,Ba+4}Transaction y: WR y0 = {Da,Ba+4,Ry} y1 = {Da,Ba+4,Cy1} y2= {Da,Ba+4,Cy2} z3 = {Da,Ba+6}Transaction z: RD z0 = {Da,Ba+6,Rz} z1 = {Da,Ba+6,Cz1} z2= {Da,Ba+6,Cz2}

a3 = {Da,Ba}Transaction a: RD a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2= {Da,Ba,Ca2} b3 = {Da,Ba+2}Transaction b: WR b0 = {Da,Ba+2,Rb} b1 = {Da,Ba+2,Cb1} b2= {Da,Ba+2,Cb2} c3 = {Da,Ba+4}Transaction c: WR c0 = {Da,Ba+4,Rc} c1 = {Da,Ba+4,Cc1} c2= {Da,Ba+4,Cc2} d3 = {Da,Ba+6}Transaction d: RD d0 = {Da,Ba+6,Rd} d1 = {Da,Ba+6,Cd1} d2= {Da,Ba+6,Cd2}

e3 = {Da,Ba}Transaction e: RD e0 = {Da,Ba,Re} e1 = {Da,Ba,Ce1} e2= {Da,Ba,Ce2}

f3 = {Da,Ba+2}Transaction f: WR f0 = {Da,Ba+2,Rf} f1 = {Da,Ba+2,Cf1} f2= {Da,Ba+2,Cf2}

T

45

46

47

44

RDf

Data Sheet E0039N30 (Ver. 3.0)

31

µµµµ

PD488588

19. Control Register Transactions

The RDRAM has two CMOS input pins SCK and CMD and two CMOS input/output pins SIO0 and SIO1. These provide serial access to a set of control registers in the RDRAM. These control registers provide configuration information to the controller during the initialization process. They also allow an application to select the appropriate operating mode of the RDRAM. SCK (serial clock) and CMD (command) are driven by the controller to all RDRAMs in parallel. SIO0 and SIO1 are connected (in a daisy chain fashion) from one RDRAM to the next. In normal operation, the data on SIO0 is repeated on SIO1, which connects to SIO0 of the next RDRAM (the data is repeated from SIO1 to SIO0 for a read data packet). The controller connects to SIO0 of the first RDRAM. Write and read transactions are each composed of four packets, as shown in Figure 19-1 and Figure 19-2. Each packet consists of 16 bits, as summarized in Table 20-1 and Table 20-2. The packet bits are sampled on the falling edge of SCK. A transaction begins with a SRQ (Serial Request) packet. This packet is framed with a 11110000 pattern on the CMD input (note that the CMD bits are sampled on both the falling edge and the rising edge of SCK). The SRQ packet contains the SOP3..SOP0 (Serial Opcode) field, which selects the transaction type. The SDEV5..SDEV0 (Serial Device address) selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is set, then all RDRAMs are selected. The SA (Serial Address) packet contains a 12 bit address for selecting a control register. A write transaction has a SD (Serial Data) packet next. This contains 16 bits of data that is written into the selected control register. A SINT (Serial Interval) packet is last, providing some delay for any side-effects to take place. A read transaction has a SINT packet, then a SD packet. This provides delay for the selected RDRAM to access the control register. The SD read data packet travels in the opposite direction (towards the controller) from the other packet types. The SCK cycle time will accommodate the total delay.

Figure 19-1 Serial Write (SWR) Transaction to Control Register

SCK

CMD

SIO0

SIO1

SCK

CMD

1111

SIO

1111

T

36

SD

T

52

next transaction

SINT

T

1111

68

1 0 1 0 1 0 1 0

0000

T

4

00000000...00000000

SRQ - SWR command

T

20

Each packet is repeated

from SIO0 to SIO1

00000000...00000000 00000000...00000000 00000000...00000000

SA

Figure 19-2 Serial Read (SRD) Transaction Control Register

T

4

0000

0

1

00000000...00000000

SRQ - SRD command

First 3 packets are repeated

from SIO0 to SIO1

SRQ - SRD command

T

20

00000000...00000000 00000000...00000000 00000000...00000000

SA

T

36

addressed RDRAM devices

0/SD15..SD0/0 on SIO0

SINT

T

52

controller drives

0 on SIO0

0

SD

non addressed RDRAMs pass

0/SD15..SD0/0 from SIO1 to SIO0

SD

next transaction

T

68

1 0 1

1111

0 1

0

0 1

0

32

Data Sheet E0039N30 (Ver. 3.0)

20. Control Register Packets

Table 20-1 summarizes the formats of the four packet types for control register transactions. Table 20-2 summarizes the fields that are used within the packets. Figure 20-1 shows the transaction format for the SETR, CLRR, and SETF commands. These transactions consist of a single SRQ packet, rather than four packets like the SWR and SRD commands. The same framing sequence on the CMD input is used, however. These commands are used during initialization prior to any control register read or write transactions.

Table 20-1 Control Register Packet Formats

µµµµ

PD488588

Figure 20-1 SETR, CLRR, SETF Transaction

SCK

CMD

SIO0

SIO1

T

4

1111

0000

00000000...00000000

SRQ packet - SETR/CLRR/SETF

The packet is repeated

from SIO0 to SIO1

SRQ packet - SETR/CLRR/SETF

T

20

1 0 1 0 1 0 1 0

SCK Cycle

SIO0 or SIO1 for SRQ

SIO0 or SIO1 for SA

SIO0 or SIO1 for SINT

SIO0 or SIO1 for SD

SCK Cycle

SIO0 or SIO1 for SRQ

SIO0 or SIO1 for SA

SIO0 or SIO1 for SINT

SIO0 or SIO1

for SD 0 rsrv rsrv 0 SD15 8 SOP1 SA7 0 SD7 1 rsrv rsrv 0 SD14 9 SOP0 SA6 0 SD6 2 rsrv rsrv 0 SD13 10 SBC SA5 0 SD5 3 rsrv rsrv 0 SD12 11 SDEV4 SA4 0 SD4 4 rsrv SA11 0 SD11 12 SDEV3 SA3 0 SD3 5 SDEV5 SA10 0 SD10 13 SDEV2 SA2 0 SD2 6 SOP3 SA9 0 SD9 14 SDEV1 SA1 0 SD1 7 SOP2 SA8 0 SD8 15 SDEV0 SA0 0 SD0

Table 20-2 Field Description for Control Register Packets

Field Description rsrv Reserved. Should be driven as “0” by c ontroller. SOP3..SOP0 0000 - SRD. Serial read of control regi ster {SA11..SA0} of RDRA M {SDEV5..SDEV0}. 0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM {SDEV5.. S DEV0}.

Note

0010 - SETR. Set Reset bit , all control registers assume their reset values .

16 t

delay until CLRR

SCYCLE

command.

0100 - SETF. Set fast (norm al ) c l ock mode. 4 t

1011 - CLRR. Clear Reset bit, all c ontrol registers retain their reset values.

delay until next comm and.

SCYCLE

Note

4 t

delay until next

SCYCLE

command.

1111 - NOP. No serial operation.

0011, 0101 – 1010, 1100 – 1110 – RSRV. Reserved encodings. SDEV5..SDEV0 Serial device. Compared to SDEVID5. .SDEVID0 field of INI T control register field to s el ect the RDRAM to

which the transaction is directed. SBC Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM sel ection. SA11..SA0 Serial address . Selects which cont rol regi ster of the selected RDRAM i s read or written. SD15..SD0 Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM.

Note The SETR and CLRR commands must always be applied in two successive transac tions to RDRAMs; i.e. they may not be used in isolation. This i s called “SETR/CLRR Reset”.

Data Sheet E0039N30 (Ver. 3.0)

33

21. Initialization

Figure 21-1 SIO Pin Reset Sequence

T

0

SCK

µµµµ

PD488588

T

16

1 0

CMD

SIO0

SIO1

00001100

00000000...00000000

0000000000000000

The packet is repeated

from SIO0 to SIO1

0000000000000000

1 0 1 0 1 0

Initialization refers to the process that a controller must go through after power is applied to the system or the system is reset. The controller prepares the RDRAM sub-system for normal Channel operation by (primarily) using a sequence of control register transactions on the serial CMOS pins. The following steps outline the sequence seen by the various memory subsystem components (including the RDRAM components) during initialization. This sequence is available in the form of reference code. Contact Rambus Inc. for more information.

1.0 Start Clocks

This step calculates the proper clock frequencies for PClk (controller logic), SynClk (RAC block), RefClk (DRCG component), CTM (RDRAM component), and SCK (SIO block).

2.0 RAC Initialization

This step causes the INIT block to generate a sequence of pulses which resets the RAC, performs RAC maintainance operations, and measures timing intervals in order to ensure clock stability.

3.0 RDRAM Initialization

This stage performs most of the steps needed to initialize the RDRAMs. The rest are performed in stages 5.0,

6.0, and 7.0. All of the steps in 3.0 are carried out through the SIO block interface.

3.1/3.2 SIO Reset

After a delay of tPAUSE

from step 1.0, this reset operation is performed before any SIO control register read or write transactions. It clears six registers (TEST34, CCA, CCB, SKIP, TEST78, and TEST79) and places the INIT register into a special state (all bits cleared except SKP and SDEVID fields are set to ones).

3.3 Write TEST77 Register The TEST77 register must be explicitly written with zeros before any other registers are read or written.

3.4 Write TCYCLE Register The TCYCLE register is written with the cycle time t

units of 64ps. The t

value is determined in stage 1.0.

CYCLE

of the CTM clock (for Channel and RDRAMs) in

CYCLE

3.5 Write SDEVID Register The SDEVID (serial device identification) register of the RDRAM is written with a unique address value so

that directed SIO read and write transactions can be performed. This address value increases from 0 to 31 according to the distance an RDRAM is from the ASIC component on the SIO bus (the closest RDRAM is address 0).

34

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

3.6 Write DEVID Register The DEVID (device identification) register of the RDRAM is written with a unique address value so that

directed memory read and write transactions can be performed. This address value increases from 0 to 31. The DEVID value is not necessarily the same as the SDEVID v alue. RDRAMs are sorted into regions of the same core configuration (number of bank, row, and column address bits and core type).

3.7 Write PDNX, PDNXA Registers The PDNX and PDNXA registers are written with values that are used to measure the timing intervals

connected with an exit from the PDN (powerdown) power state.

3.8 Write NAPX Register The NAPX register is written with values that are used to measure the timing intervals connected with an exit

from the NAP power state.

3.9 Write TPARM Register The TPARM register is written with values which determine the time interval between a COL packet with a

memory read command and the Q packet with the read data on the Channel. The values written set the RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0.

3.10 Write TCDLY1 Register The TCDLY1 register is written with values which determine the time interval between a COL packet with a

memory read command and the Q packet with the read data on the Channel. The values written set the RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0.

3.11 Write TFRM Register

parameter for the system. The t

The TFRM register is written with a value that is related to the t parameter is the time interval between a ROW packet with an activate command and the COL packet with a read or write command.

3.12 SETR/CLRR

First write the following registers with the indicated values: TEST78 000416 TEST34 004016 Next, the RDRAM is given a SETR command and a CLRR command through the SIO block. This sequence performs a second reset operation on the RDRAMs. Then the TEST34 and TEST78 registers are rewritten with zero, in that order.

3.13 Write CCA and CCB Registers These registers are written with a value halfway between their minimum and maximum values. This shortens the time needed for the RDRAMs to reach their steady-state current control values in stage 5.0.

3.14 Powerdown Exit

The RDRAM is in the PDN power state at this point. A broadcast PDNExit command is performed by the SIO block to place the RDRAMs in the RLX (relax) power state in which they are ready to receive ROW packets.

3.15 SETF

The RDRAM is given a SETF command through the SIO block. One of the operations performed by this step is to generate a value for the AS (autoskip) bit in the SKIP register and fix the RDRAM to a particular read domain.

RCD

Data Sheet E0039N30 (Ver. 3.0)

35

µµµµ

PD488588

4.0 Controller Configuration

This stage initializes the controller block. Each step of this stage will set a field of the ConfigRMC[63:0] bus to the appropriate value. Other controller implementations will have similar initialization requirements, and this stage may be used as a guide.

4.1 Initial Read Data Offset

The ConfigRMC bus is written with a value which determines the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The value written sets RMC.d1 to the minimum value permitted for the system. This will be adjusted later in stage 6.0.

4.2 Configure Row/Column Timing

This step determines the values of the tRAS,MIN

, t

RP,MIN

, t

RC,MIN

, t

RCD,MIN

, t

RR,MIN

, and t

RDRAM timing

PP,MIN

parameters that are present in the system. The ConfigRMC bus is written with values that will be compatible with all RDRAM devices that are present.

4.3 Set Refresh Interval

This step determines the values of the t

RDRAM timing parameter that are present in the system. The

REF,MAX

ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.

4.4 Set Current Control Interval

This step determines the values of the t

CCTRL,MAX

RDRAM timing parameter that are present in the system.

The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.

4.5 Set Slew Rate Control Interval

This step determines the values of the t

TEMP,MAX

RDRAM timing parameter that are present in the system. The

ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.

4.6 Set Bank/Row/Col Address Bits

This step determines the number of RDRAM bank, row, and column address bits that are present in the system. It also determines the RDRAM core types (independent, doubled, or split) that are present. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.

5.0 RDRAM Current Control This step causes the INIT block to generate a sequence of pulses which performs RDRAM maintenance operations.

6.0 RDRAM Core, Read Domain Initialization

This stage completes the RDRAM initialization

6.1 RDRAM Core Initialization

A sequence of 192 memory refresh transactions is performed in order to place the cores of all RDRAMs into the proper operating state.

6.2 RDRAM Read Domain Initialization

A memory write and memory read transaction is performed to the RDRAM to determine which read domain the RDRAM occupies. The programmed delay of the RDRAM is then adjusted so the total RDRAM read delay (propagation delay plus programmed delay) is constant. The TPARM and TCDLY1 registers of the RDRAM is rewritten with the appropriate read delay values. The ConfigRMC bus is also rewritten with an updated value.

36

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

7.0 Other RDRAM Register Fields

This stage rewrites the INIT register with the final values of the LSR, NSR, and PSR fields. In essence, the controller must read all the read-only configuration registers of all RDRAMs (or it must read the SPD device present on each RIMM), it must process this information, and then it must write all the read-write registers to place the RDRAMs into the proper operating mode.

Initialization Note :

1. During the initialization process, it is necessary for the controller to perform 128 current control operations (3xCAL, 1xCAL/SAM) and one temperature calibrate operation (TCEN/TCAL) after reset or after powerdown (PDN) exit.

2. The behavior of

S28IECO=1: Upon powerup, the device enters PDN state. The serial operations SETR, CLRR, and SETF

require a SDEVID match.

See the document detailing the reference initialization procedure for more information on how to handle this in

a system.

3. After the step of equaliz ing the total read delay of the RDRAM has been completed (i.e. after the TCDLY0 and TCDLY1 fields have been written for the final time), a single final memory read transaction should be made to the RDRAM in order to ensure that the output pipeline stages have been cleared.

4. The SETF command (in the serial SRQ packet) should only be issued once during the Initialization process, as should the SETR and CLRR commands.

5. The CLRR command (in the serial SRQ packet) leaves some of the contents of the memory core in an indeterminate state.

PD488588 at initialization is as follows. It is distinguished by the "S28IECO" bit in the SPD.

µ

Data Sheet E0039N30 (Ver. 3.0)

37

µµµµ

PD488588

22. Control Register Summary

Table 22-1 summarizes the RDRAM control registers. Detail is provided for each control register in Figure 22-1. Read-only bits which are shaded gray are unused and return zero. Read-write bits which are shaded gray are reserved and should always be written with zero. The RIMM SPD Application Note (DL-0054) of Rambus Inc. describes additional read-only configuration registers which are present on Direct RIMMs. The state of the register fields are potentially affected by the IO Reset operation or the SETR/CLRR operation. This is indicated in the text accompanying each register diagram.

Table 22-1 Control Register Summary (1/2)

SA11..SA0 Register Field read-write/ read-only Description 02116 INIT SDEVID read-write, 6 bits Serial devic e I D. Device address for cont rol regi ster read/write. PSX read-write, 1 bit Power select exit. PDN/NAP exit with device addr on DQA5.. 0. SRP read-write, 1 bi t SIO repeater. Used to initialize RDRAM. NSR read-write, 1 bit NAP self-refresh. Enables s el f-refresh in NAP mode. PSR read-wri te, 1 bit PDN self-refresh. Enables self-refres h i n PDN mode. LSR read-writ e, 1 bit Low power self-refresh. E nabl es low power self-refresh. TEN read-write, 1 bit Temperature s ensing enable. TSQ read-write, 1 bi t Temperature sensing output. DIS read-write, 1 bit RDRAM disable. IDM read-write, 1 bit Interleaved Device Mode enable. 02216 TEST34 TEST 34 read-write, 16 bits Test regist er. Do not read or write after SIO reset. 02316 CNFGA REFBIT read-only, 3 bits Refresh bank bits. Us ed f or multi-bank refresh. DBL read-only , 1 bit Doubl e. Specifies doubled-bank archi tecture. MV ER read-only, 6 bits Manufacturer version. Manufac turer identification number. PVER read-only, 6 bits Protocol version. Specif ies version of Direct protocol supported. 02416 CNFGB BYT read-only, 1 bit Byte. Specifies an 8-bi t or 9-bi t byte size. DEVTYP read-only, 3 bits Device type. Devic e can be RDRAM or some other device c ategory.

SVER read-only, 6 bits Stepping version. Mask version number. 04016 DEVID DEVID read-wri te, 5 bits Device ID. Devic e address for memory read/write. 04116 REFB RE FB read-write, 4 bits Refresh bank. Next bank to be refreshed by self -refresh. 04216 REFR REFR read-write, 9 bits Refresh row. Next row to be refreshed by REFA, sel f -refresh. 04316 CCA CCA read-write, 7 bits Current control A. Cont rol s IOL output current for DQA. ASYMA read-write, 2 bits Asymmetry control. Controls asy mmet ry of VOL/VOH swing for DQA. 04416 CCB CCB read-write, 7 bits Current control B. Cont rol s IOL output current for DQB. ASYMB read-write, 2 bits Asymmetry control. Controls asy mmet ry of VOL/VOH swing for DQB. 04516 NAPX NAPXA read-write, 5 bits NAP exit. Specifies lengt h of NAP ex it phas e A. NAPX read-write, 5 bits NAP exit. Specifies length of NAP exit phase A + phase B. DQS read-write, 1 bi t DQ select. Selects CMD framing for NAP/PDN exit. 04616 PDNXA PDNXA read-write, 13 bi t s PDN exit. Specifies l ength of PDN exit phase A.

SPT CORG

read-only, 1 bit Split-core. Each core half is an individual dependent core. read-only, 6 bits Core organization. Bank, row, column address field si zes.

38

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

Table 22-1 Control Register Summary (2/2)

SA11..SA0 Register Field read-write/ read-only Description 04716 PDNX P DNX read-write, 13 bits PDN exit. Specifies length of PDN exit phase A + phase B. 04816 TPARM TCAS read-write, 2 bits t TCLS read-write, 2 bits t TCDLY0 read-write, 3 bits t 04916 TFRM TFRM read-write, 4 bits t 04a16 TCDLY1 TCDLY1 read-write, 3 bits 04c16 TCYCLE TCYCLE read-write, 14 bits t 04b16 SKIP AS read-only, 1 bit Autosk i p value established by the SE TF command. MSE read-write, 1 bi t Manual ski p enabl e. Allows the MS value to ov erri de the AS value. MS read-write, 1 bit Manual skip value. 04d16- TEST77 TEST77 read-write, 16 bits Test regi ster. Write with zero after S I O reset. 04e16- TEST78 TEST78 read-write, 16 bits Test regi ster. Do not read or write after SIO reset. 04f16- TEST79 TEST79 read-write, 16 bits Tes t register. Do not read or write after SI O reset. 08016-Off16 reserved reserved vendor-specif i c Vendor-specific tes t registers. Do not read or write after SIO reset.

core parameter. Determines t

CAS-C

core parameter. Determines t

CLS-C

core parameter. Programmable delay for read data.

CDLY0-C

core parameter. Determines ROW - COL packet framing interval.

FRM-C

core parameter. Programmable delay for read data.

CDLY-1

t

datasheet parameter. Specifies cycle time in 64ps units.

CYCLE

datasheet parameter.

OFFP

CAC

and t

parameters.

OFFP

Data Sheet E0039N30 (Ver. 3.0)

39

µµµµ

PD488588

Figure 22-1 Control Registers (1/7)

Control Register : INIT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDE

IDM

Read/write register. Reset values are undefined except as affected by SI O Reset as noted below. SETR/CLRR Reset does not affect thi s register.

DIS TSQ TEN LSR PSR NSR SRP PSX 0 SDEVID4..0

VID5

Address : 021

16

Field Description

SDEVID5..0

DIS

TSQ

TEN

LSR PSR NSR SRP PSX

Serial Device Identif i cation. Compared to SDEVID5. .0 serial address field of serial request packet for register read/write transactions . This determines which RDRAM i s selected for the regist er read or write operation. RDRAM disable. DIS=1 c auses RDRAM to ignore NAP/PDN exit sequence, DIS=0 permit normal operation. This mechanism dis abl es an RDRAM. Temperature Sensing Output. TSQ=1 when a t em perat ure trip point has been exceeded, TSQ=0 when it has not. TSQ is available during a c urrent control operation (see Figure 25-1). Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the TSQ bit t o be read to determine if a thermal tri p poi nt has been exceeded.

Low Power Self-Refresh. This function is not supported. LS R value must be 0. PDN Self-Refresh. PS R=1 enables self-refresh in PDN mode. P SR can’t be set while in PDN mode. NAP Self-Refresh. NS R=1 enabl es self-refresh in NAP mode. NSR can’t be set while in NAP mode. SIO Repeater. Controls value on S IO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0. Power Exit Select. PDN and NAP are exited with (=0) or wit hout (=1) a device address on the DQA5..0 pi ns.

PDEV5 (on DQA5) selectes broadcast (1) or directed (0) exit. For a di rcted exit, PDEV4..0 (on DQA4..0) is compared to DEVID4..0 t o select a device.

Control Register : CNFGA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PVER5..0=000001 MVER5..0=mmmmmm DBL1 REFBIT2..0=101

Read only register.

Address : 023

16

Reset value

3f16

0

0 0 0 1

Field Description PVER5..0

MVER5..0 Manuf acturer Version. Specifi es the manufacturer identifi cation number.

DBL

REFBIT2..0

Caution In RDRAMs with protoco l version 1 PVER[5:0] =000001, the range of the PDNX field (PDNX[2:0] in the PDNX

40

Protocol Version. Specifies the Direct Prot ocol version used by this device: 0 – Reserved 1 – Version 1 protocol. 2 – Version 1 plus Interleaved Devi ce Mode. 3 to 63 – Reserved

Doubled-Bank. DBL=1 means the dev i ce uses a doubled-bank architect ure wi th adjacent-bank dependency. DBL=0 means no dependency. Refresh Bank Bits. Specifies the number of bank address bits used by REFA and REFP commands. Permits multi-bank refresh in future RDRAMs.

register) may not be large enough to specify the location of the restricted interval i n Figure 23-3. In this case, the effective tS4 parameter must increase and no row or column packets may overlap the restricted i nterval. See Figure 23-3 and Timing conditions table.

Data Sheet E0039N30 (Ver. 3.0)

Figure 22-1 Control Registers (2/7)

Control Register : CNFGB

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SVER5..0=ssssss CORG4..0=01000 SPT0 DEVTYP2..0=000 BYTB

Read only register. Field Description

SVER5..0 Stepping version. Specifies the mask v ersion number of this device.

CORG4..0

SPT Split-core. SPT=1 means the c ore is split, SPT=0 means it is not.

DEVTYP2..0 Device type. DEVTYP=000 means that this device is an RDRAM.

BYT Byte width. B=1 means the dev i ce reads and writes 9-bit memory bytes.B=0 means 8 bits .

Core organization. This field specifies the number of bank (5 bi t s), row (9 bits), and column (7 bit s) address bits.

Address : 024

16

µµµµ

PD488588

Control Register : TEST34 Address : 02216

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Read/write register. Reset values of TEST34 is zero (from SIO Reset). This register are used for tes ting purposes. It must not be read or written after SIO Reset .

Control Register : DEVID Address : 04016

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 DEVID4..0

Read/write register. Reset value is undefined.

Field Description

DEVID4..0

Device Identific at ion register. DEVID4..DEVID0 is compared to DR4.. DR0, DC4..DC0, and DX4..DX0 fiel ds for all memory read or write transact i ons. This determines whic h RDRA M is selected for the memory read or write transaction.

Data Sheet E0039N30 (Ver. 3.0)

41

Figure 22-1 Control Registers (3/7)

Control Register : REFB Address : 04116

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 REFB4..0

Read/write register.

µµµµ

PD488588

Field Description

REFB4..0

Refresh Bank Register. REFB4. .REFB0 is the bank that will be refreshed next during self-refresh. REFB4..0 is incremented after each self-refresh activat e and precharge operation pair.

Control Register : REFR Address : 04216

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 REFR8..0

Read/write register.

Field Description

REFR8..0

Refresh Row register. REFR8..REFR0 is the row that will be refreshed next by t he RE FA command or by self-refresh. REFR8..0 is incremented when BR4..0=11111 for t he RE FA command. REFR8..0 is incremented when REFB4..0=11111 for s el f-refresh.

Control Register : CCA Address : 04316

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

Read/write register.

Field Description

ASYMA0

CCA6..0

ASYMA0 control the asymmetry of the VOL/VOH voltage swing about the V DQA8..0 pins.

ASYMA0 ODF

0 0.00

1 0.12 Where ODF is the Over Drive Factor (the extra I Current Control A. Controls the I

OL

ASYM

A0

current sunk by an RSL output when ASYMA0 is set ).

OL

output current for the DQA8.. DQA 0 pi ns.

CCA6..0

reference voltage for the

REF

Control Register : CCB Address : 04416

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

Read/write register.

ASYM

B0

CCB6..0

Reset

value

0

Reset

value

0

Reset

value

0

Field Description

ASYMB0

CCB6..0

ASYMB0 control the asymmetry of the VOL/VOH voltage swing about the V DQB8..0 pins.

ASYMB0 ODF

0 0.00

1 0.12 Where ODF is the Over Drive Factor (the extra I Current Control B. Controls the I

42

Reset

value

current sunk by an RSL output when ASYMB0 is set ).

OL

output current for the DQB8.. DQB 0 pi ns.

OL

Data Sheet E0039N30 (Ver. 3.0)

reference voltage for the

REF

0

Figure 22-1 Control Registers (4/7)

Control Register : NAPX Address : 04516

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 DQS NAPX4..0 NAPXA4..0

Read/write register. Reset value is undefined. Note t

SCYCLE

is t

Field Description

DQS

DQ Select. This field specifies the number of SCK cycles (0 ≥ 0.5 cycles, 1 ≥ 1.5 cycles) between the CMD pin framing sequence and the device selection on DQ5..0. see Figure 23-4. Thi s field must be written wit h a ”1” for this RDRAM.

NAPX4..0

Nap Exit Phase A plus B. This field specifies the number of SCK cycles during the first plus second phases for exiting NAP mode. It must satisfy: NAPX•t Do not set this field to zero.

NAPXA4..0

Nap Exit Phase A. This field specifies the number of SCK cycles during the first phase for exiting NAP mode. It must satisfy: NAPXA•t Do not set this field to zero.

(SCK cycle time).

CYCLE1

SCYCLE

≥ NAPXA•t

≥ t

NAPXA,MAX

SCYCLE+tNAPXB,MAX

Control Register : PDNXA Address : 04616

µµµµ

PD488588

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 PDNXA12..0

Read/write register. Reset value is undefined.

Field Description

PDNXA4..0

PDN Exit Phase A. Thi s field specifies t he num ber of (64•SCK cycle) units during the first phase for exiting PDN mode. It must sati sfy: PDNXA•64•t

SCYCLE

≥ t

PDNXA,MAX

Do not set this field to zero. Note – only PDNXA4..0 are i m pl emented. Note – t

SCYCLE

is t

(SCK cycle time).

CYCLE1

Control Register : PDNX Address : 04716

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 PDNX12..0

Read/write register. Reset value is undefined.

Field Description

PDNX2..0

PDN Exit Phase A puls B. This field specifies the number of (256•SCK cycle) units during the first plus second phases for exiting PDN mode. It should satisfy: PDNX•256•t

SCYCLE

≥ PDNXA•64•t

SCYCLE+tPDNXB,MAX

It this equation can’t be satisfied, then the max i mum PDNX value should be written, and the t be modified (see Figure 23-4). Do not set this field to zero. Note – only PDNX2..0 are im pl em ented. Note – t

SCYCLE

is t

(SCK cycle time).

CYCLE1

/ tH4 timing window will

S4

Data Sheet E0039N30 (Ver. 3.0)

43

Figure 22-1 Control Registers (5/7)

Control Register : TPARM Address : 04816

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 TCDLY0 TCLS TCAL

Read/write register. Reset value is undefined.

Field Description

TCDLY0

Specifies the t

core parameter in t

CDLY0-C

permitting round trip read delay to al l device to be equalized. This f i el d m ay be written with the values “010” (2•t

TCLS1..0

TCAS1..0

through “101” (5•t Specifies the t

Specifies the t

CLS-C CAS-C

).

CYCLE

core parameter in t

The equations relating the core paramet ers to the datasheet parameters f ol l ow: t t t

CAS-C CLS-C CPS-C

=2•t

CYCLE

=2•t

CYCLE

=1•t

Not programmable

CYCLE

t

OFFP=tCPS-C

=4•t t

RCD=tRCD-C

=t

CYCLE

RCD-C

+ t

+ 1•t

- 1•t

CAS-C

CYCLE

+ t

CLS-C

– t

CLS-C

- 1•t

CYCLE

t

CAC

=3•t

CYCLE

+ t

CLS-C

+ t

CDLY0-C

+ t

(see table below programming ranges)

CDLY1-C

units. This adds a programmable del ay to Q (read data) packets,

CYCLE

units. Should be “10” (2•t

CYCLE

units. This should be “10” (2•t

CYCLE

).

CYCLE

).

CYCLE

µµµµ

PD488588

CYCLE

)

TCDLY0

010 2•t 011 3•t 011 3•t 011 3•t 100 4•t 101 5•t

t

CDLY0-C

000 0•t

CYCLE

000 0•t

CYCLE

001 1•t

CYCLE

010 2•t

CYCLE

010 2•t

CYCLE

010 2•t

CYCLE

TCDLY1

t

CDLY1-C

CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE

t

CAC@tCYCLE

7•t 8•t

9•t 10•t 11•t 12•t

=3.30 ns t

CYCLE CYCLE CYCLE

Control Register : TFRM Address : 04916

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 TFRM3..0

Read/write register. Reset value is undefined.

Field Description

TFRM3..0

Specifies the posit i on of the framing point in t parameter. This is the mini m um offset between a ROW packet (whi ch places a device at ATTN) and the first COL packet (directed to that device) which must be framed. Thi s field may be written with the value “0111” (7•t through “1010” (10•t 4•t

) that is present in an RDRAM i n t he memory system. Thus, if an RDRAM with t

CYCLE

). TFRM is usually set to the value which matches t he l argest t

CYCLE

present, then TFRM would be programmed to 7•t

units. This value mus t be greater than or equal to the t

CYCLE

.

parameter (modulo

RCD,MIN

=11•t

RCD,MIN

CAC@tCYCLE

not allowed

8•t

CYCLE

9•t

CYCLE

10•t

CYCLE

11•t

CYCLE

12•t

CYCLE

FRM,MIN

CYCLE

were

CYCLE

=2.50 ns

)

44

Data Sheet E0039N30 (Ver. 3.0)

Figure 22-1 Control Registers (6/7)

Control Register : TCDLY1 Address : 04a16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 TCDLY1

Read/write register. Reset value is undefined.

Field Description

TCDLY1

Specifies the value of the t packets, permitt i ng round trip read to delay all devices to be equalized. This field may be wri tten with the values “000” (0•t

) through “010” (2•t

CYCLE

core parameter in t

CDLY1-C

). Refer to TPARM Register for more details.

CYCLE

units. This adds a programmable del ay to Q (read data)

Control Register : SKIP Address : 04b16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 AS MSE MS 0 0 0 0 0 0 0 0 0 0

Read/write register (except AS field). Reset value is zero (SIO Reset).

µµµµ

PD488588

Field Description

MS

MSE

AS

Manual skip (MS must be 1 when M SE=1). > During initializat i on, the RDRAMs at the furthest poi nt in the fifth read domain may have selected the AS=0 value, placing them at the closest point in a s i xth read domain. Setting the MSE/MS fields to 1/1 overrides the autoski p value and returns them to the furthest point of the fifth read dom ai n. Manual skip enable (0=auto, 1=manual ).

Autoskip. Read-only val ue determined by autoskip circ ui t and stored when SETF serial comm and i s received by RDRAM during initializati on. In Figure34-1, AS=1 corresponds t o the early Q(a1) packet and AS=0 to the Q(a1) packet one t

later for the four uncertain c ases.

CYCLE

Control Register : TCYCLE Address : 04c16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 TCYCLE13..0

Read/write register. Reset value is undefined.

Field Description

TCYCLE13..0

Specifies the value of the t should be written with the val ue “00027

datasheet parameter in 64ps units. For the t

CYCLE

” (39•64ps).

16

CYCLE,MIN

of 2.50 ns (2500ps), this f i el d

Data Sheet E0039N30 (Ver. 3.0)

45

Figure 22-1 Control Registers (7/7)

Control Register : TEST77 Address : 04d16

µµµµ

PD488588

Control Register : TEST78 Address : 04e16 Control Register : TEST79 Address : 04f16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Read/write register.

Field Description

TEST77 TEST78 TEST79

It must be written wit h zero after SIO reset. These regi sters must only be used f or testing purposes.  Do not read or written after SIO res et . 0 Do not read or written after SIO res et . 0

Reset

value

46

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

23. Power State Management

Table 23-1 summarizes the power states available to a Direct RDRAM. In general, the lowest power states have the longest operational latencies. For example, the relative power levels of PDN state and STBY state have a ratio of about 1:110, and the relative access latencies to get read data have a ratio of about 250:1. PDN state is the lowest power state available. The information in the RDRAM core is usually maintained with selfrefresh; an internal timer automatically refreshes all rows of all banks. PDN has a relatively long exit latency because the TCLK/RCLK block must resynchronize itself to the external clock signal. NAP state is another low-power state in which either self-refresh or REFA-refresh are used to maintain the core. See 24. Refresh for a description of the two refresh mechanisms. NAP has a shorter exit latency than PDN because the TCLK/RCLK block maintains its synchronization state relative to the external clock signal at the time of NAP entry. This imposes a limit (t or ATTN to update this synchronization state.

Power State Description Blocks consuming power Power state Description Blocks consuming power PDN Powerdown state. Self-refresh NAP Nap state. S i m i l ar to

STBY Standby state.

Ready for ROW packets.

ATTNR Attention read state.

Ready for ROW and COL packets. Sending Q (read data) packets.

) on how long an RDRAM may remain in NAP state before briefly returning to STBY

NLIMIT

Table 23-1 Power State Summary

Self-refresh or REFA-refresh TCLK/RCLK-Nap REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ demux receiver Core power

REFA-refresh TCLK/RCLK ROW demux receiver

REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ mux transmitter Core power

PDN except lower wake-up latency.

ATTN Attention state.

Ready for ROW and COL packets.

ATTNW At tention write state.

Ready for ROW and COL packets. Ready for D (write data) packets.

Data Sheet E0039N30 (Ver. 3.0)

47

µµµµ

PD488588

Figure 23-1 summarizes the transition conditions needed for moving between the various power states. Note that NAP and PDN have been divided into two substates (NAP-A/NAP-S and PDN-A/PDN-S) to account for the fact that a NAP or PDN exit may be made to either ATTN or STBY states.

Figure 23-1 Power State Transition Diagram

automatic

ATTNR ATTNW

automatic

ATTN

NLIMIT

t

RLX

NAPR • RLXR

PDEV.CMD•SIO0

NAPR • RLXR

PDEV.CMD•SIO0

NAP-A

NAP

NAP-S

ATTN

PDNR

STBY

NAPR

PDNR • RLXR

PDEV.CMD•SIO0

PDNR • RLXR

PDEV.CMD•SIO0

PDN-A

PDN

PDN-S

SETR/CLRR

Notation: SETR/CLRR - SETR/CLRR Reset sequence in SRQ packet PDNR - PDNR command in ROWR packet NAPR - NAPR command in ROWR packet RLXR - RLX command in ROWR packet RLX - RLX command in ROWR,COLC,COLX packets SIO0 - SIO0 input value PDEV.CMD - (PDEV=DEVID)•(CMD=01) ATTN - ROWA packet(non-broadcast) or ROWR packet (non-broadcast) with ATTN command

At initialization, the SETR/CLRR Reset sequence will put the RDRAM into PDN-S state. The PDN exit sequence involves an optional PDEV specification and bits on the CMD and SIO

IN

pins. Once the RDRAM is in STBY, it will move to the ATTN/ATTNR/ATTNW states when it receives a non-broadcast ROWA packet or non-broadcast ROWR packet with the ATTN command. The RDRAM returns to STBY from these three states when it receives a RLX command. Alternatively, it may enter NAP or PDN state from ATTN or STBY states with a NAPR or PDNR command in an ROWR packet. The PDN or NAP exit sequence involves an optional PDEV specification and bits on the CMD and SIO0 pins. The RDRAM returns to the ATTN or STBY state it was originally in when it first entered NAP or PDN. An RDRAM may only remain in NAP state for a time t

. It must periodically return to ATTN or STBY.

NLIMIT

The NAPRC command causes a napdown operation if the RDRAM’s NCBIT is set. The NCBIT is not directly visible. It is undefined on reset. It is set by a NAPR command to the RDRAM, and it is cleared by an ACT command to the RDRAM. It permits a controller to manage a set of RDRAMs in a mixture of power states. STBY state is the normal idle state of the RDRAM. In this state all banks and sense amps have usually been left precharged and ROWA and ROWR packets on the ROW pins are being monitored. When a non-broadcast ROWA packet or non-broadcast ROWR packet(with the ATTN command) packet addressed to the RDRAM is seen, the RDRAM enters ATTN state (see the right side of Figure 23-2). This requires a time t activates the specified row of the specified bank. A time TFRM•t

after the ROW packet, the RDRAM will be able

CYCLE

during which the RDRAM

SA

to frame COL packets (TFRM is a control register field – see Figure 22-1(5/7) “TFRM Register”). Once in ATTN state, the RDRAM will automatically transition to the ATTNW and ATTNR states as it receives WR and RD commands.

48

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

Once the RDRAM is in ATTN, ATTNW, or ATTNR states, it will remain there until it is explicitly returned to the STBY state with a RLX command. A RLX command may be given in an ROWR, COLC, or COLX packet (see the left side of Figure 23-2). It is usually given after all banks of the RDRAM have been precharged; if other banks are still activated, then the RLX command would probably not be given. If a broadcast ROWA packet or ROWR packet (with the ATTN command) is received, the RDRAM’s power state doesn’t change. If a broadcast ROWR packet with RLXR command is received, the RDRAM goes to STBY.

Figure 23-2 STBY Entry (left) and STBY Exit (right)

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0

DQB8..0

Power

State

T

1

2

3

0

RLXR

RLXC RLXX

ATTN

T

5

6

7

4

t

AS

T

8

9

T

10

STBY

T

13

14

11

15

12

CTM/CFM

..ROW0 COL4

..COL0

DQA8..0

Power

T

17

18

19

16

ROW2

DQB8..0

State

T

21

22

20

T

23

0

T

1

2

ROP a0

t

STBY

T

SA

T

3

T

5

6

7

4

COP a1 XOP a1

TFRM•t

T

9

8

COP a1

CYCLE

T

10

11

COP a1

COP a0 XOP a0

ATTN

T

13

14

15

12

16

ROP=non-broadcast ROWA or ROWR/ATTN

a0={d0, b0, r0} a1={d1, b1, c1}

No COL packets may be placed in the three indicated positions; i.e. at (TFRM-{1,2,3})•t

A COL packet to device d0 (or any other device) is okay at

CYCLE

(TFRM)•t or later.

A COL packet to another device (d1!=d0) is okay at

CYCLE

(TFRM-4)•t or earlier.

CYCLE

.

Figure 23-3 shows the NAP entry sequence (left). NAP state is entered by sending a NAPR command in a ROW packet. A time t clock on CTM/CFM must remain stable for a time t

is required to enter NAP state (this specification is provided for power calculation purposes). The

ASN

after the NAPR command.

CD

Figure 23-3 NAP Entry (left) and PDN Entry (right)

T

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0

DQB8..0

Power

State

Note The(eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry

T

1

2

3

0

ROP a0

(NAPR)

COP a0 XOP a0

ATTN/STBY

T

5

4

restricted

T

t

NPQ

t

T

6

ASN

7

t

Note

T

8

CD

T

9

10

ROP a1

COP a1 XOP a1

T

11

15

12

T

13

14

T

17

18

19

16

CTM/CFM

ROW2

..ROW0

COL4

..COL0

T

21

22

20

T

23

0

T

1

2

ROP a0

(PDNR)

COP a0 XOP a0

T

3

T

5

4

restricted

t

restricted

T

6

NPQ

T

7

8

t

CD

T

9

10

ROP a1

T

13

14

11

12

a0={d0, b0, r0, c0} a1={d1, b1, c1, c1}

No ROW or COL packets directed to device d0 may overlap the restricted interval. No broadcast ROW packets may overlap the quiet interval.

COP a1 XOP a1

ROW or COL packets to a device other than d0 may overlap the restricted interval.

DQA8..0

NAP

DQB8..0

Power

State

t

ASP

ATTN/STBY

Note

ROW or COL packets directed to device d0 after the restricted interval will be ignored.

PDN

The RDRAM may be in ATTN or STBY state when the NAPR command is issued. When NAP state is exited, the RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is specified with NAPR, then the RDRAM will return to STBY state when NAP is exited. Figure 23-3 also shows the PDN entry sequence (right). PDN state is entered by sending a PDNR command in a ROW packet. A time t purposes). The clock on CTM/CFM must remain stable for a time t

is required to enter PDN state (this specification is provided for power calculation

ASP

after the PDNR command.

CD

Data Sheet E0039N30 (Ver. 3.0)

49

µµµµ

PD488588

The RDRAM may be in ATTN or STBY state when the PDNR command is issued. When PDN state is exited, the RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is specified with PDNR, then the RDRAM will return to STBY state when PDN is exited. The current- and slew-ratecontrol levels are re-established.

The RDRAM’s write buffer must be retired with the appropriate COP command before NAP or PDN are entered. Also, all the RDRAM’s banks must be precharged before NAP or PDN are entered. The exception to this is if NAP is entered with the NSR bit of the INIT register cleared(disabling self-refresh in NAP). The commands for relaxing, retiring, and precharging may be given to the RDRAM as late as the ROPa0, COPa0, and XOPa0 packets in Figure 23-3. No broadcast packets nor packets directed to the RDRAM entering NAP or PDN may overlay the quiet window. This window extends for a time t

after the packet with the NAPR or PDNR command.

NPQ

Figure 23-4 shows the NAP and PDN exit sequences. These sequences are virtually identical; the minor differences will be highlighted in the following description.

Before NAP or PDN exit, the CTM/CFM clock must be stable for a time tCE. Then, on a falling and rising edge of SCK, if there is a “01” on the CMD input, NAP or PDN state will be exited. Also, on the falling SCK edge the SIO0 input must be at a 0 for NAP exit and 1 for PDN exit.

If the PSX bit of the INIT register is 0, then a device PDEV5..0 is specified for NAP or PDN exit on the DQA5..0 pins. This value is driven on the rising SCK edge 0.5 or 1.5 SCK cycles after the original falling edge, depending upon the value of the DQS bit of the NAPX register. If the PSX bit of the INIT register is 1, then the RDRAM ignores the PDEV5..0 address packet and exits NAP or PDN when the wake-up sequence is presented on the CMD wire. The

/

ROW and COL pins must be quiet at a time t

t

around the indicated falling SCK edge(timed with the PDNX or

S4

H4

NAPX register fields). After that, ROW and COL packets may be directed to the RDRAM which is now in ATTN or STBY state.

Figure 23-5 shows the constraints for entering and exiting NAP and PDN states. On the left side, an RDRAM exits NAP state at the end of cycle T3. This RDRAM may not re-enter NAP or PDN state for an interval of t enters NAP state at the end of cycle T13. This RDRAM may not re-exit NAP state for an interval of t

. The RDRAM

NU0

. The equations

NU1

for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. NAPX is the value in the NAPX field in the NAPX register.

On the right side of Figure23-4, an RDRAM exits PDN state at the end of cycle T3. This RDRAM may not re-enter PDN or NAP state for an interval of t re-exit PDN state for an interval of t

. The RDRAM enters PDN state at the end of cycle T13. This RDRAM may not

PU0

. The equations for these two parameters depend upon a number of factors,

PU1

and are shown at the bottom of the figure. PDNX is the value in the PDNX field in the PDNX register.

50

Data Sheet E0039N30 (Ver. 3.0)

Figure 23-4 NAP and PDN Exit

µµµµ

PD488588

T

1

0

T

2

T

3

T

5

6

7

4

CTM/CFM

ROW2

..ROW0

If PSX=1 in Init register, then NAP/PDN exit is broadcast (no PDEV field).

COL4

..COL0

DQA8..0 DQB8..0

tS3t

H3

Note 2

PDEV5..0

t

CE

DQS=0

SCK

CMD

SIO0

The packet is repeated

from SIO0 to SIO1

SIO1

Power

State

Notes 1. Use 0 for NAP exit, 1 for PDN exit

2. Device selection timing slot is selected by DQS field of NAPX register

3. The DQS field must be written with “1” for this RDRAM.

4. Exit to STBY or ATTN depends upon whether RLXR was asserted at NAP or PDN entry time

0 1

Note 1

0/1

Note 1

0/1

NAP/PDN

DQS=0

Figure 23-5 NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right)

T

8

T

9

10

tS3t

Note 2

PDEV5..0

Note 2,3

Note 2

T

11

12

H3

DQS=1

T

13

14

15

16

T

17

18

19

20

T

21

22

23

T

24

T

25

T

26

27

T

29

30

31

28

T

33

34

35

32

No ROW packets may overlap the restricted interval

No COL packets may overlap the restricted interval if device PDEV is exiting the NAP-A or PDN-A states

Note 2

Effective hold becomes tH4’ = tH4 +[PDNXA•64•tSCYCLE + tPDNXB,MAX] - [PDNX•256•tSCYCLE] if [PDNX•256•tSCYCLE] < [PDNXA•64•tSCYCLE + tPDNXB,MAX].

(NAPX•t )/(256•PDNX•t )

SCYCLE

STBY/ATTN

Note 2

SCYCLE

Note 4

T

36

ROP

COP XOP

T

37

T

38

T

39

40

restricted

t

S4tH4

restricted

t

S4tH4

T

41

42

T

43

T

45

46

47

44

ROP

COP

XOP

T

0

T

1

T

2

T

5

6

3

4

CTM/CFM

ROW2 ..ROW0

SCK

NAP exit

CMD

t =5•t +(2+NAPX)•t

NU0

t =8•t - (0.5•t )

NU1

=23•t

CYCLE CYCLE

CYCLE

0 1

no entry to NAP or PDN

SCYCLE

T

7

T

8

T

9

T

10

T

11

15

12

T

13

14

T

17

18

19

16

T

21

22

23

20

T

24

T

25

T

26

T

27

3

0

T

1

2

T

5

6

7

4

T

9

10

11

8

T

12

T

13

T

14

T

17

18

15

19

16

CTM/CFM

NAP entry

NAPR

ROW2 ..ROW0

PDN entry

PDNR

SCK

PDN exit

t

NU0

SCYCLE

t

NU1

no exit

if NSR=0 if NSR=1

0 1

CMD

0 1

t

PU0

no entry to NAP or PDN

t =5•t +(2+256•PDNX)•t

PU0

t =8•t - (0.5•t )

PU1

=23•t

CYCLE CYCLE

CYCLE

SCYCLE

t

no exit

SCYCLE

if PSR=0 if PSR=1

PU1

0

Data Sheet E0039N30 (Ver. 3.0)

51

µµµµ

PD488588

24. Refresh

RDRAMs, like any other DRAM technology, use volatile storage cells which must be periodically refreshed. This is accomplished with the REFA command. Figure 24-1 shows an example of this. The REFA command in the transaction is typically a broadcast command (DR4T and DR4F are both set in the ROWR packet), so that in all devices bank number Ba is activated with row number REFR, where REFR is a control register in the RDRAM. When the command is broadcast and ATTN is set, the power state of the RDRAMs (ATTN or STBY) will remain unchanged. The controller increments the bank address Ba for the next REFA command. When Ba is equal to its maximum value, the RDRAM automatically increments REFR for the next REFA command. On average, these REFA commands are sent once every t bits and RBIT are the number of row address bits) so that each row of each bank is refreshed once every t interval. The REFA command is equivalent to an ACT command, in terms of the way that it interacts with other packets (see Table 6-1). In the example, an ACT command is sent after t REFA command. A second ACT command can be sent after a time t

to address c0, the same bank (or an adjacent bank) as the

RC

REFA command. Note that a broadcast REFP command is issued a time t

RAS

the refreshed bank in all RDRAMs. After a bank is given a REFA command, no other core operations(activate or precharge) should be issued to it until it receives a REFP. It is also possible to interleave refresh transactions (not shown). In the figure, the ACT b0 command would be replaced by a REFA b0 command. The b0 address would be broadcast to all devices, and would be {Broadcast, Ba+2,REFR}. Note that the bank address should skip by two to avoid adjacent bank interference. A possible bank incrementing pattern would be: {12, 10, 5, 3, 0, 14, 9, 7, 4, 2, 13, 11, 8, 6, 1, 15, 28, 26, 21, 19, 16, 30, 25, 23, 20, 18, 29, 27, 24, 22, 17, 31}. Every time bank 31 is reached, a REFA command would automatically increment the REFR register. A second refresh mechanism is available for use in PDN and NAP power states. This mechanism is called selfrefresh mode. When the PDN power state is entered, or when NAP power state is entered with the NSR control register bit set, then self-refresh is automatically started for the RDRAM. Self-refresh uses an internal time base reference in the RDRAM. This causes an activate and precharge to be

BBIT+RBIT

carried out once in every t

REF /

2

interval. The REFB and REFR control registers are used to keep track of the bank and row being refreshed. Before a controller places an RDRAM into self-refresh mode, it should perform REFA/REFP refreshes until the bank address is equal to the maximum value. This ensures that no rows are skipped. Likewise, when a controller returns an RDRAM to REFA/REFP refresh, it should start with the minimum bank address value (zero). Figure 24-2 illustrates the requirement imposed by the t

BURST

enabled) power states are exited, the controller must refresh all banks of the RDRAM once during the interval t after the restricted interval on the ROW and COL buses. This will ensure that regardless of the state of self-refresh during PDN or NAP, the t

parameter is met for all banks. During the t

REF, MAX

refreshed in a single burst, or they may be scattered throughout the interval. Note that the first and last banks to be refreshed in the t

interval are numbers 12 and 31, in order to match the example refresh sequence.

BURST

BBIT+RBIT

2

REF /

to address b0, a different (non-adjacent) bank than the

RR

after the initial REFA command in order to precharge

(where BBIT are the number of bank address

REF

parameter. After PDN or NAP (when self-refresh is

BURST

interval, the banks may be

BURST

52

Data Sheet E0039N30 (Ver. 3.0)

Figure 24-1 REFA/REFP Refresh Transaction Example

µµµµ

PD488588

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0

DQB8..0

CTM/CFM

ROW2

..ROW0

COL4

..COL0

DQA8..0 DQB8..0

T

Transaction a: REFA a0 = {Broadcast,Ba,REFR}

T

1

2

3

0

4

REFA a0 ACT c0

T

5

6

7

8

t

RR

T

9

ACT b0

T

10

11

T

12

16

T

13

14

15

T

17

18

19

20

t

RC

T

21

22

23

T

25

24

T

26

T

27

T

29

28

T

30

31

33

32

REFP a1

t

RAS

t

REF

BBIT+RBIT

/2

t

RP

a1 = {Broadcast,Ba} Transaction b: xx b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb} Transaction c: xx c0 = {Dc, ==Ba, Rc}

Transaction d: REFA d0 = {Broadcast,Ba+1,REFR}

T

20

restricted

t

BURST

T

21

22

23

restricted

t

S4tH4

Requirement

T

t

T

24

T

25

T

26

27

T

29

28

T

30

31

33

32

BURST

ROP REFA b12 REFA b31

COP XOP

Figure 24-2 NAP/PDN Exit - t

T

1

2

3

0

4

T

5

6

7

T

8

T

9

10

T

11

T

13

14

15

12

T

17

18

19

16

ROP

COP XOP

t

CE

T

34

35

36

T

37

T

38

T

41

42

39

40

BBIT = #bank address bits RBIT = #row address bits REFB = REFB3..REFB0 REFR = REFR8..REFR0

T

34

35

36

T

37

T

38

T

41

42

39

40

32 bank refresh sequence

T

43

44

REFA d0

T

43

44

T

45

46

47

T

45

46

47

SCK

CMD

SIO0

The packet is repeated

from SIO0 to SIO1

SIO1

Power

State

Notes 1. Use 0 for NAP exit, 1 for PDN exit

2. Device selection timing slot is selected by DQS field of NAPX register

0 1

Note 1

0/1

Note 1

0/1

NAP/PDN

DQS=0

Note 2

DQS=1

Note 2

(NAPX•t )/(256•PDNX•t )

SCYCLE

STBY

SCYCLE

Data Sheet E0039N30 (Ver. 3.0)

53

µµµµ

L

PD488588

25. Current and Temperature Control

Figure 25-1 shows an example of a transaction which performs current control calibration. It is necessary to perform this operation once to every RDRAM in every t proper range. This example uses four COLX packets with a CAL command. These cause the RDRAM to drive four calibration packets Q(a0) a time t

later. An offset of t

CAC

must be placed between the Q(a0) packet and read data Q(a1)

RDTOCC

from the same device. These calibration packets are driven on the DQA4..3 and DQB4..3 wires. The TSQ bit of the INIT register is driven on the DQA5 wire during same interval as the calibration packets. The remaining DQA and DQB wires are not used during these calibration packets. The last COLX packet also contains a SAM command (concatenated with the CAL command). The RDRAM samples the last calibration packet and adjusts its IOL current value. Unlike REF commands, CAL and SAM commands cannot be broadcast. This is because the calibration packets from different devices would interfere. Therefore, a current control transaction must be sent every t is the number of RDRAMs on the Channel. The device field Da of the address a0 in the CAL/SAM command should be incremented after each transaction. Figure 25-2 shows an example of a temperature calibration sequence to the RDRAM. This sequence is broadcast once every t

interval to all the RDRAMs on the Channel. The TCEN and TCAL are ROP commands, and cause

TEMP

the slew rate of the output drivers to adjust for temperature drift. During the quiet interval t calibrated can’t be read, but they can be written.

Figure 25-1 Current Control CAL/SAM Transaction Example

interval in order to keep the IOL output current in its

CCTRL

the devices being

TCQUIET

/N, where N

CTM/CFM

ROW2

..ROW0

COL4

..COL0

DQA8..0

DQB8..0

CTM/CFM

ROW2

..ROW0 COL4

..COL0

DQA8..0

DQB8..0

T

1

2

3

0

Read data from the same device from an earlier RD command must be at this packet position or earier.

CAL a0 CAL a2

Q (a1)

t

READTOCC

Transaction a0: CAL/SAM

Transaction a1: RD

Transaction a2: CAL/SAM

T

5

6

7

4

CAL a0 CAL a0 CAL/SAM a0

t

CAC

T

8

T

9

13

10

11

12

Q (a0)

T

14

15

Read data from a different device from an earlier RD command can be anywhere prior to the Q(a0) packet.

T

17

18

19

16

20

a0 = {Da, Bx} a1 = {Da, Bx} a2 = {Da, Bx}

T

21

22

23

t

CCTRL

T

25

26

27

24

28

Read data from a different device from a later RD command can be anywhere after to the Q(a0) packet.

T

29

30

T

31

32

t

T

33

34

35

CCSAMTOREAD

T

37

36

T

41

38

39

40

Read data from the same device from a later RD command must be at this packet position or later.

T

42

Q (a1)

DQA5 of the first calibrate packet has the inverted TSQ bit of INIT control register; i.e. logic 0 or high voltage means hot temperature.

When used for monitoring, it should be enabled with the DQA3

bit (current control one value) in case there is no RDRAM present:

•

HotTemp = /DQA5

DQA3

Note that DQB3 could be used instead of DQA3.

Figure 25-2 Temperature Calibration (TCEN-TCAL) Transactions to RDRAM

T

0

T

1

T

2

T

5

6

3

4

TCEN

Any ROW packet may be placed in the gap between the ROW packets with the TCEN and TCAL commands.

T

7

t

TCEN

8

TCAL

T

9

10

T

11

t

12

TCAL

T

13

14

15

T

17

16

T

21

18

19

20

t

TCQUIET

No read data from devices

being calibrated

T

22

t

T

23

24

TEMP

T

25

T

26

T

27

31

28

T

29

30

T

33

34

35

32

T

37

36

T

41

38

39

40

T

45

46

43

47

44

T

42

T

45

46

43

47

44

TCEN

CA

54

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

26. Electrical Conditions

Electrical Conditions

Symbol P aram eter and Conditions MIN. MAX. Unit Tj Junction temperature under bias  100 °C V VDD,N,V VDD,N,V V Supply voltage for CMOS pins (1.8V controllers) 1.80 – 0.1 1.80 + 0.2 V V V V V V ADI RSL data asymmetry : A VX RSL c l ock input - crossing point of true and complement signals 1.3 1.8 V VCM RSL clock input - common mode VCM = (V V V V V

Supply voltage 2.50 – 0.13 2.50 + 0.13 V

DD, VDDa

Supply vol tage droop (DC) during NAP interval (t

DDa,N

Supply vol tage ripple (AC) during NAP interval (t

DDa,N

Supply voltage for CMOS pins (2.5V controllers ) 2.50 – 0.13 2.50 + 0.25 V

CMOS

Termination voltage 1.80 – 0.1 1.80 + 0.1 V

TERM

Reference voltage 1.40 – 0.2 1.40 + 0.2 V

REF

RSL data input - low voltage V

DIL

RSL data input - high voltage V

DIH

RSL data input swing : V

DIS

RSL cloc k input swing : V

CIS, CTM

RSL cloc k input swing : V

CIS, CFM

CMOS input low voltage – 0.3 + (V

IL, CMOS

CMOS i nput high voltage V

IH, CMOS

DIS

DI

= V

= [(V

CIS

= V = V

DIH

– V

0.4 1.0 V

DIL

– V

) + (V

REF

+ V

CIH

– V

CIH

(CTM, CTMN pins). 0.35 1.00 V

CIL

– V

(CFM, CFMN pins). 0.225 1.00 V

CIL

) — 2.0 %

NLIMT

) –2.0 +2.0 %

NLIMT

0.5 V

REF –

0.2 V

REF +

– V

)] / V

DIL

REF

) / 2 1.4 1.7 V

CIL

0 –20 %

DIS

/ 2+0.25 V

CMOS

0.2 V

REF –

0.5 V

REF +

/ 2– 0.25) V

CMOS

0.3 V

CMOS +

Data Sheet E0039N30 (Ver. 3.0)

55

µµµµ

PD488588

27. Timing Conditions

Timing Conditions

Symbol Parameter MIN. MAX. Unit Figures t

CTM and CFM cycle times -C60 3.33 3.83 ns

CYCLE

-C71 2.81 3.83

-C80 2.50 3.83 tCR, tCF CTM and CFM input rise and fal l times 0.2 0.5 ns tCH, tCL CTM and CFM hi gh and l ow t i m es 40% 60% t tTR CTM-CFM differential (MSE/MS=0/0) 0.0 1.0 t (MSE/MS=1/1) t

Domain cros sing window –0.1 +0.1 t

DCW

Note1

0.9 1.0

CYCLE

tDR, tDF DQA/DQB/ROW/COL input ri se/fall times 0.2 0.65 ns tS, tH DQA/DQB/ROW/COL-to-CFM t setup/hold time t t t

, t

SI O0, SIO1 input rise and fall tim es — 5.0 ns

DR1

DF1

t

CMD,SCK input rise and fall times — 2.0 ns

DR2, tDF2

t

SCK cycle time - Serial control register transactions 1,000 — ns

CYCLE1

=2.50ns 0.200

CYCLE

=2.81ns 0.240

CYCLE

=3.33ns 0.275

CYCLE

Note4

— ns

Note3,4

—

Note2,4

—

SCK cycle time - Power transitions 10 — ns t

, t

SCK high and low times 4.25 — ns

CH1

CL1

tS1 CMD setup time to SCK rising or fa l l i ng edge tH1 CMD hold t ime to SCK rising or falli ng edge

Note5

1.25 — ns

Note5

1 — ns tS2 SIO0 setup time to SCK fall i ng edge 40 — ns tH2 SIO0 hold time to SCK falling edge 40 — ns tS3 PDEV setup time on DQA5..0 to S CK ri sing edge 0 — ns tH3 PDEV hold time on DQA5..0 to SCK ri sing edge 5.5 — ns tS4 ROW2..0, COL4..0 setup time for quiet window tH4 ROW2.. 0, COL4..0 hold time for quiet window 5 — t V

CMOS i nput low voltage - over / undershoot v ol tage

IL, CMOS

Note6

–1 — t

–0.7 +(V

/2–0.6) V

CMOS

CYCLE

duration is less than or equal t o 5 ns

V

CMOS input high voltage - over / undershoot v ol t age

IH, CMOS

V

/2 + 0.6 V

CMOS

+ 0.7 V

CMOS

duration is less than or equal t o 5ns

t

Quiet on ROW / COL bits during NAP / PDN entry 4 — t

NPQ

t t

Offset between read data and CC packets (same dev i ce) 12 — t

READTOCC

CCSAMTOREAD

Offset between CC packet and read data (same device) 8 — t tCE CTM/CFM stable before NAP/P DN exit 2 — t tCD CTM/ CFM stable after NAP/PDN entry 100 — t t

ROW packet to COL packet ATTN framing delay 7 — t

FRM

t

Maximum time in NAP mode — 10 µs

NLIMIT

t

Refresh interval — 32 ms

REF

t

Current control interval 34 t

CCTRL

t

Temperature control interval — 100 ms

TEMP

t

TCE command to TCAL command 150 — t

TCEN

t

TCAL command to quiet window 2 2 t

TCAL

t

Quiet window (no read data) 140 — t

TCQUIET

t

RDRAM delay (no RSL operations allowed) — 200 µs

PAUSE

t

Interval after PDN or NAP (with self-refresh) exit in which

BURST

100 ms —

CYCLE

— 200 µs

CYCLE

all banks of the RDRAM mus t be refreshed at least once.

Figure 30-1

Figure 30-1 Figure 30-1 Figure 22-1 Figure 30-1 Figure 35-1 Figure 31-1 Figure 31-1

Figure 33-1 Figure 33-1 Figure 33-1 Figure 33-1 Figure 33-1 Figure 33-1 Figure 33-1 Figure 33-1

Figure 33-1 Figure 23-4, 33-2 Figure 23-4, 33-2

Figure 23-4

Figure 23-3

Figure 25-1

Figure 23-4

Figure 23-3

Figure 23-2

Figure 23-1

Figure 24-1

Figure 25-1

Figure 25-2

Figure 22-1

Figure 24-2

56

Data Sheet E0039N30 (Ver. 3.0)

Notes 1. MSE/MS are fields of the SKIP register. For this combination (skip override) the t

effectively 0.0 to 0.0.

2. This parameter also applies to a -C80 or -C71 part when operated with tCYCLE

3. This parameter also applies to a -C80 part when operated with t

4. t

5. With V

6. Effective hold becomes t

if [PDNX • 256 • t

and t

S,MIN

specified t

IL,CMOS

H,MIN

CYCLE

= 0.5 V

for other t

values.

CMOS

SCYCLE

values can be interpolated between or extrapolated from the timings at the 3

CYCLE

− 0.6 V and V

’=t

+ [PDNXA • 64 • t

H4

] < [PDNXA • 64 • t

IH,CMOS

SCYCLE

= 0.5 V

SCYCLE

+ t

+ 0.6 V

CMOS

+ t

PDNXB,MAX

= 2.81ns.

CYCLE

] − [PDNX • 256 • t

]. See Figure 23-4.

= 3.33 ns.

µµµµ

parameter range is

DCW

]

SCYCLE

PD488588

Data Sheet E0039N30 (Ver. 3.0)

57

µµµµ

PD488588

28. Electrical Characteristics

Electrical Characteristics

Symbol P aram eter and Conditions MIN. M AX. Unit

Junction-to-Case thermal resi stance — 0.5 °C/Watt

JC

Θ

I

V

REF

IOH RSL output high current @ (0≤V I

ALL

RSL IOL current resolution step — 2.0 mA

OL

∆I r

Dynamic output impedance 150 — Ω

OUT

I

CMOS input leakage current @ (0

I,CMOS

V

CMOS output low v ol tage @ I

OL,CMOS

V

CMOS output high voltage @ I

OH,CMOS

current @ V

REF

current @ VOL=0.9 V, V

RSL IOL

–10 +10 µA

REF,MAX

) –10 +10 µA

OUT

DD

≤V

Note

, T

DD,MIN

V

I,CMOS

≤

= 1.0 mA — 0.3 V

OL,CMOS

OH,CMOS = –

j,MAX

) –10.0 +10.0 µA

VCMOS

≤

0.25 mA V

30 90 mA

0.3 — V

CMOS –

Note This measurement is made in manual current control mode; i.e. with all output device legs sinking current.

29. Timing Characteristics

Timing Characteristics

Symbol Parameter MIN. MAX. Unit Figure(s) tQ CTM-to-DQA/DQB output time t t t

CYCLE

= 2.50 ns = 2.81 ns

= 3.33 ns

–0.260 –0.300 –0.350

+0.260

Note2,3

Note1,3

Note3

tQR, tQF DQA/DQB output ris e and fall times 0.2 0.45 ns tQ1 SCK-to-SIO0 delay @ C tHR SCK(pos)-to-SIO0 delay @ C t

, t

SIO

QR1

QF1

t

SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C

PROP1

t

NA P exit delay - phase A — 50 ns

NAPXA

t

NA P exit delay - phase B — 40 ns

NAPXB

t

PDN exit del ay - phase A — 4 µs

PDNXA

t

PDN exit del ay - phase B — 9,000 t

PDNXB

rise/fall @ C

OUT

LOAD,MAX =

= 20 pF (SD read packet) — 10 ns

LOAD,MAX

= 20pF (SD read data hold) 2 — ns

LOAD,MAX

20 pF — 5 ns

LOAD,MAX =

20 pF — 10 ns

tAS A TTN-t o-STBY power state delay — 1 t tSA S TBY-to-ATTN power state delay — 0 t t

ATTN/STBY-to-NAP power state delay — 8 t

ASN

t

ATTN/STBY-to-PDN power stat e del ay — 8 t

ASP

Notes 1. This parameter also applies to a -C80 or -C71 part when operated with t

2. This parameter also applies to a -C80 part when operated with t

3. t

and t

Q,MIN

Q,MAX

3 specified tCYCLE

for other t

values.

values can be interpolated between or extrapolated from the timings at the

CYCLE

=2.81 ns.

+0.300

+0.350

=3.33 ns.

Note3

Note2,3

Note1,3

ns

Figure 32-1

CYCLE

Figure 32-1 Figure 34-1 Figure 34-1 Figure 34-1 Figure 34-1 Figure 23-4 Figure 23-4 Figure 23-4 Figure 23-4 Figure 23-2 Figure 23-2 Figure 23-3 Figure 23-3

58

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

30. RSL Clocking

Figure 30-1 is a timing diagram which shows the detailed requirements for the RSL clock signals on the Channel. The CTM and CTMN are differential clock inputs used for transmitting information on the DQA and DQB, outputs. Most timing is measured relative to the points where they cross. The t CTM edge to the falling CTM edge. The tCL and tCH parameters are measured from falling to rising and rising to falling edges of CTM. The tCR and tCF rise-and fall-time parameters are measured at the 20 % and 80 % points. The CFM and CFMN are differential clock outputs used for receiving information on the DQA, DQB, ROW and COL outputs. Most timing is measured relative to the points where they cross. The t falling CFM edge to the falling CFM edge. The tCL and tCH parameters are measured from falling to rising and rising to falling edges of CFM. The tCR and tCF rise- and fall-time parameters are measured at the 20 % and 80 % points. The tTR parameters specifies the phase difference that may be tolerated with respect to the CTM and CFM differential clock inputs (the CTM pair is always earlier).

Figure 30-1 RSL Timing - Clock Signals

t

CYCLE

CTM

t

CL

t

CH

t

CR

VX-

parameter is measured from the falling

CYCLE

parameter is measured from the

CYCLE

t

CR

VCM VX+

V

CIH

80%

50%

CTMN

CFM

CFMN

20% V

t

CF

t

TR

t

CR

t

CF

t

CR

VX-

VCM VX+

CIL

V

CIH

80%

50%

20%

V

t

CL

t

CYCLE

t

CH

CF

CIL

Data Sheet E0039N30 (Ver. 3.0)

59

µµµµ

PD488588

31. RSL - Receive Timing

Figure 31-1 is a timing diagram which shows the detailed requirements for the RSL input signals on the Channel. The DQA, DQB, ROW, and COL signals are inputs which receive information transmitted by a Direct RAC on the Channel. Each signal is sampled twice per t sample points are centered at the 0 % and 50 % points of a cycle, measured relative to the crossing points of the falling CFM clock edge. The set and hold parameters are measured at the V The tDR and tDF rise- and fall-time parameters are measured at the 20 % and 80 % points of the input transition.

Figure 31-1 RSL Timing - Data Signals for Receive

interval. The set/hold window of the sample points is tS/tH. The

CYCLE

voltage point of the input transition.

REF

CFM

CFMN

DQA DQB ROW

COL

V

CIH

V

X-

V

CM

V

X+

80%

50%

20% V

CIL

0.5•t

CYCLE

t

DR

t

S

H

t

S

H

V

DIH

80%

even

odd

V

REF

20% V

t

DF

DIL

60

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

32. RSL - Transmit Timing

Figure 32-1 is a timing diagram which shows the detailed requirements for the RSL output signals on the Channel. The DQA and DQB signals are outputs to transmit information that is received by a Direct RAC on the Channel. Each signal is driven twice per t point of the previous cycle and at the 25 % point of the current cycle. The beginning and end of the odd transmit window is at the 25 % point and at the 75 % point of the current cycle. These transmit points are measured relative to the crossing points of the falling CTM clock edge. The size of the actual transmit window is less than the ideal t

/2, as indicated by the non-zero valued of t

CYCLE

point of the output transition. The tQR and tQF rise- and fall-time parameters are measured at the 20 % and 80 % points of the output transition.

interval. The beginning and end of the even transmit window is at the 75 %

CYCLE

Q,MIN

and t

. The tQ parameters are measured at the 50 % voltage

Q,MAX

Figure 32-1 RSL Timing - Data Signals for Transmit

CTM

CTMN

DQA DQB

VX-

0.75•t

CYCLE

t

QR

V

CIH

80%

VCM

50%

VX+

20% V

CIL

V

QH

t

Q,MAX

0.25•t t

Q,MIN

0.75•t

CYCLE

t

Q,MAX

CYCLE

t

Q,MIN

80%

even

odd

50%

20% V

t

QF

QL

Data Sheet E0039N30 (Ver. 3.0)

61

µµµµ

PD488588

33. CMOS - Receive Timing

Figure 33-1 is a timing diagram which shows the detailed requirements for the CMOS input signals. The CMD and SIO0 signals are inputs which receive information transmitted by a controller (or by another RDRAM’s SIO1 output). SCK is the CMOS clock signal driven by the controller. All signals are high true. The cycle time, high phase time, and low phase time of the SCK clock are t 50 % level. The rise and fall times of SCK, CMD, and SIO0 are t The CMD signal is sampled twice per t

interval, on the rising edge (odd data) and the falling edge (even data).

CYCLE1

DR1

and t

DF1

The set/hold window of the sample points is tS1/tH1. The SCK and CMD timing points are measured at the 50 % level. The SIO0 signal is sampled once per t

interval on the falling edge. The set/hold window of the sample points

CYCLE1

is tS2/tH2. The SCK and SIO0 timing points are measured at the 50 % level.

Figure 33-1 CMOS Timing - Data Signals for Receive

t

DR2

SCK

, t

CYCLE1

CH1

and t

, all measured at the

CL1

, measured at the 20 % and 80 % levels.

V

IH,CMOS

80%

50%

20% V

IL,CMOS

V

IH,CMOS

80%

CMD

t

DF2

t

DR2

t

CH1

t

CYCLE1

t

S1

even

t

CL1

t

H1

t

H1

S1

odd

50%

20% V

IL,CMOS

V

IH,CMOS

80%

t

DR1

SIO0

t

DF2

t

H2

S2

50%

20% V

t

DF1

IL,CMOS

62

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

The SCK clock is also used for sampling data on RSL input in one situation. Figure23-4 shows the PDN and NAP exit sequences. If the PSX field of the INIT register is one (Figure 22-1 control registers (1/7) “INIT Register”), then the PDN and NAP exit sequences are broadcast; i.e. all RDRAMs that are in PDN or NAP will perform the exit sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences are directed; i.e. only one RDRAM that is in PDN or NAP will perform the exit sequence. The address of that RDRAM is specified on the DQA[5:0] bus in the set hold window tS3/tH3 around the rising edge of SCK. This is shown Figure 33-2. The SCK timing point is measured at the 50 % level, and the DQA [5:0] bus signals are measured at the V

REF

level.

Figure 33-2 CMOS Timing - Device Address for NAP or PDN Exit

V

SCK

IH,CMOS

80%

50%

20% V

IL,CMOS

DQA[5:0]

t

S3

PDEV

t

H3

V

DIH

80%

V

REF

20% V

DIL

Data Sheet E0039N30 (Ver. 3.0)

63

µµµµ

PD488588

34. CMOS - Transmit Timing

Figure 34-1 is a timing diagram which shows the detailed requirements for the CMOS output signals. The SIO0 signal is driven once per t and SIO0 timing points are measured at the 50 % level. The rise and fall times of SIO0 are t the 20 % and 80 % levels. Figure34-1 also shows the combinational path connecting SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read data only). The t input must be t are t

QR1

and t

QF1

PROP1

and t

DR1

DF1

, measured at the 20 % and 80 % levels.

SCK

interval on the falling edge. The clock-to-output window is t

CYCLE1

Q1,MIN /tQ1,MAX

and t

QR1

. The SCK

, measured at

QF1

parameter specified this propagation delay. The rise and fall times of SIO0 and SIO1

, measured at the 20 % and 80 % levels. The rise and fall times of SIO0 and SIO1 outputs

Figure 34-1 CMOS Timing - Data Signals for Transmit

V

IH,CMOS

80%

50%

SIO0

or

SIO1

t

Q1,MAX

t

QF1

t

DF1

t

PROP1,MAX

t

HR,MIN

t

PROP1,MIN

t

QR1

DR1

t

QR1

20% V

IL,CMOS

V

OH,CMOS

80%

50%

20% V

OL,CMOS

V

IH,CMOS

80%

50%

20% V

IL,CMOS

64

SIO0

or

SIO1

t

QF1

V

OH,CMOS

80%

50%

20% V

OL,CMOS

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

35. RSL - Domain Crossing Window

When read data is returned by the RDRAM, information must cross from the receive clock domain (CFM) to the transmit clock domain (CTM). The tTR parameter permits the CFM to CTM phase to vary though an entire cycle ; i.e. there is no restriction on the alignment of these two clocks. A second parameter t how the delay between a RD command packet and read data packet varies as a function of the tTR value. Figure 35-1 shows this timing for five distinct values of tTR. Case A (tTR=0) is what has been used throughout this document. The delay between the RD command and read data is t through E), the command to data delay is (t data delay can also be (t value is in the range (t

CYCLE+tDCW,MIN

CAC-tTR-tCYCLE

). This is shown as cases A’ and B’ (the gray packets). Similarly, when the tTR

) to t

CYCLE

). When the tTR value is in the range 0 to t

CAC-tTR

, the command to data delay can also be (t

. As tTR varies from zero to t

CAC

as cases D’ and E’ (the gray packets). The RDRAM will work reliably with either the white or gray packet timing. The delay value is selected at initialization, and remains fixed thereafter.

Figure 35-1 RSL Timing - Crossing Read Domains

is needed in order to describe

DCW

(cases A

CYCLE

, the command to

DCW,MAX

CAC-tTR+tCYCLE

). This is shown

CFM COL

CTM DQA/B DQA/B

CTM DQA/B

DQA/B

CTM DQA/B

DQA/B

•••

t

RDa1

CYCLE

•••

-t t

t

TR

Case A t

Case A' t =0

TR

=0

CAC TR

-t t -t

CAC TR CYCLE

Q(a1)

•••

t

TR

Case B t =t Case B' t =t

TR

DCW,MAX

t -t

CAC TR

t -t -t

CAC TR CYCLE

Q(a1)

•••

t -t

Case C t =0.5•t

t

TR

CYCLE

CAC TR

Q(a1)

•••

t

TR

Case D t =t + t

CYCLE

TR

Case D' t =t + t

TR

CYCLE

DCW,MIN

t -t

CAC TR

-t +t t

CAC

TR

Q(a1)

CYCLE

Q(a1)

CTM DQA/B

DQA/B

t

TR

Case E t =t

Case E' t =t

TR

CYCLE

•••

t-t

CAC TR

t-t+t

CAC TR CYCLE

Data Sheet E0039N30 (Ver. 3.0)

Q(a1)

65

µµµµ

PD488588

36. Timing Parameters

Timing Parameters Summary

Para- Description MIN. MAX. Units Figures meter -C80 -C71 -C60

-45 -45 -53 Row Cycle time of RDRAM banks - the interval between ROWA pac kets

tRC

28 28 28 — t

with ACT commands to the sam e bank. RAS-asserted time of RDRAM bank - the interval between ROWA packet

t

RAS

with ACT command and next ROWR packet with PRER

Note 1

command to the

20 20 20

same bank. Row Precharge time of RDRAM banks - the interval between ROWR packet

tRP

with PRER

Note 1

command and next ROWA packet with ACT command to the

8 8 8 — t

same bank. Precharge-to-precharge time of RDRA M device - the interval between

tPP

successive ROWR packets with PRER

Note 1

commands to any banks of

8 8 8 — t

the same device. RAS-to-RAS time of RDRA M device - the interval between successive

tRR

8 8 8 — t

ROWA packets with ACT com mands to any banks of the sam e device. RAS-to-CAS Delay - the interval from ROWA packet with ACT

t

RCD

9 7 7 — t command to COLC packet wit h RD or WR command. Note - the RASto-CAS delay seen by the RDRAM core (t t

because of differences i n the row and column paths through the

RCD

) is equal to t

RCD-C

RCD-C = 1 +

RDRAM interface. CAS Access delay - the interval from RD command to Q read dat a. The

t

CAC

equation for t CAS Write Delay - interval from WR command to D write data. 6 6 6 6 t

t

CWD

CAS-to-CAS time of RDRAM bank - the interval between s uccessive

tCC

is given in the TPARM regis t er i n Fi gure 22-1(5/7).

CAC

8 8 8 12 t

4 4 4 — t COLC commands.

Length of ROWA, ROWR, COLC, COLM or COLX packet. 4 4 4 4 t

t

PACKET

Interval from COLC packet with WR command to COLC packet which

t

RTR

8 8 8 — t causes retire, and to COLM pac ket with bytemask.

The interval (offset) f rom COLC packet with RDA command, or from

t

OFFP

4 4 4 4 tCYCLE COLC packet with retire com m and (after WRA automatic precharge), or from COLC packet with PREC command, or from COLX packet wi t h PREX command to the equiv al ent ROWR packet with PRER. The equation for t

Interval from last COLC packet with RD command to ROWR pac ket

t

RDP

is given in the TPARM regis t er i n Fi gure 22-1(5/7).

OFFP

4 4 4 — t with PRER.

Interval from last COLC packet with automatic retire command to

t

RTP

4 4 4 — t ROWR packet with PRER.

Note 2

64µs

CYCLE

t

CYCLE

Figure13-1

Figure14-1

Figure13-1

Figure14-1

Figure13-1

Figure14-1

Figure10-3

Figure12-1

Figure13-1

Figure14-1

Figure4-1

Figure4-1 Figure13-1

Figure14-1 Figure2-1 Figure15-1

Figure14-2

Figure13-1

Figure14-1

Notes 1. Or equivalent PREC or PREX command. See Figure 12-2.

2. This is a constraint imposed by the core, and is therefore in units of ms rather than tCYCLE

66

Data Sheet E0039N30 (Ver. 3.0)

.

37. Absolute Maximum Ratings

Absolute Maximum Ratings

µµµµ

PD488588

V

I,ABS

V

DD,ABS

T

STORE

Symbol

,V

DDa,ABS

Voltage applied to any RSL or CMOS pin with respect to GND –0.3 V Voltage on V

and V

DD

Storage temperature –50 +100 °C

Parameter MIN. MAX. Unit

+0.3 V

DD

with respect to GND –0.5 VDD +1.0 V

DDa

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

38. IDD - Supply Current Profile

I

DD - Supply Current Profile

I

value

DD

I

Self-refresh only for INIT.LSR=0  6.0 mA

DD,PDN

I

T/RCLK-Nap  4.2 mA

DD,NAP

I

T/RCLK,ROW-demux 2.50 ns  90 mA

DD,STBY

RDRAM blocks consuming power

@ t

2.81 ns  80

3.33 ns  70

3.83 ns  65 I

T/RCLK, ROW-demux, COL-demux 2.50 ns  135 mA

DD,ATTN

2.81 ns  125

3.33 ns  115

3.83 ns  105 I

T/RCLK, ROW-demux, COL-demux, 2.50 ns  720 mA

DD,ATTN-W

DQ-demux, 1•WR-SenseAmp, 4 •ACT-Bank 2.81 ns  670

3.33 ns  620

3.83 ns  570 I

T/RCLK, ROW-dem ux, COL-demux, 2.50 ns  630 mA

DD,ATTN-R

Note 2

DQ-mux, 1•RD-SenseAmp, 4•ACT-Bank

3.33 ns  520

3.83 ns  470

Note 1

CYCLE

MIN. MAX. Unit

2.81 ns  580

Notes 1. The CMOS interface consumes power in all power states.

2. This does not include the IOL

sink current. The RDRAM diss ipates I

one is driven.

Data Sheet E0039N30 (Ver. 3.0)

in each output driver when a logic

OL•VOL

67

µµµµ

PD488588

39. Capacitance and Inductance

Figure 39-1 shows the equivalent load circuit of the RSL and CMOS pins. The circuit models the load that the device presents to the Channel. This circuit does not include pin coupling effects that are often present in the packaged device. Because coupling effects make the effective single-pin inductance LI, and capacitance CI, a function of neighboring pins, these parameters are intrinsically data-dependent. For purposes of specifying the device electrical loading on the Channel, the effective LI and CI are defined as the worst-case values over all specified operating conditions. LI is defined as the effective pin inductance based on the device pin assignment. Because the pad assignment places each RSL signal adjacent to an AC ground (a GND or VDD pin), the effective inductance must be defined based on this configuration. Therefore, LI assumes a loop with the RSL pin adjacent to an AC ground. CI is defined as the effective pin capacitance based on the device pin assignment. It is the sum of the effective package pin capacitance and the IO pad capacitance.

Figure 39-1 Equivalent Load Circuit for RSL Pins

Pad

L

I

C

I

R

I

L

I

C

I

R

I

L

I,CMOS

C

I

DQA,DQB,RQ Pin

GND Pin

CTM,CTMN, CFM,CFMN Pin

GND Pin

SCK,CMD Pin

68

Pad

C

I,CMOS,SIO

L

I,CMOS

Data Sheet E0039N30 (Ver. 3.0)

GND Pin

SIO0,SIO1 Pin

GND Pin

µµµµ

PD488588

RSL Pin Parasitics

Symbol Parameter and Conditions - RSL pins MIN. M AX. Unit LI RSL effective input i nductance – 4.0 nH L12 Mutual inductance between any DQA or DQB RSL signals. – 0.2 nH Mutual inductance between any ROW or COL RSL signals. – 0.6 nH

Difference in LI value between any RSL pins of a s i ngl e device. – 1.8 nH

I

∆L CI

RSL effective input capacitance

Note

800 MHz 2.0 2.4 pF 711 MHz 2.0 2.4 600 MHz 2.0 2.6 C12 Mutual capacitance between any RSL signals. – 0.1 pF

Difference in CI value between any RSL pins of a s i ngl e device. – 0.06 pF

I

∆C RI RSL effective input resistance 4 15 Ω

Note This value is a combination of the device IO circuitry and package capacitances.

CMOS Pin Parasitics

Symbol Parameter and Conditions - CMOS pins MIN. M AX. Unit L

CMOS effective input induct ance – 8.0 nH

I,CMOS

C

I,CMOS

C

I,CMOS,SIO

CMOS effective input capacitance (SCK,CMD) CMOS effective input capacitance (SIO1,SI O0)

Note

1.7 2.1 pF – 7.0 pF

Note This value is a combination of the device IO circuitry and package capacitances.

Data Sheet E0039N30 (Ver. 3.0)

69

µµµµ

PD488588

40. Interleaved Device Mode

Interleaved Device Mode permits a group of eight RDRAMs on the Channel to collectively respond to acommand.

The purpose of this collective response is to limit the number of bits in each dualoct data packet which are read from

or written to a single RDRAM device. This capability permits a memory controller to implement hardware for fault

detection and correction that can tolerate the complete internal failure of one RDRAM device on a Channel.

The IDM bit of the INIT control register enables this fault tolerant operating mode. When it is set, the RDRAM will

interpret the DR4..0 and DC4..0 fields of the ROW and COLC packets differently. Figure 40-1 shows the differences

using an example system with eight RDRAMs.

The DEVID4..0 registers of these RDRAMs are initial-ized to “00000” through “00111’. However, when the IDM bit is

set, only the upper two bits (DEVID4..3) will be compared to the DR4..3 and DC4..3 fields. This means that ROW and

COLC packets will be executed by groups of eight RDRAMs, with a Channel containing from one to four of these

groups. The low-order DR2..0 bits are not used when IDM is set, and the low-order DC2..0 bits have a modified

function described below.

With IDM set, a directed ACT or PRE command in a ROW packet causes eight RDRAMs to perform the indicated

operation. Likewise, when a RD or WR command is specified in a COLC command, the selected group of eight

RDRAMs responds. When using IDM, devices must be added to the Channel in groups of eight. An application will

typically make the IDM bit setting the same for all RDRAMs on a Channel.

The mechanism for indicating a broadcast ROW packet (DR4F and DR4T are both set to one) is not affected by the

setting of the IDM bit; i.e. IDM mode does not change the broadcast ROW packet mechanism.

Likewise, the COLX fields (DX4..0, XOP4..0, and BX5..0) are not changed by IDM mode - all COLX packets are

directed to a single device.

When the IDM bit is set, COLM packets should not be used (the M bit should be set to zero, selecting only COLX

packets). This is because the mapping of bytes to RDRAM storage cells is changed by IDM mode.

Returning to Figure 40-1, the remaining fields of the ROW and COLC packets are interpreted in the same way

regardless of the setting of the IDM bit – IDM mode does not affect these fields. Specifically, the BR5..0 and BC5..0

fields of the ROW and COLC packets are used to select one of the banks just as when IDM is not set. The R8..0 field

of the ROW packet selects a row of the selected (BR5..0) bank to load into the bank’s sense amp. And the C6..0 field

selects one dualoct of the selected (BC5..0) bank’s sense amp.

The IDM bit affects what is done with this selected dualoct. When IDM is not set, the dualoct is driven onto the

Channel by the single selected RDRAM device. When IDM is set, the RDRAM of the eight device group selected by

DC4..3 drives 16 or 24 bits (x18 device) of the 144-bit dualoct. The bits driven are a function of the DEVID2..0

RDRAM register field, the DC2..0 COLC packet field, and the device width (x18). Figure 40-1 shows the mapping that

is appropriate for DC2..0=000.

Figure 40-2 and Figure 40-3 show the mapping for all eight values of DC2..0. There are eight mappings, which are

rotated among the eight devices using the following equation:

Pin = 7 - 4 • (DEVID2^DC2)

- 2 • (DEVID1^DC1) - 1 • (DEVID0^DC0) (Eq 1)

where “^” is the exclusive-or function. “Pin” is the pin number that is driven by the RDRAM with the DEVID2..0 value.

For example, Pin=0 means the RDRAM drives DQA0 and DQB0, and so forth. The DQA8 pin is always driven with

DQA7, and DQB8 is always driven with DQB6 for x18 devices. For x16 devices, the DQA8 and DQB8 pins are not

used. For each of the eight mappings, the eight-RDRAM group supplies a complete dualoct. As the application steps

through eight values of DC2..0, all the bits of the eight underlying dualocts will be accessed. Thus, an eight-RDRAM

group appears to be a single RDRAM with eight times the normal page size, with the DC2..0 field providing the extra

column addressing informa-tion (beyond what C6..0 provides).

70

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

Figure 40-1 ACT, PRE, RD, and WR Commands for Eight RDRAM System with IDM = 1

RDRAM 0

RDRAM 1 RDRAM 2 RDRAM 3

RDRAM 4

RDRAM 5

RDRAM 6 RDRAM 7

DEVID

4..0

DR4..3 DC4..3

access device

BR5..0 BC5..0

access

bank

R12..0

access

row

C6..0

access column

00000

compare to DEVID4..3

bank array

•

one bank

• •

•

• •

•

• •

PRE

• •

WR

•

ACT

sense amp.

• •

RD

00001

same as device 0

00010 00011

same as device 0

00100

same as device 0

00101

same as device 0

00110

same as device 0

00111

same as device 0

DC2..0

=000

form

dualoct

Channel

DQA7 DQB7 DQA8

DQA6 DQB6 DQB8

DQA0

•

DQA8 DQB0

•

DQB8

CTM/CFM

DQA5 DQB5

•

DQA4 DQB4

•

Data Sheet E0039N30 (Ver. 3.0)

DQA3 DQB3

DQA2 DQB2

DQA1 DQB1

DQA0 DQB0

notation

• •

•

• •

•

• •

one bitdualoct (144 bits)row (2C dualocts)bank (2R rows)device (2B banks)

71

DC2..0

000

Figure 40-2 Mapping from DEVID2..0 and DC2..0 Fields to DQ Packet with IDM = 1

DEVID2..0

000 001 010 011 100 101 110 111

µµµµ

PD488588

Mapping for

previous figure

001

010

DQA7 DQB7 DQA8

DQA6 DQB6 DQB8

DQA5 DQB5

DQA6 DQB6 DQB8

DQA7 DQB7 DQA8

DQA4 DQB4

DQA5 DQB5

DQA4 DQB4

DQA7 DQB7 DQA8

DQA4 DQB4

DQA5 DQB5

DQA6 DQB6 DQB8

DQA3 DQB3

DQA2 DQB2

DQA1 DQB1

DQA2 DQB2

DQA3 DQB3

DQA0 DQB0

DQA1 DQB1

DQA0 DQB0

DQA3 DQB3

DQA0 DQB0

DQA1 DQB1

DQA2 DQB2

CTM/CFM

DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8

72

011

DQA4 DQB4

DQA5 DQB5

DQA6 DQB6 DQB8

DQA7 DQB7 DQA8

DQA0 DQB0

Data Sheet E0039N30 (Ver. 3.0)

DQA1 DQB1

DQA2 DQB2

DQA3 DQB3

DC2..0

100

µµµµ

PD488588

Figure 40-3 Mapping from DEVID2..0 and DC2..0 Fields to DQ Packet with IDM = 1 (continued)

DEVID2..0

000 001 010 011 100 101 110 111

101

110

DQA3 DQB3

DQA2 DQB2

DQA1 DQB1

DQA2 DQB2

DQA3 DQB3

DQA0 DQB0

DQA1 DQB1

DQA0 DQB0

DQA3 DQB3

DQA0 DQB0

DQA1 DQB1

DQA2 DQB2

DQA7 DQB7 DQA8

DQA6 DQB6 DQB8

DQA5 DQB5

DQA6 DQB6 DQB8

DQA7 DQB7 DQA8

DQA4 DQB4

DQA5 DQB5

DQA4 DQB4

DQA7 DQB7 DQA8

DQA4 DQB4

DQA5 DQB5

DQA6 DQB6 DQB8

CTM/CFM

DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8

111

DQA0 DQB0

DQA1 DQB1

DQA2 DQB2

DQA3 DQB3

DQA4 DQB4

Data Sheet E0039N30 (Ver. 3.0)

DQA5 DQB5

DQA6 DQB6 DQB8

DQA7 DQB7 DQA8

73

µµµµ

PD488588

41. Glossary of Terms

ACT Activate command from A V field. D Write data packet on DQ pins. activate To access a roe and place in sense amp. DBL CNFGB register field – doubled-bank . activate To access a row and place i n sense amp. DC Dev i ce address field in COLC packet . adjacent dev ice An RDRAM on a Channel.

ASYM CCA register field for RSL V ATTN Power state – ready for ROW / COL packets . DM Device match for ROW packet decode. ATTNR Power state – transmitt i ng Q packets. Doubled-bank RDRAM with shared sense amp. ATTNW Power state – rec ei ving D packets. DQ DQA and DQB pins. AV Opcode f i el d i n ROW packets. DQA Pins for data byte A. bank DQB Pins for data byte B .

BC Bank address field in CLC pac ket. DR,DR4T,DR4F BBIT CNFGA register field - # bank address bits. broadcast An operation executed by all RDRAMs. dual oct 16 bytes – the smallest addressable datum. BR Bank address field in ROW packets. DX Devi ce address field in COLX packet. bubble f i el d A collection of bits in a packet.

BYT CNFGB regist er f i el d – 9 bi t s per byte. initial i zation BX Bank address field in COLX packet. C Column addres s field in COLC packet. LSR CNFGA regi ster field – low-power self-refresh. CAL Calibrate (I CBIT CNFGB register field - # column address bits. MA Field in COLM packet for mask i ng byte A. CCA Control register – current control A. MB Field in COLM packet for masking byte B. CCB Control register – current control B. MSK Mask command in M field. CFM,CFMN Clock pins for receiv i ng packets. MVER Control register – manufacturer ID. Channel ROW / COL / DQ pi ns and external wires. NAP Power state – needs SCK/CMD wakeup. CLRR Clear reset comm and from SOP field. NAPR Nap command in ROP field. CMD CMOS pins for initiali zation / power control. NAPRC Conditional nap com m and i n ROP field. CNFGA Control register with configuration fields. NAPXA NAPX register field – NAP exit delay A. CNFGB Control register with configuration fields. NAPXB NAPX register field – NAP exit delay B. COL Pins for col um n-access control. NOCOP No-operation c om m and i n COP field. COLC Column operation packet on COL pins. NOROP No-operation command in ROP field. COLM Write mask pac ket on COL pins. NOXOP No-operation command in X OP field. column NS R INI T regi ster field – NAP self-ref resh.

Command A decoded bit-com bi nat i on from a field. PDN Power state – needs SCK/CMD wakeup. COLX Extended operation pac ket on COL pins. PDNR Powerdown command in ROP field. controller PDNXA Control register – PDN exit delay A.

COP Column opcode field in COLC pac ket. pin effici ency The fraction of non-idle cycles on a pin. core The banks and sense amps of an RDRAM. PRE PRE C, PRER, PREX precharge commands . CTM, CTMN Clock pins for transmitting packets. PREC Precharge command in COP field. Current control prec harge Prepares sense amp and bank for activate.

Two RDRAM banks which share s ense amps (also called doubled banks).

/ VOH.

OL

RBIT•2CBIT

A block of 2 of the RDRAM.

Idle cycle(s) on RDRAM pins needed because of a resource const rai nt.

Rows in a bank or activated i n sense amps

CBTI

have 2

A logic-device which drives the ROW / COL / DQ wires for a Channel of RDRAMs .

Periodic operations to update t he proper I Value of RSL output drivers.

dualocts column st orage.

storage cells in the core

) command in XOP field. M Mask opcode field (COLM/COLX pac ket).

OL

DEVID

DQS NAPX register field – PDN/NAP exit.

I NIT Control register wit h i ni tialization fields.

pac ket A collection of bits carried on the Channel.

PDNXB Control register – PDN exit delay B.

P RE R Precharge command in ROP fi eld.

Control register with devic e address that is matched against DR, DC, and DX fields.

Device address field and pac ket framing fields in ROW and ROWE packets.

Configuring a Channel of RDRAMs so t hey are ready to respond to transact i ons.

74

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

PREX Precharge command in XOP field. SETF Set fast clock comm and f rom SOP field. PSX INIT register field – PDN/NAP exit. SETR Set reset command from SOP field. PSR INIT regist er f i el d – P DN self-refresh. SINT PVER CNFGB register field – protocol version. Q Read data packet on DQ pins. SIO0,SIO1 CMOS serial pins for control registers. R Row address field of ROWA packet. SOP Seri al opcode field in SRQ. RBIT CNFGB register field - #row address bi ts. SRD Serial read opcode c o m m and from SOP. RD/RDA Read (/precharge) command in COP field. SRP INIT register field – Serial repeat bit. read Operation of accessing s ense amp data. SRQ receive

Moving information from t he Channel i nto the RDRAM (a serial stream is demuxed).

STBY Power state – ready for ROW packets. REFA Refresh-act ivate command in ROP field. SVER Control register – stepping v ersion. REFB Control register – next bank (self-refresh). SWR Serial write opc ode command from SOP. REFBIT TCAS TCLSCAS register fiel d – t

CNFGA register field – ignore bank bits (for REFA and self-refresh).

TCLS TCLSCAS regi ster field – t REFP Refresh-precharge command in ROP field. TCLSCAS Control register – t REFR Control register – next row for REFA. TCYCLE Control register – t refresh Periodic operations to restore st orage cells. TDAT Control register – t retire TEST77 Control register – for test purposes.

The automatic operation that s tores write buffer into sense amp aft er WR command.

TEST78 Control register – for test purposes. RLX RLXC, RLXR, RLXX relax commands. TRDLY Control register – t RLXC Relax command in COP field. transaction ROW, COL, DQ packets for memory access. RLXR Relax command in ROP field. transmit RLXX Relax c om m and i n XOP field. ROP Row-opcode field in ROWR pack et. WR/WRA Write (/precharge) command in COP field.

CBIT

row 2

dualocts of cells (bank/sense amp). write Operati on of modifying sense amp data. ROW Pins for row-access control XOP Extended opcode field i n COLX packet. ROW ROWA or ROWR packets on ROW pins. ROWA Activate packet on ROW pins. ROWR Row operation packet on ROW pins. RQ Alternate name for ROW/COL pins. RSL Rambus Si gnal l e vels.

) command in XOP field.

SAM Sample (I SA

Serial address packet f or control register transactions w/ SA address field.

OL

SBC Serial broadcast f i el d i n SRQ. SCK CMOS clock pin. SD

Serial data packet for c ont rol register transactions w/ SD dat a field.

SDEV Serial device addres s in SRQ packet. SDEVID INIT register field – Serial devic e ID. self-refresh Refresh mode for PDN and NAP. sense amp Fas t storage that holds copy of bank’s row.

Serial interval packet for control register read/write transactions .

Serial request packet f or control register read/write transactions .

core delay.

CAS

core delay.

CLS CAS CYCLE DAC

RDLY

and t

delay.

CLS

delay.

Moving information from the RDRAM onto the Channel (parallel word is muxed).

Data Sheet E0039N30 (Ver. 3.0)

75

42. Package Drawing

µµµµ

80-ball FBGA (

BGA) (17.16 ×××× 10.2)

E

INDEX MARK

y1 S

A1

µµµµ

PD488588

SB

w

D

SA

w

A

S

ZE2

yS

U T S R P N M L K J H G F E D C B A

b

SE

B

11034 78

φ

eE

ZE1

SABx M

ZD

eD A

SD

ITEM MILLIMETERS

D 17.16±0.10 E 10.2±0.1 w 0.2 A 0.96±0.10

A1 0.40±0.05 eD 0.8 eE 0.8

0.50±0.05b

0.08x

y

0.1

0.2

y1 SD 0.4 SE 1.2 ZD 1.78

ZE1 1.1 ZE2 1.9

ECA-TS2-0051-02

76

Data Sheet E0039N30 (Ver. 3.0)

43. Recommended Soldering Conditions

Please consult our sales office for soldering conditions of the

Type of Surface Mount Device

PD488588.

µ

µµµµ

PD488588

PD488588FF-DH1 : 80-ball FBGA (

µ

BGA) (17.16 × 10.2)

µ

Data Sheet E0039N30 (Ver. 3.0)

77

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V

DD

or GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

µµµµ

PD488588

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.

CME0107

78

Data Sheet E0039N30 (Ver. 3.0)

µµµµ

PD488588

µµµµ

BGA is a registered trademark of Tessera, Inc.

Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc.

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc.

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Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.

M01E0107