Datasheet PCM3002E, PCM3002E-2K, PCM3003E, PCM3003E-2K Datasheet (Burr Brown)

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Page 1

PCM3003

PCM3002

For most current data sheet and other product

information, visit www.burr-brown.com

PCM3003

16-/20-Bit Single-Ended Analog Input/Output

STEREO AUDIO CODECs

FEATURES

● MONOLITHIC 20-BIT ∆Σ ADC AND DAC

● 16-/20-BIT INPUT/OUTPUT DATA

● SOFTWARE CONTROL: PCM3002

● HARDWARE CONTROL: PCM3003

● STEREO ADC:

Single-Ended Voltage Input 64X Oversampling High Performance

THD+N: –86dB SNR: 90dB Dynamic Range: 90dB

● STEREO DAC:

Single-Ended Voltage Output Analog Low Pass Filter 64X Oversampling High Performance

THD+N: –86dB SNR: 94dB Dynamic Range: 94dB

● SPECIAL FEATURES

Digital De-emphasis Digital Attenuation (256 Steps) Soft Mute Digital Loop Back Power Down: ADC/DAC Independent

● SAMPLING RATE: Up to 48kHz

● SYSTEM CLOCK: 256fS, 384fS, 512f

● SINGLE +3V POWER SUPPLY

● SMALL PACKAGE: SSOP-24

DESCRIPTION

The PCM3002 and PCM3003 are low cost single chip stereo audio CODECs (analog-to-digital and digital-toanalog converters) with single-ended analog voltage input and output.

The ADCs and DACs employ delta-sigma modulation with 64X oversampling. The ADCs include a digital decimation filter, and the DACs include an 8X oversampling digital interpolation filter. The DACs also include digital attenuation, de-emphasis, infinite zero detection and soft mute to form a complete subsystem. PCM3002 and PCM3003 operate with left-justified, and right-justified formats, while the PCM3002 also supports the I2S data format.

PCM3002 and PCM3003 provide a power-down mode that operates on the ADCs and DACs independently.

Fabricated on a highly advanced CMOS process, PCM3002 and PCM3003 are suitable for a wide variety of cost-sensitive consumer applications where good performance is required.

PCM3002’s programmable functions are controlled by software and the PCM3003’s functions include deemphasis, power down, and audio data format selections, which are controlled by hardware.

Lch In

Rch In

Lch Out

Rch Out

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

Analog Front-End

Low Pass Filter

and

Output Buffer

Delta-Sigma

Modulator

Multi-Level

Delta-Sigma

Modulator

Digital

Decimation

Filter

Digital

Interpolation

Filter

Serial Interface

and

Mode Control

Digital Out

Digital In

Serial Mode Control System Clock

1 PCM3002/3003

Page 2

SPECIFICATIONS

All specifications at +25°C, VDD = V

PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUT/OUTPUT

Input Logic

Input Logic Level: V

Input Logic Current: I Input Logic Current: I

(1, 2, 3)

(2)

(1)

Output Logic

Output Logic Level: V

(5)

(4)

CLOCK FREQUENCY

Sampling Frequency (f

) 32

System Clock Frequency 256f

ADC CHARACTERISTICS RESOLUTION 20 Bits DC ACCURACY

Gain Mismatch Channel-to-Channel ±1.0 ±3.0 % of FSR Gain Error ±2.0 ±5.0 % of FSR Gain Drift ±20 ppm of FSR/°C Bipolar Zero Error High-Pass Filter Disabled Bipolar Zero Drift High-Pass Filter Disabled

DYNAMIC PERFORMANCE

THD+N: VIN = –0.5dB –86 –80 dB

VIN = –60dB –28 dB Dynamic Range A-Weighted 86 90 dB Signal-to-Noise Ratio A-Weighted 86 90 dB Channel Separation 84 88 dB

DIGITAL FILTER PERFORMANCE

Passband 0.454f Stopband 0.583f Passband Ripple ±0.05 dB Stopband Attenuation –65 dB Delay Time 17.4/f HPF Frequency Response –3dB 0.019f

ANALOG INPUT

Voltage Range 0.60 V Center Voltage 0.50 V Input Impedance 30 kΩ Anti-Aliasing Filter Frequency Response –3dB 150 kHz

NOTES: (1) Pins 7, 8, 17 and 18: RST, ML, MD, MC for the PCM3002; PDAD, PDDA, DEM1, DEM0 for PCM3003 (Schmitt-Trigger input with 100kΩ typical internal pull-down resistor). (2) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt Trigger input). (3) Pin16: 20BIT for PCM3003 (Schmitt-Trigger input, 100kΩ typical internal pull-down resistor). (4) Pin 12: DOUT. (5) Pin 16: ZFLG (open drain output). (6) High Pass Filter for Offset Cancel. (7) Refer to Application Bulletin AB-148 for information relating to operation at lower sampling frequencies. (8) f HPF used for performance calculation. (9) f (10) Applies for voltages between 2.4V to 2.7V for 0°C to +70°C and 256f

= 3.0V, fS = 44.1kHz, SYSCLK = 384fS, and 16-bit data, unless otherwise noted.

0.7 x V

= –1mA V

OUT

= +1mA 0.3 VDC

OUT

= +1mA 0.3 VDC

OUT

384f

512f

(6) (6)

(8)

= 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz

= 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation.

OUT

/512fS operation (384fS not available). (11) SYSCLK, BCKIN, and LRCIN are stopped.

8.1920 11.2896 12.2880 MHz

12.2880 16.9344 18.4320 MHz

16.3840 22.5792 24.5760 MHz

PCM3002E/3003E

0.3 x V

VDC VDC

±1 µA

100 µA

–0.3 VDC

(7)

44.1 48 kHz

±1.7 % of FSR

±20 ppm of FSR/°C

CC CC

Hz Hz

sec

mHz

Vp-p

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

PCM3002/3003

Page 3

SPECIFICATIONS

All specifications at +25°C, VDD = V

PARAMETER CONDITIONS MIN TYP MAX UNITS DAC CHARACTERISTICS

RESOLUTION 20 Bits DC ACCURACY

Gain Mismatch Channel-to-Channel ±1.0 ±3 % of FSR Gain Error ±1.0 ±5 % of FSR Gain Drift ±20 ppm of FSR/°C Bipolar Zero Error ±1.0 % of FSR Bipolar Zero Drift ±20 ppm of FSR/°C

DYNAMIC PERFORMANCE

THD+N: V

Dynamic Range EIAJ, A-Weighted 88 94 dB Signal-to-Noise Ratio EIAJ, A-Weighted 88 94 dB Channel Separation 86 91 dB

DIGITAL FILTER PERFORMANCE

Passband 0.445f Stopband 0.555f Passband Ripple ±0.17 dB Stopband Attenuation –35 dB Delay Time 11.1/f

ANALOG OUTPUT

Voltage Range 0.60 x V Center Voltage 0.5 x V Load Impedance AC-Coupling 10 kΩ

LPF Frequency Response f = 20kHz –0.16 dB

POWER SUPPLY REQUIREMENTS

Voltage Range: V

Supply Current: Operation V

Power Dissipation: Operation V

TEMPERATURE RANGE

Operation –25 +85 °C Storage –55 +125 °C Thermal Resistance,

= 0dB (Full Scale) –86 –80 dB

OUT

= –60dB –28 dB

OUT

, V

Power-Down V

Power-Down

= 3.0V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 18-bit data, unless otherwise noted.

PCM3002E/3003E

(9)

(11)

–25°C to +85°C 2.7 3.0 3.6 VDC

0° C to +70°C

= VDD = 3.0V 18 24 mA

= VDD = 3.0V 50 µA

= VDD = 3.0V 54 72 mW

VCC = VDD = 3.0V 150 µW

(10)

2.4 3.0 3.6 VDC

100 °C/W

Hz Hz

sec

Vp-p VDC

PACKAGE/ORDERING INFORMATION

PACKAGE SPECIFIED

PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER

PCM3002E SSOP-24 338 –25°C to +85°C PCM3002E PCM3002E Rails

" " " " " PCM3002E/2K Tape and Reel

PCM3003E SSOP-24 338 –25°C to +85°C PCM3003E PCM3003E Rails

" " " " " PCM3003E/2K Tape and Reel

NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM3002E/2K” will get a single 2000-piece Tape and Reel.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage

, +VCC1, +VCC2 ...................................................................... +6.5V

Supply Voltage Differences............................................................... ±0.1V

GND Voltage Differences.................................................................. ±0.1V

Digital Input Voltage...................................................... –0.3 to V

Analog Input Voltage......................................... –0.3 to V

Power Dissipation .......................................................................... 300mW

Input Current ................................................................................... ±10mA

Operating Temperature Range ......................................... –25°C to +85°C

Storage Temperature...................................................... –55°C to +125°C

Lead Temperature (soldering, 5s).................................................. +260°C

(reflow, 10s)..................................................... +235°C

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

ELECTROSTATIC DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small

CC1, VCC

+ 0.3V

2 + 0.3V

(1)

MEDIA

parametric changes could cause the device not to meet its published specifications.

3 PCM3002/3003

Page 4

VCC1 V

REF

L PDAD PDDA SYSCLK LRCIN BCKIN DOUT

2 AGND1 AGND2

COM

OUT

DEM0 DEM1

20BIT

DIN V

DGND

1 2 3 4 5 6 7 8

9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

PCM3003

PIN CONFIGURATION—PCM3002 PIN CONFIGURATION—PCM3003

Top View SSOP

PCM3002

1 2 3 4 5 6 7 8

9 10 11 12

VCC1 V

REF

RST ML SYSCLK LRCIN BCKIN DOUT

AGND1 AGND2

COM

OUT

MC MD

ZFLG

DIN V

DGND

23 22 21 20

18 17 16 15 14

Top View SSOP

PIN ASSIGNMENTS—PCM3002

PIN NAME I/O DESCRIPTION

1V 2V 3V 4V 5V 6VINL IN ADC Analog Input, Lch 7 RST IN Reset, Active LOW 8 ML IN Strobe Pulse for Mode Control 9 SYSCLK IN System Clock Input 10 LRCIN IN Sample Rate Clock Input (fS) 11 BCKIN IN Bit Clock Input 12 DOUT OUT Data Output 13 DGND — Digital Ground 14 V 15 DIN IN Data Input 16 ZFLG OUT Zero Flag Output, Active LOW 17 MD IN Serial Data for Mode Control 18 MC IN Bit Clock for Mode Control 19 V 20 V 21 V 22 AGND2 — DAC Analog Ground 23 AGND1 — ADC Analog Ground 24 V

NOTES: (1) With 100kΩ typical internal pull-down resistor. (2) Schmitt-Trigger input. (3) Open drain output.

1 — ADC Analog Power Supply

R IN ADC Analog Input, Rch

L — ADC Reference, Lch

REF

R — ADC Reference, Rch

REF

— Digital Power Supply

L OUT DAC Analog Output, Lch

OUT

R OUT DAC Analog Output, Rch

OUT

— ADC/DAC Common

COM

2 — DAC Analog Power Supply

PCM3002/3003

(1, 2)

(2)

(1, 2)

(2)

(1, 2)

(3)

PIN ASSIGNMENTS—PCM3003

PIN NAME I/O DESCRIPTION

1V 2V 3V 4V 5V

1 — ADC Analog Power Supply

R IN ADC Analog Input, Rch

L — ADC Reference, Lch

REF

R — ADC Reference, Rch

REF

6VINL IN ADC Analog Input, Lch 7 PDAD IN ADC Power Down, Active LOW 8 PDDA IN DAC Power Down, Active LOW 9 SYSCLK IN System Clock Input

(2)

10 LRCIN IN Sample Rate Clock Input (fS) 11 BCKIN IN Bit Clock Input

(2)

(1, 2) (1, 2)

(2)

12 DOUT OUT Data Output 13 DGND — Digital Ground 14 V

— Digital Power Supply

15 DIN IN Data Input 16 20BIT IN 20-Bit Format Select 17 DEM1 IN De-emphasis Control 18 DEM0 IN De-emphasis Control 0 19 V 20 V 21 V

L OUT DAC Analog Output, Lch

OUT

R OUT DAC Analog Output, Rch

OUT

— ADC/DAC Common

COM

(1, 2)

22 AGND2 — DAC Analog Ground 23 AGND1 — ADC Analog Ground 24 V

2 — DAC Analog Power Supply

NOTE: (1) With 100kΩ typical internal pull-down resistor. (2) Schmitt-Trigger input.

Page 5

TYPICAL PERFORMANCE CURVES ADC SECTION

At TA = +25°C, V

= V

= 3.0V, fS = 44.1kHz, f

= 384fS, and F

SYSCLK

= 1kHz, unless otherwise noted.

SIGNAL

0.010

0.008

0.006

THD+N at –0.5dB (%)

0.004

0.002 –25 0 25 50 75 85 100

0.010

0.008

0.006

THD+N vs TEMPERATURE

–60dB

0.5dB

Temperature (°C)

THD+N vs SUPPLY VOLTAGE

–60dB

5.0

4.0

2.0

THD+N at –60dB (%)

3.0

1.0

5.0

4.0

3.0

Dynamic Range (dB)

DYNAMIC RANGE and SNR vs TEMPERATURE

Dynamic Range

SNR

–25 0 25 50 75 85 100

Temperature (°C)

DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE

Dynamic Range

SNR

5.0

4.0

2.0

SNR (dB)

3.0

1.0

SNR (dB)

0.004

THD+N at –0.50dB (%)

0.002

0.010

0.008

0.006

THD+N at –0.5dB (%)

0.004

0.002

2.4 2.7 3.0 3.3 3.6

–60dB

–0.5dB

Supply Voltage

THD+N vs SAMPLING FREQUENCY

32 44.1 48

(kHz)

(V)

THD+N at –60dB (%)

2.0

1.0

5.0

4.0

3.0

THD+N at –60dB (%)

2.0

1.0

Dynamic Range (dB)

2.4 2.7 3.0 3.3 3.6 Supply Voltage

DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY

Dynamic Range

SNR

32 44.1 48

(kHz)

(V)

SNR (dB)

5 PCM3002/3003

Page 6

TYPICAL PERFORMANCE CURVES DAC SECTION

At TA = +25°C, V

= V

= 3.0V, fS = 44.1kHz, f

= 384fS, and F

SYSCLK

= 1kHz, unless otherwise noted.

SIGNAL

0.010

THD+N vs TEMPERATURE

0.008

–60dB

0.006

THD+N at FS (%)

0.004

0.002 –25 0 25 50 75 85 100

0dB

Temperature (°C)

THD+N vs SUPPLY VOLTAGE

0.010

0.008

–60dB

0.006

THD+N at FS (%)

0.004

0dB

4.0

3.0

2.0

THD+N at –60dB (%)

1.0

4.0

3.0

2.0

THD+N at –60dB (%)

1.0

DYNAMIC RANGE and SNR vs TEMPERATURE

Dynamic Range

SNR

Dynamic Range (dB)

–25 0 25 50 75 85 100

Temperature (°C)

DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE

Dynamic Range

SNR

Dynamic Range (dB)

SNR (dB)

0.002

0.010

0.008

0.006

THD+N at FS (%)

0.004

0.002

2.4 2.7 3.0 3.3 3.6 Supply Voltage

(V)

THD+N vs SAMPLING FREQUENCY

and SYSTEM CLOCK

–60dB

0dB

32 44.1 48

(kHz)

384f

256fS, 512f

384f

256fS, 512f

2.4 2.7 3.0 3.3 3.6 Supply Voltage

(V)

DYNAMIC RANGE and SNR

vs SAMPLING FREQUENCY and SYSTEM CLOCK

4.0

3.0

2.0

THD+N at –60dB (%)

1.0

SNR

Dynamic

Range

Dynamic Range (dB)

256fS, 512f

384f

32 44.1 48

(kHz)

SNR (dB)

PCM3002/3003

Page 7

OUTPUT SPECTRUM (–60dB, N = 8192)

Frequency (kHz)

Amplitude (dB)

–20

–40

–60

–80

–100

–120

–140

51015 2520 220

TYPICAL PERFORMANCE CURVES

THD+N vs SIGNAL LEVEL

Signal Level (dB)

THD+N (%)

100

0.1

0.001

0.001 –72–84–96 –60 –48 –36 –12–24 0

Output Spectrum

At TA = +25°C, V

DACs ADCs

= V

= 3.0V, fS = 44.1kHz, f

OUTPUT SPECTRUM (0dB, N = 8192)

= 384fS, and F

SYSCLK

= 1kHz, unless otherwise noted.

SIGNAL

OUTPUT SPECTRUM (0dB, N = 8192)

–20

–40

–60

–80

Amplitude (dB)

–100

–120

–140

–20

–40

–60

–80

Amplitude (dB)

–100

51015 2522200

Frequency (kHz)

OUTPUT SPECTRUM (–60dB, N = 8192)

–20

–40

–60

–80

Amplitude (dB)

–100

–120

–140

51015 2522200

Frequency (kHz)

–120

–140

51015 2520 220

Frequency (kHz)

THD+N vs SIGNAL LEVEL

100

0.1

THD+N (%)

0.001

0.001 –72–84–96 –60 –48 –36 –12–24 0

Signal Level (dB)

7 PCM3002/3003

Page 8

TYPICAL PERFORMANCE CURVES Supply Current

At TA = +25°C, V

= V

= 3.0V, fS = 44.1kHz, f

= 384fS, DIN = BPZ, and VIN = BPZ, unless otherwise noted.

SYSCLK

(mA)

+ I

ADC & DAC

ADC

DAC

Power Down & OFF

ICC + IDD vs TEMPERATURE

–25–50 –0 25 50 75 100

Temperature (°C)

ICC + IDD vs SAMPLING FREQUENCY

ADC & DAC

(mA)

+ I

2.5

2.0

1.5

1.0

(mA)

+ I

Power Down and OFF (mA)

DD:

0.5

+ I

512f

256f

ADC & DAC

ADC

DAC

Power Down & OFF

+ IDD vs SUPPLY VOLTAGE

2.4 2.7 3.0 3.3 3.6 Supply Voltage (V)

2.5

2.0

1.5

1.0

Power Down and OFF (mA)

DD:

0.5

+ I

32 44.1 48

(kHz)

PCM3002/3003

Page 9

TYPICAL PERFORMANCE CURVES

HIGH PASS FILTER RESPONSE

Normalized Frequency (x f

/1000 Hz)

Amplitude (dB)

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

12340

TRANSITION BAND CHARACTERISTICS

Normalized Frequency (x f

Hz)

Amplitude (dB)

0 –1 –2 –3 –4 –5 –6 –7 –8 –9

–10

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55

–4.13dB at 0.5 x f

At TA = +25°C, V

ADC DIGITAL FILTER

= V

= 3.0V, fS = 44.1kHz, and f

= 384fS, unless otherwise noted.

SYSCLK

–50

–100

Amplitude (dB)

–150

–200

0.2

0.0

–0.2

–0.4

OVERALL CHARACTERISTICS

81624320

Normalized Frequency (x f

Hz)

PASSBAND RIPPLE CHARACTERISTICS

0 –10 –20 –30 –40 –50 –60

Amplitude (dB)

–70 –80 –90

–100

STOPBAND ATTENUATION CHARACTERISTICS

0.2 0.4 0.6 0.8 1.00 Normalized Frequency (x f

Hz)

Amplitude (dB)

–0.6

–0.8

–1.0

0.1 0.2 0.3 0.4 0.50 Normalized Frequency (x f

HIGH PASS FILTER RESPONSE

0 –10 –20 –30 –40 –50 –60

Amplitude (dB)

–70 –80 –90

–100

0.1 0.2 0.3 0.4 0.50 Normalized Frequency (x f

Hz)

/1000 Hz)

9 PCM3002/3003

Page 10

TYPICAL PERFORMANCE CURVES

At TA = +25°C, V

ANTI-ALIASING FILTER

= V

= 3.0V, fS = 44.1kHz, and f

= 384fS, unless otherwise noted.

SYSCLK

–10

–20

–30

Amplitude (dB)

–40

–50

ANTI-ALIASING FILTER OVERALL

FREQUENCY RESPONSE

10 100 1k 10k 100k 1M 10M0

Frequency (Hz)

0.2

0.0

–0.2

–0.4

–0.6

Amplitude (dB)

–0.8

–1.0

ANTI-ALIASING FILTER PASSBAND

FREQUENCY RESPONSE

10 100 1k 10k 100k0

Frequency (Hz)

PCM3002/3003

Page 11

DE-EMPHASIS ERROR (32kHz)

0 3628 7256 10884 14512

0 4999.8375 9999.675 14999.5125 19999.35

0 5442 10884 16326 21768

Frequency (Hz)

0.6

0.4

0.2 0

–0.2 –0.4 –0.6

0.6

0.4

0.2 0

–0.2 –0.4 –0.6

0.6

0.4

0.2 0

–0.2 –0.4 –0.6

DE-EMPHASIS ERROR (44.1kHz)

Frequency (Hz)

DE-EMPHASIS ERROR (48kHz)

Frequency (Hz)

Error (dB) Error (dB) Error (dB)

TYPICAL PERFORMANCE CURVES

At TA = +25°C, V

DAC DIGITAL FILTER

= V

= 3.0V, fS = 44.1kHz, and f

= 384fS, unless otherwise noted.

SYSCLK

OVERALL FREQUENCY CHARACTERISTICS

–20

–40

Level (dB)

–60

–80

–100

0 50k 100k 150k

DE-EMPHASIS FREQUENCY RESPONSE (32kHz)

0 –2 –4 –6 –8

–10 –12

0 5k 10k 15k 20k 25k

DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)

0 –2 –4 –6 –8

–10 –12

0 5k 10k 15k 20k 25k

= 44.1kHz)

Frequency (Hz)

PASSBAND RIPPLE CHARACTERISTICS (fS = 44.1kHz)

–0.2

–0.4

Level (dB)

–0.6

–0.8

–1.0

0 5k 10k 15k 20k

Frequency (Hz)

DE-EMPHASIS FREQUENCY RESPONSE (48kHz)

0 –2 –4 –6 –8

Level (dB) Level (dB) Level (dB)

–10 –12

0 5k 10k 15k 20k 25k

Frequency (Hz)

INTERNAL ANALOG FILTER FREQUENCY RESPONSE

–20

–40

Level (dB)

–60

–80

–100

10 100 1k 10k 100k 1M 10M

(10Hz~10MHz)

Frequency (Hz)

0.15

0.10

0.05

Level (dB)

–0.05

–0.10

–0.15

INTERNAL ANALOG FILTER FREQUENCY RESPONSE

10 100 1k 10k 100k

(1Hz~20kHz)

Frequency (Hz)

11 PCM3002/3003

Page 12

BLOCK DIAGRAM

Analog

REF

COM

REF

Front-End

Circuit

Reference

Analog

Front-End

Circuit

Analog

OUT

Low-Pass

Filter

Analog

OUT

Low-Pass

Filter

(+)

(–)

(+)

Delta-Sigma

Modulator

Delta-Sigma

Modulator

Multi-Level

Delta-Sigma

Modulator

Multi-Level

Delta-Sigma

Modulator

Power Supply

Decimation

High Pass Filter

ADC

Decimation

High Pass Filter

Interpolation

8X Oversampling

DAC

Interpolation

8X Oversampling

and

Filter

Clock

Serial Data

Interface

Mode

Control

Interface

Reset and

Power Down

Zero Detect

LRCIN

BCKIN

DIN

DOUT

(1 )

(1)

/DEM0

/DEM1

(2)

/PDAD

(2)

(1 )

ML 20BIT

PDDA RST

(1)

AGND2 VCC2 AGND1 VCC1

DGND V

SYSCLK ZFLG

(1)

NOTES: (1) MC, MD, ML, RST, and ZFLG are for PCM3002 only. (2) DEM0, DEM1, 20BIT, PDAD, and PDDA are for PCM3003 only.

1.0µF

VINR

30kΩ

(+)

(–)

Delta-Sigma

Modulator

4.7µF

COM

REF

4.7µF +

REF

4.7µF

FIGURE 1. Analog Front-End (Single-Channel).

PCM3002/3003

Page 13

PCM AUDIO INTERFACE

The four-wire digital audio interface for PCM3002/3003 is comprised of: LRCIN (pin 10), BCKIN (pin 11), DIN (pin

15), and DOUT (pin 12). The PCM3002 may be used with any of the four input/output data formats (Formats 0 - 3), while the PCM3003 may only be used with selected input/ output formats (Formats 0 - 1). For the PCM3002, these formats are selected through PROGRAM REGISTER 3 in

FORMAT 0: PCM3002/3003

DAC: 16-Bit, MSB-First, Right-Justified

the software mode. For the PCM3003, data formats are selected by the 20BIT input (pin 16). Figures 2, 3 and 4 illustrate audio data input/output formats and timing.

The PCM3002/3003 can accept 32-, 48-, or 64-bit clocks (BCKIN) in one clock of LRCIN. Only 16-bit data formats can be selected when 32-bit clocks/LRCIN are applied.

LRCIN

BCKIN

DIN

ADC: 16-Bit, MSB-First, Left-Justified

LRCIN

BCKIN

DOUT

123 14 15 16 123 14 15 16 1

MSB LSB

FORMAT 1: PCM3002/3003

DAC: 20-Bit, MSB-First, Right-Justified

LRCIN

BCKIN

DIN

ADC: 20-Bit, MSB-First, Left-Justified

LRCIN

L–ch R–ch

116 2 3 14 15 16 123 14 15 16

MSB

L–ch R–ch

120 2 3 18 19 20 123 18 19 20

MSB

L–ch R–ch

LSB

MSB LSB

BCKIN

DOUT

123

MSB

FORMAT 2: PCM3002 Only

DAC: 20-Bit, MSB-First, Left-Justified

LRCIN

BCIN

DIN

ADC: 20-Bit, MSB-First, Left-Justified

LRCIN

BCIN

DOUT

123 18 19 20 123 18 19 20

MSB

123 18 19 20 123 18 19 20

MSB

FIGURE 2. Audio Data Input/Output Format.

18 19 20 123

LSB

L–ch R–ch

LSB

L–ch R–ch

LSB

MSB

MSB LSB

13 PCM3002/3003

18 19 20

LSB

Page 14

FORMAT 3: PCM3002 Only

DAC: 20-Bit, MSB-First, I2S

LRCIN

BCKIN

DIN

123 18 19 20 123 18 19 20

MSB

ADC: 20-Bit, MSB-First, I

LRCIN

BCKIN

DOUT

123 18 19 20 123 18 19 20

MSB

FIGURE 3. Audio Data Input/Output Format.

LRCIN

BCH

L-ch

BCL

R-ch

LSB

MSB LSB

R-ch

LSB

LRP

MSB LSB

0.5V

BCKIN

BCY

DIN

BDO

DOUT

BCKIN Pulse Cycle Time t BCKIN Pulse Width High t BCKIN Pulse Width Low t BCKIN Rising Edge to LRCIN Edge t LRCIN Edge to BCKIN Rising Edge t LRCIN Pulse Width t DIN Set-up Time t DIN Hold Time t DOUT Delay Time to BCKIN Falling Edge t DOUT Delay Time to LRCIN Edge t Rising Time of All Signals t Falling Time of All Signals t

0.5V

DIH

DIS

0.5V

LDO

0.5V

300ns (min)

BCY

120ns (min)

BCH

120ns (min)

BCL

40ns (min)

LB LRPtBCY DIS DIH

BDO LDO RISE FALL

(min) 40ns (min) 40ns (min) 40ns (max) 40ns (max) 20ns (max) 20ns (max)

FIGURE 4. Audio Data Input/Output Timing.

PCM3002/3003

Page 15

SYSTEM CLOCK

The system clock for PCM3002/3003 must be either 256fS, 384fS or 512fS, where fS is the audio sampling frequency. The system clock should be provided at the SYSCLK input (pin 9).

The PCM3002/3003 also has a system clock detection circuit which automatically senses if the system clock is operating at 256fS, 384fS, or 512fS. When 384fS or 512fS system clock is used, the clock is divided into 256fS automatically. The 256f clock is used to operate the digital filters and the delta-sigma modulators.

Table I lists the relationship of typical sampling frequencies and system clock frequencies, while Figure 5 illustrates the system clock timing.

SAMPLING RATE FREQUENCY SYSTEM CLOCK FREQUENCY

TABLE I. System Clock Frequencies.

(kHz) (MHz)

256f

32 8.1920 12.2880 16.3840

44.1 11.2896 16.9340 22.5792 48 12.2880 18.4320 24.5760

SYSCLK

384f

"H"

"L"

512f

SCKH

POWER-ON RESET

Both the PCM3002 and PCM3003 have internal power-on reset circuitry. Power-on reset occurs when system clock (SYSCLK) is active and VDD > 2.2V. For the PCM3003, the SYSCLK must complete a minimum of 3 complete cycles prior to VDD > 2.2V to ensure proper reset operation. The initialization sequence requires 1024 SYSCLK cycles for completion, as shown in Figure 6. Figure 8 shows the state

of the DAC and ADC outputs during and after the reset sequence.

EXTERNAL RESET

The PCM3002 includes a reset input, RST (pin 7), while the PCM3003 utilizes both PDAD (pin 7) and PDDA (pin 8) for external reset control. As shown in Figure 7, the external reset signal must drive RST or PDAD/PDDA low for a minimum of 40 nanoseconds while SYSCLK is active in order to initiate the reset sequence. Initialization starts on the rising edge of RST or PDAD/PDDA, and requires 1024 SYSCLK cycles for completion. Figure 8 shows the state of the DAC and ADC outputs during and after the reset sequence.

0.7V

0.3V

System Clock Pulse Width High t System Clock Pulse Width Low t

FIGURE 5. System Clock Timing.

2.4V

2.2V

2.0V

Internal Reset

SYSCLK

FIGURE 6. Internal Power-On Reset Timing.

RST

PDAD and PDDA

Internal Reset

SCKL

1024 System Clock Periods

1/256fS,1/384fS,or 1/512f

Reset

RST

SCKH

SCKL

= 40ns minimum

Reset

12ns (min) 12ns (min)

Reset Removal

SYSCLK

FIGURE 7. External Forced Reset Timing.

1024 System Clock Periods

15 PCM3002/3003

Page 16

SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM

The PCM3002/3003 operates with LRCIN synchronized to the system clock. PCM3002/3003 does not require any specific phase relationship between LRCIN and the system clock, but there must be synchronization. If the synchronization between the system clock and LRCIN changes more than 6 bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the DAC will stop within 1/fS, and the analog output will be forced to bipolar zero (0.5VCC) until the system clock is resynchronized to LRCIN followed by t

DACDLY2

delay time. Internal operation of the ADC will also stop within 1/fS, and the digital output codes will be set to bipolar zero until re-

Reset Removal or Power Down OFF

Internal Reset

or Power Down

DAC V

OUT

Reset

Power Down

GND

DACDLY1

synchronization occurs followed by t

ADCDLY2

delay time. If LRCIN is synchronized with 5 or less bit clocks to the system clock, operation will be normal. Figure 9 illustrates the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero (<1/fS seconds), the outputs are not defined and some noise may occur. During the transitions between normal data and undefined states, the output has discontinuities, which will cause output noise.

ZERO FLAG OUTPUT: PCM3002 ONLY

Pin 16 is an open-drain output, used as the infinite zero detection flag on the PCM3002 only. When input data is continuously zero for 65,536 BCKIN cycles, ZFLG is LOW, otherwise, ZFLG is in a high-impedance state.

Ready/Operation

(16384/fS)

COM

(0.5VCC)

(18436/fS)

ADCDLY1

ADC DOUT

NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR with 200ms time constant) appears initially.

Zero Zero Normal Data

FIGURE 8. DAC Output and ADC Output for Reset and Power Down.

Synchronization

State of

Synchronization

DAC V

OUT

Lost

Synchronous Asynchronous

within

1/f

Undefined Data

Normal

Undefined Data

Resynchronization

COM

(= 1/2 x VCC)

DACDLY2

ADCDLY2

Synchronous

(32/fS)

Normal

(1)

ADC DOUT

NOTES: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR with 200ms time constant) appears initially.

Normal

Zero

FIGURE 9. DAC Output and ADC Output for Loss of Synchronization.

PCM3002/3003

Normal

(1 )

Page 17

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

FIGURE 10. Control Data Input Format.

MC Pulse Cycle Time t MC Pulse Width LOW t MC Pulse Width HIGH t MD Setup Time t MD Hold Time t ML Low Level Time t ML High Level Time t ML Setup Time t ML Hold Time t

SYSCLK: 1/256fS or 1/384fS or 1/512f

MCHtMCL

MCY

MDS

MDH

100ns (min)

MCY

40ns (min)

MCL

40ns (min)

MCH

40ns (min)

MDS

40ns (min)

MDH

40ns + 1SYSCLK (min)

MLL

40ns + 1SYSCLK (min)

MLH

40ns (min)

MLS

40ns (min)

MLH

LSB

MLH

MLS

MLL

FIGURE 11. Control Data Input Timing.

FUNCTION ADC/DAC PCM3002 PCM3003

Audio Data Format ADC/DAC 4 Selectable Formats 2 Selectable Formats LRCIN Polarity ADC/DAC O X

Loop-Back Control ADC/DAC O X Left Channel Attenuation DAC O X Right Channel Attenuation DAC O X Attenuation Control DAC O X Infinite Zero Detection DAC O X DAC Output Control DAC O X Soft Mute Control DAC O X

De-Emphasis (OFF, 32kHz, 44.1kHz, 48kHz) DAC O O ADC Power-Down Control ADC O O DAC Power-Down Control DAC O O High Pass Filter Operation ADC O X

TABLE II. Selectable Functions (O = User Selectable; X = Not Available).

OPERATIONAL CONTROL

PCM3002 can be controlled in a software mode with a three-wire serial interface on MC (pin 18), MD (pin 17), and ML (pin 8). Table II indicates selectable functions, and

Figure 10 and 11 illustrate the control data input format and timing. PCM3003 only allows for control of 16-/20-bit data format, digital de-emphasis, and Power-Down Control by hardware pins.

17 PCM3002/3003

Page 18

MAPPING OF PROGRAM REGISTERS

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0

res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

res res res res res A1 A0 PDAD BYPS PDDA ATC IZD OUT DEM1 DEM0 MUT

res res res res res A1 A0 res res res LOP res FMT1 FMT0 LRP res

SOFTWARE CONTROL (PCM3002)

PCM3002’s special functions are controlled using four program registers which are 16 bits long. There are four distinct registers, with bits 9 and 10 determining which register is in use. Table III describes the functions of the four registers.

NAME NAME DESCRIPTION

res Reserved, should be set to “0”

LDL DAC Attenuation Data Load Control for Lch

AL (7:0) Attenuation Data for Lch

res Reserved, should be set to “0”

LDR

AR (7:0) DAC Attenuation for Rch

res Reserved, should be set to “0” PDAD ADC Power-Down Control PDDA DAC Power-Down Control BYPS ADC High-Pass Filter Operation Control

ATC DAC Attenuation Data Mode Control

IZD DAC Infinite Zero Detection Circuit Control

OUT DAC Output Enable Control

DEM (1:0) DAC De-emphasis Control

MUT Lch and Rch Soft Mute Control

res Reserved, should be set to “0”

LOP ADC/DAC Analog Loop-Back Control

FMT (1:0) ADC/DAC Audio Data Format Selection

LRP ADC/DAC Polarity of LR-clock Selection

DAC Attenuation Data Load Control for Rch

TABLE III. Functions of the Registers.

PROGRAM REGISTER 0

A (1:0): Bit 10, 9 Register Address

These bits define the address for REGISTER 0:

A1 A0

0 0 Register 0

res: Bit 11 : 15 Reserved

These bits are reserved and should be set to “0”.

LDL: Bit 8 DAC Attenuation Data Load Control for

Left Channel

new attenuation data will be ignored, and the output level will remain at the previous attenuation level. The LDR bit in REGISTER 1 has the equivalent function as LDL. When either LDL or LDR is set to “1”, the output level of the left and right channels are simultaneously controlled.

AL (7:0): Bit 7:0

DAC Attenuation Data for Left Channel

AL7 and AL0 are MSB and LSB, respectively. The attenuation level (ATT) is given by:

ATT = 20 x log10 (ATT data/255) (dB)

AL (7:0) ATTENUATION LEVEL

00h –∞dB (Mute) 01h –48.16dB

:: FEh –0.07dB FFh 0dB (default)

PROGRAM REGISTER 1

A (1:0): Register Address

These bits define the address for REGISTER 1:

A1 A0

0 1 Register 1

res: Bit 15:11 Reserved

These bits are reserved and should be set to “0”

LDR: Bit 8 DAC Attenuation Data Load Control for

Right Channel

This bit is used to simultaneously set analog outputs of the left and right channels. The output level is controlled by AL (7:0) attenuation data when this bit is set to “1”. When set to “0”, the new attenuation data will be ignored, and the output level will remain at the previous attenuation level. The LDL bit in REGISTER 0 has the equivalent function as LDR. When either LDL or LDR is set to “1”, the output level of the left and right channels are simultaneously controlled.

AR (7:0): Bit 7:0 DAC Attenuation Data for Left

Channel

AR7 and AR0 are MSB and LSB respectively. See REGISTER 0 for the attenuation formula.

PCM3002/3003

Page 19

PROGRAM REGISTER 2

A (1:0): Bit 10, 9 Register Address

These bits define the address for REGISTER 2:

A1 A0

1 0 Register 2

res: Bit 15:11, 6 Reserved

These bits are reserved and should be set to “0”.

PDAD: Bit 8 ADC Power-Down Control

This bit places the ADC section in the lowest power consumption mode. The ADC operation is stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC Power-down mode enable. Figure 8 illustrates the ADC DOUT response for ADC power-down ON/ OFF. This does not affect the DAC operation.

PDAD DAC POWER-DOWN

0 Power Down Mode Disabled (default) 1 Power Down Mode Enabled

IZD: Bit 4 DAC Infinite Zero Detection Circuit

Control

This bit enables the Infinite Zero Detection Circuit in PCM3002. When enabled, this circuit will disconnect the analog output amplifier from the deltasigma DAC when the input is continuously zero for 65,536 consecutive cycles of BCKIN.

IZD

0 Infinite Zero Detection Disabled (default) 1 Infinite Zero Detection Enabled

OUT: Bit 3 DAC Output Enable Control

When set to “1”, the outputs are forced to VCC/2 (bipolar zero). In this case, all registers in PCM3002 hold the present data. Therefore, when set to “0”, the outputs return to the previous programmed state.

OUT

0 1 DAC Outputs Disabled (forced to BPZ)

DAC Outputs Enabled (default normal operation)

BYPS: Bit 7 ADC High-Pass Filter Bypass Control

This bit enables or disables the high-pass filter for the ADC.

BYPS

0 High-Pass Filter Enabled (default) 1 High-Pass Filter Disabled (bypassed)

PDDA: Bit 6 DAC Power-Down Control

This bit places the DAC section in the lowest power consumption mode. The DAC operation is stopped by cutting the supply current to the DAC section and V

is fixed to GND during DAC Power-

OUT

Down Mode enable. Figure 8 illustrates the DAC V

response for DAC Power-Down ON/OFF.

OUT

This does not affect the ADC operation.

PDDA

0 Power-Down Mode Disabled (default) 1 Power-Down Mode Enabled

ATC: Bit 5 DAC Attenuation Channel Control

When set to “1”, the REGISTER 0 attenuation data can be used for both DAC channels. In this case, the REGISTER 1 attenuation data is ignored.

ATC

Individual Channel Attenuation Data Control (default)

1 Common Channel Attenuation Data Control

DEM (1:0):Bit 2,1

DAC De-emphasis Control

These bits select the de-emphasis mode as shown below:

DEM1 DEM0

0 0 De-emphasis 44.1kHz ON 0 1 De-emphasis OFF (default) 1 0 De-emphasis 48kHz ON

1 1 De-emphasis 32kHz ON

MUT: Bit 0 DAC Soft Mute Control

When set to “1”, both left and right-channel DAC outputs are muted at the same time. This muting is done by attenuating the data in the digital filter, so there is no audible click noise when soft mute is turned on.

MUT

0 Mute Disable (default) 1 Mute Enable

PROGRAM REGISTER 3

A (1:0): Bit 10:9 Register Address

These bits define the address for REGISTER 3:

A1 A0

1 1 Register 3

res: Bit 15:11, 8:6, 4:0 Reserved

These bits are reserved, and should be set to “0”.

19 PCM3002/3003

Page 20

LOP: Bit 5 ADC to DAC Loop-Back Control

When this bit is set to “1”, the ADC’s audio data is sent directly to the DAC. The data format will default to I2S. In Format 3 (I2S Frame), Loopback is not supported.

LOP

0 Loop-back Disable (default) 1 Loop-back Enable

LRP: Bit 1 Polarity of LRCIN Applies only to

Formats 0 through 2.

LRP

0 1 Left-channel is “L”, Right-channel is “H”.

Left-channel is “H”, Right-channel is “L”. (default)

FMT (1,0)

Bit 3:2 Audio Data Format Select These bits determine the input and output audio

data formats.

FMT1 FMT0 DAC ADC

0 0 16-bit, MSB-first, 16-bit, MSB-first,

0 1 20-bit, MSB-first, 20-bit, MSB-first, Format 1

1 0 20-bit, MSB-first, 20-bit, MSB-first, Format 2

1 1 20-bit, MSB-first, 20-bit, MSB-first, Format 3

Rch In

Lch In

Audio

Interface

Data Format Data Format NAME

Format 0 (default)

Right-justified Left-justified

Left-justified Left-justified

0.1µF

and 10µF

1µF

4.7µF

1µF

SYSCLK

L/R CLK BIT CLK

DATA OUT

PCM3002/3003

(1)

VCC1

(2)

4 5 6 7 8

9 10 11 12

REF

RST/PDAD ML/PDDA SYSCLK LRCIN BCKIN DOUT

DATA IN

AGND1 AGND2

COM

OUT

MC/DEM0

MD/DEM1

ZFLG/20BIT

DIN

DGND

+3V Analog V

0.1µF and 10µF

(1)

23 22 21 20

19 18 17 16 15 14

4.7µF +

(4)

4.7µF +

(4)

Rch Out

Lch Out

(6)

/DEM0

(6)

/DEM1

ZFLG

(5)

(6)

/20BIT

(5)

(7)

10kΩ

Control

Interface

0.1µF and

(1)

10µF

(6)

/PDDA

(6)

/PDAD

(7)

ML RST

NOTES: (1) 0.1µF ceramic and 10µF tantalum, typical, depending on power supply quality and pattern layout. (2) 4.7µF typical, gives settling time with 30ms (4.7µF x 6.4kΩ) time constant in Power ON and Power-Down OFF period. (3) 1µF typical, gives 5.3Hz cut-off frequency of input HPF in normal operation and gives settling time with 30ms (1µF x 30kΩ) time constant in Power ON and Power -Down OFF period. (4) 4.7µF typical, gives 3.4Hz cut-off frequency of output HPF in normal operation and gives settling time with 47ms (4.7µF x 10kΩ) time constant in Power ON and Power-Down OFF period. (5) Post low pass filter with R of system performance. (6) MC, MD, ML, ZFLG, RST and 10kΩ pull-up resistor are for the PCM3002. (7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.

FIGURE 12. Typical Connection Diagram for PCM3002/3003.

PCM3002/3003

>10kΩ, depending on requirement

Page 21

PCM3003 DATA FORMAT CONTROL

PCM3003 has hardware functional control using PDAD (pin

7) and PDDA (pin 8) for Power-Down Control; DEM0 (pin

18) and DEM1 (pin 17) for de-emphasis; and 20BIT (pin 16) for 16-/20-bit format selection.

Power-Down Control (Pin 7 and Pin 8)

Both the ADC’s and DAC’s Power-Down Control pins place the ADC or DAC section in the lowest power consumption mode. The ADC/DAC operation is stopped by cutting the supply current to the ADC/DAC section. DOUT is fixed to zero during ADC Power-Down Mode enable and V

is fixed to GND during DAC Power-Down Mode

OUT

enable. Figure 8 illustrates the ADC and DAC output response for Power-Down ON/OFF.

PDAD PDDA POWER DOWN

Low Low Reset (ADC/DAC Power-Down Enable)

Low High ADC Power-Down/DAC Operates High Low ADC Operates/DAC Power-Down High High ADC and DAC Normal Operation

De-Emphasis Control (Pin 17 and Pin 18)

DEM0 (pin 18) and DEM1 (pin 17) are used as de-emphasis control pins.

DEM1 DEM0 DE-EMPHASIS

Low Low De-Emphasis Enabled for 44.1kHz

Low High De-Emphasis Disabled High Low De-Emphasis Enabled for 48kHz High High De-Emphasis Enabled for 32kHz

GROUNDING

In order to optimize the dynamic performance of PCM3002/ 3003, the analog and digital grounds are not connected internally. The PCM3002/3003 performance is optimized with a single ground plane for all returns. It is recommended to tie all PCM3002/3003 ground pins with low impedance connections to the analog ground plane. PCM3002/3003 should reside entirely over this plane to avoid coupling high frequency digital switching noise into the analog ground plane.

VOLTAGE INPUT PINS

A tantalum or aluminum electrolytic capacitor, between 1µF and 10µF, is recommended as an AC-coupling capacitor at the inputs. Combined with the 30kΩ characteristic input impedance, a 1.0µF coupling capacitor will establish a 5.3Hz cut-off frequency for blocking DC. The input voltage range can be increased by adding a series resistor on the analog input line. This series resistor, when combined with the 30kΩ input impedance, creates a voltage divider and enables larger input ranges.

INPUTS

REF

A 4.7µF to 10µF tantalum capacitor is recommended between V

REF

L, V

R, and AGND to ensure low source

REF

impedance for the ADC’s references. These capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the ADC reference.

20BIT Audio Data Selection (Pin 16)

20BIT FORMAT

Low ADC: 16-bit MSB-first, Left-justified

DAC: 16-bit MSB-first, Right-justified

High ADC: 20-bit MSB-first, Left-justified

DAC: 20-bit MSB-first, Right-justified

APPLICATION AND LAYOUT CONSIDERATIONS

POWER SUPPLY BYPASSING

The digital and analog power supply lines to PCM3002/ 3003 should be bypassed to the corresponding ground pins with both 0.1µF ceramic and 10µF tantalum capacitors as close to the device pins as possible. Although PCM3002/ 3003 has three power supply lines to optimize dynamic performance, the use of one common power supply is generally recommended to avoid unexpected latch-up or pop noise due to power supply sequencing problems. If separate power supplies are used, back-to-back diodes are recommended to avoid latch-up problems.

INPUTS

COM

A 4.7µF to 10µF tantalum capacitor is recommended between V

and AGND to ensure low source impedance of

COM

the ADC and DAC common voltage. This capacitor should be located as close as possible to the V

pin to reduce

COM

dynamic errors on the DC common mode voltage.

SYSTEM CLOCK

The quality of the system clock can influence dynamic performance of both the ADC and DAC in the PCM3002/

3003. The duty cycle and jitter at the system clock input pin must be carefully managed. When power is supplied to the part, the system clock, bit clock (BCKIN) and a word clock (LCRIN) should also be supplied simultaneously. Failure to supply the audio clocks will result in a power dissipation increase of up to three times normal dissipation and may degrade long term reliability if the maximum power dissipation limit is exceeded.

21 PCM3002/3003

Page 22

EXTERNAL MUTE CONTROL

For Power-Down ON/OFF control without click noise which is generated by DAC output DC level change, an external mute control is recommended. The control sequence, which is external mute ON, CODEC Power-Down ON, SYSCLK stop and resume if necessary, CODEC Power-down OFF, and external mute OFF is recommended.

THEORY OF OPERATION

ADC SECTION

The PCM3002/3003 ADC consists of two reference circuits, a stereo single-to-differential converter, a fully differential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The Block Diagram in this data sheet illustrates the architecture of the ADC section, Figure 1 shows the single-to-differential converter, and Figure 13 illustrates the architecture of the 5th-order delta-sigma modulator and transfer functions.

An internal reference circuit with three external capacitors provides all reference voltages which are required by the ADC, which defines the full scale range for the converter. The internal single-to-differential voltage converter saves the space and extra parts needed for external circuitry required by many delta-sigma converters. The internal fulldifferential signal processing architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at 64X oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying anti-alias filtering requirements. The 5th-order

delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator and a feedback loop consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels.

The 64fS one-bit data stream from the modulator is converted to 1fS 18-bit data words by the decimation filter, which also acts as a low pass filter to remove the shaped quantization noise. The DC components are removed by a high pass filter function contained within the decimation filter.

THEORY OF OPERATION

DAC SECTION

The delta-sigma DAC section of PCM3002/3003 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level delta-sigma format. A block diagram of the 5-level deltasigma modulator is shown in Figure 14. This 5-level deltasigma modulator has the advantage of improved stability and reduced clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8X interpolation filter is 64fS for a 256fS system clock. The theoretical quantization noise performance of the 5-level deltasigma modulator is shown in Figure 15.

Analog In

X(z)

+ –

1st SW-CAP

Integrator

1-Bit

DAC

–

2nd SW-CAP

Integrator

3rd SW-CAP

Integrator

Y(z) = STF(z) • X(z) + NTF(z) • Qn(z) Signal Transfer Function Noise Transfer Function

FIGURE 13. Simplified 5th-Order Delta-Sigma Modulator.

PCM3002/3003

H(z)

–

4th SW-CAP

Integrator

STF(z) = H(z)/[1 + H(z)] NTF(z) = 1/[1 + H(z)]

5th SW-CAP

Integrator

Qn(z)

Digital Out

Y(z)

Comparator

Page 23

18-Bit

–

–1

–

Out

64f

(256fS)

FIGURE 14. 5-Level Delta-Sigma Modulator Block Diagram.

0 –10 –20 –30 –40 –50 –60 –70 –80 –90

Gain (–dB)

–100 –110 –120 –130 –140 –150

0 5 10 15 20 25 30

3rd ORDER ∆Σ MODULATOR

Frequency (kHz)

5-level Quantizer

4 3 2 1 0

FIGURE 15. Quantization Noise Spectrum.

23 PCM3002/3003

Datasheet PCM3002E, PCM3002E-2K, PCM3003E, PCM3003E-2K Datasheet (Burr Brown)

Specifications and Main Features

Frequently Asked Questions

User Manual