Page 1
INTEGRATED CIRCUITS
PCK2020
CK00 (100/133MHz) spread spectrum
differential system clock generator
Product specification
Supersedes data of 2000 Jul 25
2000 Nov 13
Page 2
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
FEA TURES
•3.3 V operation
•Four differential CPU clock pairs
•Ten PCI clocks at 3.3 V
•Four 66 MHz clocks at 3.3 V
•Two 48 MHz clocks at 3.3 V
•Two 14.318 MHz reference clocks
•100 or 133 MHz operation
•Power management control pins
•CPU clock skew less than 200 ps cycle-to-cycle
•CPU clock skew less than 150 ps pin-to-pin
•1.5 ns to 3.5 ns delay on PCI pins
•Spread Spectrum capability
DESCRIPTION
The PCK2020 is a clock synthesizer/driver for a Pentium III and
other similar processors.
The PCK2020 has four differential pair CPU current source outputs,
two Mref clock outputs running at 1/2 the CPU clock frequency
depending on the state of SEL133/100 pin and four 3V66 clocks
running at 66 MHz. There are ten PCI clock outputs running at
33 MHz and two 48 MHz clocks. Finally, there are two 3.3 V
reference clocks at 14.318 MHz. All clock outputs meet Intel’s drive
strength, rise/fall times, jitter, accuracy, and skew requirements.
The part possesses a dedicated power-down input pin for power
management control. This input is synchronized on-chip and
ensures glitch-free output transitions.
PIN CONFIGURATION
1
Ref0/MultSel0
Ref1/MultSel1
V
DD
XTAL_IN
XTAL_OUT
PCICLK0
PCICLK1
V
DD
PCICLK2
PCICLK4
PCICLK5
V
DD
PCICLK6
PCICLK7
PCICLK9
V
DD
SEL100/133
48MHz0/SelA
2
3
3.3Ref
4
5
6
V
7
PCI
SS
8
9
10
3.3PCI
11
12 45
13
14
15
16
3.3PCI
17
18 39
19 38
VSSPCI
20
21
22
3.3PCI
23
24
USB
V
SS
25 32
26 31 3V66_248MHz1/SelB
27 30 3V66_3VDD3.3USB
28 29PWRDWN VDD3.3
PCK2020
V
56VSSRef
3.3M
DD
55
3VMref
54
3VMref_b
M
53
V
SS
SPREAD
52
51
CPUCLK0
50
CPUCLK0
V
3.3CPU
49
DD
48
CPUCLK1
47
CPUCLK1
46
VSSCPU
CPUCLK2PCICLK3
44VSSPCI
CPUCLK2
V
3.3CPU
43
DD
42
CPUCLK3
CPUCLK3
41
40
VSSCPU
I_REF
V
3.3Core
DD
37PCICLK8
Core
V
SS
36
V
3.3
DD
35
3V66_0
34
3V66_1
33
V
SS
V
SS
SW00577
ORDERING INFORMA TION
PACKAGES TEMPERATURE RANGE (°C) ORDER CODE DRAWING NUMBER
56-Pin Plastic SSOP 0 to +70 PCK2020 DL SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
2000 Nov 13 853-2209 25006
2
Page 3
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 VSSRef
2, 3
4 VDD3.3Ref
5 XTAL_IN Crystal input
6 XTAL_OUT Crystal output
7, 13, 19 VSSPCI
8, 9, 11, 12, 14, 15, 17,
18, 20, 21
10, 16, 22 VDD3.3PCI
23 SEL100/133 Select input pin for enabling 133 MHz or 100 MHz CPU outputs.
24 VSSUSB
25, 26
27 VDD3.3USB
28 PWRDWN Device enters power down mode when held low. Asserts low.
29, 36 VDD3.3
30, 31, 34, 35 3V66[0–3] 3.3 V fixed 66 MHz CPU clock outputs.
32, 33 V
37 VSSCore
38 VDD3.3Core 3.3 V power supply for analog circuits.
39 I_REF
40, 46 VSSCPU
41, 44, 47, 50 CPUCLK[0–3]
42, 45, 48, 51 CPUCLK[0–3]
43, 49 VDD3.3CPU
52 SPREAD
53 VSSM
54 3VMref_b
55 3VMref
56 VDD3.3M 3.3 V power supply
Ref0/MultSel0
Ref1/MultSel1
PCICLK[0–9] 3.3 V PCI clock outputs fixed at 33 MHz.
48 MHz/SelA
48 MHz/SelB
SS
During power up, pins functions as a latched inputs that enables MULTSEL0 and
MULTSEL1 prior to the pins being used for output of 3 V at 14.318 MHz. Part must be
clocked to latch data in.
3.3 V fixed 48 MHz clock outputs. During power up, pins functions as latched inputs
that enables SELA and SELB prior to the pins being used for output of 3 V at 48 MHz.
Part must be clocked to latch data in.
This pin controls the reference current for the host pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the correct current.
Enables spread spectrum mode when held low on differential host outputs,
MREF/MREF_B clocks, 66 MHz clocks, and 33 MHz PCI clocks. Asserts low.
3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending
on the state of input pin SEL133/100. (Out of phase with 3VMREF output).
3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending
on the state of input pin SEL133/100.
PCK2020
2000 Nov 13
3
Page 4
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
BLOCK DIAGRAM
XIN
X
14.318
MHZ
XOUT
SPREAD
SEL 133/100
SEL0
SEL1
OSC
X
X
X
DECODE
X
LOGIC
X
USBPLL
SYSPLL
PWRDWN
PWRDWN
PWRDWN
PWRDWN
PWRDWN
REF [0–1](14.318 MHz)
X
X
48 MHz[0–1] 3 V
CPUCLK [0–3]
X
CPUCLK [0–3]
X
3V66 [0–3] (66 MHz)
X
3VMRef
X
PCK2020
PWRDWN
PWRDWN
X
PWRDWN
PWRDWN
PCICLK_F (33 MHz)
X
3VMRef
X
PCICLK_F (33 MHz)
X
SW00727
2000 Nov 13
4
Page 5
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
PCK2020
differential system clock generator
FUNCTION TABLES
SEL
100/133
0 0 0 100 MHz 50 MHz 66.7 MHz 33.3 MHz 48 MHz 14.318 MHz
0 0 1 105 MHz
0 1 0 200 MHz 50 MHz 66.7 MHz 33.3 MHz N/A N/A
0 1 1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
1 0 0 133 MHz 66.7 MHz 66.7 MHz 33.3 MHz 48 MHz 14.318 MHz
1 0 1 126.7 MHz
1 1 0 200 MHz 66.7 MHz 66.7 MHz 33.3 MHz 48 MHz 14.318 MHz
1 1 1 TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK
NOTE:
1. These frequencies are for debug and thus can vary a small amount from the values listed at the vendor’s discretion.
SEL
100/133
0 0 0 Active 100 MHz
0 0 1 Active 100 MHz – ~5% over-clock
0 1 0 200 MHz, 50 MHz M
0 1 1 HI-Z all outputs
1 0 0 Active 133 MHz
1 0 1 Active 133.3 MHz minus ~5 under-clock
1 1 0 200 MHz, 66 MHz M
1 1 1 Test mode
SELA SELB HOST M
1
1
SELA SELB HOST
REF
52.5 MHz
63.3 MHz
REF
REF
1
1
3V66 3V33 PCI 48 MHz REF
1
70 MHz
63.3 MHz
35 MHz
1
31.7 MHz
1
1
48 MHz 14.318 MHz
48 MHz 14.318 MHz
POWER DOWN MODE
PWRDWN HOST/HOST_BAR MREF/MREF_B 3V66 PCI 48 MHz REF 14.318/66 MHz Seeds
Asserts low
0 = Active
NOTE:
1. The differential outputs should have a voltage forced across them when power down is asserted.
HOST = 2*I
HOST_BAR
REF
LOW LOW LOW LOW OFF LOW/(if applicable)
SPREAD SPECTRUM FUNCTION TABLE
SPREAD FUNCTION
1
0
HOST/PCI/3V66/M
HOST/PCI/3V66/M
Down spread –0.5%
No spread
REF/MREF_B
REF/MREF_B
48 MHz PLL
REF/MULTSEL0
REF/MULTSEL1
No spread
No spread
2000 Nov 13
5
Page 6
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
HOST SWING SELECT FUNCTIONS – TABLE 1
MULTSEL0 MULTSEL1
0 0 60 Ω R
0 0 50 Ω R
0 1 60 Ω R
0 1 50 Ω R
1 0 60 Ω R
1 0 50 Ω R
1 1 60 Ω R
1 1 50 Ω R
0 0 30 Ω R
0 0 25 Ω R
0 1 30 Ω R
0 1 25 Ω R
1 0 30 Ω R
1 0 25 Ω R
1 1 30 Ω R
1 1 25 Ω R
NOTE:
1. In Table 1, the outputs are optimized for the configurations in bold.
BOARD
IMPEDANCE
REF
I
= –2.32 mA
REF
REF
I
= –2.32 mA
REF
REF
I
= –2.32 mA
REF
REF
I
= –2.32 mA
REF
REF
I
= –2.32 mA
REF
REF
I
= –2.32 mA
REF
REF
I
= –2.32 mA
REF
REF
I
= –2.32 mA
REF
REF
I
REF
REF
I
REF
REF
I
REF
REF
I
REF
REF
I
REF
REF
I
REF
REF
I
REF
REF
I
REF
I
REF
= 475 1%
= 475 1%
= 475 1%
= 475 1%
= 475 1%
= 475 1%
= 475 1%
= 475 1%
= 221 1%
= –5 mA
= 221 1%
= –5 mA
= 221 1%
= –5 mA
= 221 1%
= –5 mA
= 221 1%
= –5 mA
= 221 1%
= –5 mA
= 221 1%
= –5 mA
= 221 1%
= –5 mA
I
OH
IOH = 5*I
IOH = 5*I
IOH = 6*I
IOH = 6
IOH = 4*I
IOH = 4*I
IOH = 7*I
IOH = 7*I
IOH = 5*I
IOH = 5*I
IOH = 6*I
IOH = 6*I
IOH = 4*I
IOH = 4*I
IOH = 7*I
IOH = 7*I
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
VOH @ I
PCK2020
= 2.32 mA
REF
0.71 V
0.59 V
0.85 V
0.71 V
0.56 V
0.47 V
0.99 V
0.82 V
0.75 V
0.62 V
0.90 V
0.75 V
0.60 V
0.50 V
1.05 V
0.84 V
I
OUT
I
VDD = 3.3 V ±5% All combinations,
OUT
2000 Nov 13
CONDITIONS CONFIGURATION LOAD MIN. MAX.
VDD = 3.3 V All combinations,
see Table 1
see Table 1
Nominal test load for given configuration –7% of I
See Table 1
Nominal test load for given configuration –12% of I
See Table 1
OH
OH
+7% of I
See Table 1
+12% of I
See Table 1
6
OH
OH
Page 7
Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITION
UNIT
SYMBOL
PARAMETER
CONDITIONS
UNIT
C
L
CK00 (100/133MHz) spread spectrum
PCK2020
differential system clock generator
ABSOLUTE MAXIMUM RATINGS
V
DD3
I
IK
V
I
I
OK
V
O
I
O
T
STG
P
TOT
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC 3.3 V supply –0.5 +4.6 V
DC input diode current VI < 0 –50 mA
DC input voltage Note 2 V
DC output diode current VO > VDD or VO < 0 ±50 mA
DC output voltage Note 2 –0.5 VDD + 0.5 V
DC output source or sink current VO = 0 to V
Storage temperature range –65 +150 °C
Power dissipation per package
plastic medium-shrink (SSOP)
RECOMMENDED OPERATING CONDITIONS
V
A
DD3
VDD
DC 3.3 V supply voltage 3.135 3.465 V
DC 3.3 V analog supply voltage 3.135 3.465 V
Capacitive load on:
1, 2
DD
For temperature range: –40 to +125°C
above +55°C derate linearly with 11.3 mW/K
LIMITS
MIN MAX
±50 mA
850 mW
LIMITS
MIN MAX
PCICLK Must meet PCI 2.1 requirements 10 30 pF
3V66 1 device load, possible 2 loads 10 30 pF
48 MHz clock 1 device load 10 20 pF
REF 1 device load 10 20 pF
M
f
REF
T
amb
, M
REF
REF_BAR
Reference frequency , oscillator normal value 14.31818 14.31818 MHz
Operating ambient temperature range in free air 0 +70 °C
1 device load 10 30 pF
POWER MANAGEMENT
CONDITION
Power-down mode (PWRDWN = 0) 60 mA
Full active 100/133 MHz 250 mA
MAXIMUM 3.3 V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAP LOADS, V
ALL STATIC INPUTS = V
DD3
DDL
OR V
= 3.465 V
SS
2000 Nov 13
7
Page 8
Philips Semiconductors Product specification
TEST CONDITIONS
I
y
mA
I
,
y
mA
I
_
3.135 to 3.465
Type X1
I
y
mA
I
,
y
mA
CK00 (100/133MHz) spread spectrum
PCK2020
differential system clock generator
DC CHARACTERISTICS
LIMITS
T
SYMBOL PARAMETER
VDD (V) OTHER MIN TYP MAX
V
V
HIGH level input voltage 3.135 to 3.465 2.0
IH
LOW level input voltage 3.135 to 3.465 VSS – 0.3 0.8 V
IL
3.3 V output HIGH voltage
V
REF, 3V48M, 3V66, MREF ,
OH3
MREF_BAR, 48 MHz
3.135 to 3.465 IOH = –1 mA 2.0 – V
3.3 V output LOW voltage
V
V
V
V
±I
REF, 3V48M, 3V66, MREF ,
OL3
MREF_BAR, 48 MHz
3.3 V output HIGH voltage
OHP
PCI
3.3 V output LOW voltage
OLP
PCI
PCI, 3V66
3VMREF
OH
3VMREF_BAR
output HIGH current
48 MHz, REF
OH
output HIGH current
HOST/HOST_BAR
OH
OUTPUT CURRENT
PCI, 3V66
3VMREF
OL
3VMREF_BAR
output LOW current
48 MHz, REF
OL
output LOW current
HOST/HOST_BAR VSS = 0.0
OL
±I
Input leakage current 3.365 0 < VIN < V
I
3-State output OFF-State
OZ
current
3.135 to 3.465 IOH = 1 mA – 0.4 V
3.135 to 3.465 IOH = –1 mA 2.4 – V
3.135 to 3.465 IOH = 1 mA – 0.55 V
3.135 V
3.465 V
3.135 V
3.465 V
3.135 V
3.465 V
3.135 V
3.465 V
3.465
= 1.0 V
OUT
= 3.135 V
OUT
= 1.0 V
OUT
= 3.135 V
OUT
0.66 V
0.76 V
= 1.95 V
OUT
= 0.4 V
OUT
= 1.95 V
OUT
= 0.4 V
OUT
Rs = 33.2 Ω
Rp = 49.9 Ω
V
=
OUT
VDD or GND
Type 5
12–55 Ω
Type 3
20–60 Ω
p
Type 5
12–55 Ω
Type 3
20–60 Ω
Type X1 0.0 0.05 V
DD3
IO = 0 10 µA
Cin Input pin capacitance 5 pF
Cxtal Crystal input capacitance 13.5 22.5 pF
Cout Output pin capacitance 6 pF
NOTE:
1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section.
= 0°C to +70°C UNIT
amb
V
+
DD3
0.3
–33
–33
–29
–23
–11 mA
–12.7
30
38
29
27
–5 5 µA
V
2000 Nov 13
8
Page 9
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
PCK2020
differential system clock generator
AC CHARACTERISTICS
V
= 3.3 V –5%; f
DD3
HOST CLOCK OUTPUTS (SEE FIGURE 1 FOR WAVEFORMS AND FIGURE 6 FOR TEST SETUP)
SYMBOL PARAMETER
T
PKP
AbsMinPeriod Absolute Minimum Host CLK Period 7.35 N/A 9.85 N/A ns 11, 14, 20
T
RISE
T
FALL
T
JITTER
DUTY CYCLE Output duty cycle 45 55 45 55 % 11, 14, 20
T
SKEW
Rise/Fall Matching Rise and fall time matching 35% 35% 11, 16, 20
Vcrossover 45% V
= 14.31818 MHz
crystal
LIMITS
T
= 0°C to +70°C
amb
133 MHz MODE 100 MHZ MODE
UNITS NOTES
MIN MAX MIN MAX
HOST CLK period 7.5 7.65 10.0 10.2 ns 11, 14, 20
HOST CLK rise time 175 700 175 700 ps 11, 15, 20
HOST CLK fall time 175 700 175 700 ps 11, 15, 20
HOST CLK cycle-to-cycle jitter 200 200 ps 11, 12, 14, 20
HOST CLK pin-to-pin skew 150 150 ps 11, 14, 20
OH
60% V
OH
45% V
OH
60% V
OH
V 11, 14, 20
MREF OUTPUTS
LIMITS
T
= 0°C to +70°C
SYMBOL PARAMETER
133 MHz MODE 100 MHz MODE
amb
UNITS NOTES
MIN MAX MIN MAX
T
PKP
T
PKH
T
T
RISE
T
FALL
T
JITTER
PKL
MREF period 15.0 15.3 20.0 20.4 ns 2, 9, 20
MREF HIGH time 5.25 N/A 7.5 N/A ns 5, 10, 20
MREF LOW time 5.05 N/A 7.3 N/A ns 6, 10, 20
MREF rise time 0.5 2.0 0.5 2.0 ns 8, 20
MREF fall time 0.5 2.0 0.5 2.0 ns 8, 20
Cycle-to-cycle jitter 250 250 ps 18, 20
DUTY CYCLE Output Duty Cycle 45 55 45 55 % 18, 20
3V66 OUTPUTS
LIMITS
T
= 0°C to +70°C
SYMBOL PARAMETER
133 MHz MODE 100 MHz MODE
MIN MAX MIN MAX
T
PKP
T
PKH
T
T
RISE
T
FALL
T
JITTER
PKL
3V66 period 15.0 16.0 15.0 16.0 ns 2, 4, 9, 20
3V66 HIGH time 5.25 N/A 5.25 N/A ns 5, 10, 20
3V66 LOW time 5.05 N/A 5.05 N/A ns 6, 10, 20
3V66 rise time 0.5 2.0 0.5 2.0 ns 8, 20
3V66 fall time 0.5 2.0 0.5 2.0 ns 8, 20
Cycle-to-cycle jitter 300 300 ps 18, 20
DUTY CYCLE Output Duty Cycle 45 55 45 55 % 18, 20
T
SKEW
Pin-to-pin skew 250 250 ps 20
amb
UNIT NOTES
2000 Nov 13
9
Page 10
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
PCK2020
differential system clock generator
PCI OUTPUTS
LIMITS
T
= 0°C to +70°C
SYMBOL PARAMETER
133 MHz MODE 100 MHz MODE
MIN MAX MIN MAX
T
PKP
T
PKH
T
T
RISE
T
FALL
T
JITTER
PKL
PCI period 30.0 N/A 30.0 N/A ns 2, 3, 9, 20
PCI HIGH time 12.0 N/A 12.0 N/A ns 5, 10, 20
PCI LOW time 12.0 N/A 12.0 N/A ns 6, 10, 20
PCI rise time 0.5 2.0 0.5 2.0 ns 8, 20
PCI fall time 0.5 2.0 0.5 2.0 ns 8, 20
Cycle-to-cycle jitter 500 500 ps 18, 20
DUTY CYCLE Output Duty Cycle 45 55 45 55 % 18, 20
T
SKEW
Pin-to-pin skew 500 500 ps 18, 20
USB CLOCK OUTPUT, 48 MHz (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL PARAMETER
MIN MAX MIN MAX
f Frequency, Actual 48.008 MHz
f
D
T
HKL
T
RISE
T
FALL
T
JITTER
DUTY CYCLE Output Duty Cycle 45 55 45 55 % 18, 20
Deviation from 48 MHz +167 ppm
3V48MHZCLK LOW time 5.05 N/A 5.05 N/A ns 20
3V48MHZCLK rise time 1.0 4.0 1.0 4.0 ns 8, 20
3V48MHZCLK fall time 1.0 4.0 1.0 4.0 ns 8, 20
Cycle-to-cycle jitter 350 350 ps 18, 20
amb
LIMITS
T
= 0°C to +70°C
amb
48 MHz
UNITS NOTES
UNITS NOTES
REF CLOCK OUTPUT, (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS
T
= 0°C to +70°C
SYMBOL PARAMETER
amb
48 MHz
UNITS NOTES
MIN MAX MIN MAX
f Frequency, Actual 14.318 MHz 20
T
T
HKH
T
RISE
T
FALL
T
JITTER
HKL
REF CLK LOW time 31.0 36.67 31.0 36.67 ns 20
REF CLK HIGH time 32.0 37.5 32.0 37.5 ns 20
REF CLK rise time N/A N/A N/A N/A ns 8, 20
REF CLK fall time N/A N/A N/A N/A ns 8, 20
Cycle-to-cycle jitter 1000 1000 ps 18, 20
DUTY CYCLE Output Duty Cycle 45 55 45 55 % 18, 20
ALL OUTPUTS
LIMITS
T
= 0°C to +70°C
SYMBOL PARAMETER
133 MHz MODE 100 MHz MODE
MIN MAX MIN MAX
TpZL, tpZH Output enable delay (all outputs) 1.0 10.0 1.0 10.0 ns 20
TpLZ, tpZH Output disable delay (all outputs) 1.0 10.0 1.0 10.0 ns 20
T
STABLE
All clock Stabilization from Power-up 3 3 ms 7, 20
amb
UNITS NOTES
2000 Nov 13
10
Page 11
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
PCK2020
differential system clock generator
GROUP OFFSET LIMITS
GROUP OFFSET MEASUREMENT LOADS (LUMPED) MEASURE POINTS NOTES
3V66 to PCI
NOTES:
1. Output drivers must have monotonic rise/fall times through the specified V
2. Period, jitter, offset and skew measured on rising edge @ 1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks.
3. The PCI clock is the Host clock divided by four at Host = 133 MHz. PCI clock is the Host clock divided by three at Host = 100 MHz.
4. 3V66 is internal VCO frequency divided by four for Host = 133 MHz. 3V66 clock is internal VCO frequency divided by three at Host =
100 MHz.
5. T
6. T
7. The time is specified from when V
8. T
9. The average period over any 1 µs period of time must be greater than the minimum specified period.
10.Calculated at minimum edge-rate (1 V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure
11.Test load is Rs = 33.2 Ω, Rp = 49.9 Ω.
12.Must be guaranteed in a realistic system environment.
13.Configured for V
14.Measured at crossing points.
15.Measured at 20% to 80%.
16.Determined as a fraction of 2* (Trp–Trn)/(Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.
17.Voltage measure point (Vm = 1.25 V). V
18.Voltage measure point (Vm = 1.5 V). V
19.All offsets are to be measured at rising edges.
20.Parameters are guaranteed by design.
is measured at 2.0 V for 2.5 V outputs and 2.4 V for 3.3 V outputs as shown in Figure 7.
HKH
is measured at 0.4 V for all outputs as shown in Figure 7.
HKL
and operating within specification.
and T
HRISE
duty-cycle specification is met.
are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification.
HFALL
= 0.71 V in a 50 Ω environment.
OH
1.5–3.5 ns
3V66 leads
achieves its normal operating level (typical condition V
DDQ
DD
= 3.3 V.
DD
= 2.5 V.
3V66 @ 30 pf
PCI @ 30 pf
OL/VOH
levels.
3V66 @ 1.5 V
PCI @ 1.5 V
= 3.3 V) until the frequency output is stable
DDQ
19, 20
2000 Nov 13
11
Page 12
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
AC WAVEFORMS
VM = 1.25 V @ V
VX = VOL + 0.3 V
VY = VOH –0.3 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
CPUCLK
@133MHz
3v66
@66MHz
and 1.5 V @ V
DDL
1.25V
1.5V
T
HPOFFSET
Figure 1. Host clock
DD3
CPU leads 3V66
V
DDQ2
V
SS
V
DDQ3
V
SS
SW00569
V
I
SEL1,
SEL0
GND
V
DD
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
V
SS
PCK2020
V
M
t
PLZ
V
X
t
PHZ
V
Y
Outputs
enabled
Figure 3. State enable and disable times
Outputs
disabled
t
PZL
t
PZH
V
M
V
M
Outputs
enabled
SW00571
COMPONENT
MEASUREMENT
POINTS
COMPONENT
MEASUREMENT
POINTS
V
OL
V
OL
2.5VOLT MEASURE POINTS
= 2.0V
V
OH
= 0.4V
V
SS
3.3VOLT MEASURE POINTS
VOH = 2.4V
= 0.4V
V
SS
V
DDQ2
V
= 1.7V
IH
1.25V
V
= 0.7V
IL
V
DDQ3
VIH = 2.0V
1.5V
VIL = 0.7V
Figure 2. 3.3 V clock waveforms
SYSTEM
MEASUREMENT
POINTS
SYSTEM
MEASUREMENT
POINTS
SW00570
2000 Nov 13
12
Page 13
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
V
I
PULSE
GENERATOR
R
T
TEST S
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
V
DD
D.U.T.
Open
2<V
V
SS
PCK2020
S
1
2<V
DD
Open
V
SS
V
O
C
L
1
DD
500Ω
500Ω
PWRDWN
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PWRDWN
CPUCLK
(EXTERNAL)
PCICLK
(EXTERNAL)
OSC & VCO
USB (48 MHz)
VDD = V
DDQ2
or V
, DEPENDS ON THE OUTPUT
DDQ3
Figure 4. Load circuitry for switching times
Figure 5. Power management
SW00572
SW00573
2000 Nov 13
13
Page 14
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
V
I
PULSE
GENERATOR
R
T
TEST S
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
V
DD
D.U.T.
Open
2<V
V
SS
PCK2020
S
1
2<V
DD
Open
V
SS
V
O
C
L
1
DD
500Ω
500Ω
VDD = V
DDQ2
2.5 V CLOCKING
INTERFACE
3.3 V CLOCKING
INTERFACE
(TTL)
or V
, DEPENDS ON THE OUTPUT
DDQ3
Figure 6. Host clock measurements
T
HKP
DUTY CYCLE
T
HKH
2.0 V
1.25 V
0.4 V
T
T
T
T
FALL
PKP
FALL
HKL
T
PKL
2.4 V
1.5 V
0.4 V
T
RISE
DUTY CYCLE
T
PKH
T
RISE
Figure 7. 2.5 V/3.3 V clock waveforms
SW00574
SW00575
2000 Nov 13
14
Page 15
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
PCK2020
differential system clock generator
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1
2000 Nov 13
15
Page 16
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
PCK2020
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Date of release: 11-00
Document order number: 9397 750 07818
2000 Nov 13
16
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