Datasheet PCK2002DGG, PCK2002DL Datasheet (Philips)

INTEGRATED CIRCUITS

PCK2002

2

0–300 MHz I

Product data
File under Integrated Circuits ICL03




C 1:18 clock buffer

2001 Jul 19

Philips Semiconductors Product data

2

0–300 MHz I

C 1:18 clock buffer

PCK2002

FEA TURES

•HIGH speed, LOW noise non-inverting 1–18 buffer

•Typically used to support four SDRAM DIMMs

•Multiple V

, VSS pins for noise reduction

DD

•3.3 V operation

•Separate 3-State pin for testing

•ESD protection exceeds 2000 V per Standard 801.2

•Optimized for 66 MHz, 100 MHz and 133 MHz operation

•Typical 175 ps skew outputs

•Available in 48-pin SSOP and TSSOP packages

•See PCK2002M for mobile (reduced pincount) 28-pin 1-10 buffer

•Spread spectrum compliant

•Individual clock output enable/disable via I

DESCRIPTION

The PCK2002 is a 1–18 fanout buffer used for 133/100 MHz CPU,
66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM
clock distribution. 18 outputs are typically used to support up to
4 SDRAM DIMMS commonly found in desktop, workstation or
server applications.

All clock outputs meet Intel’s drive, rise/fall time, accuracy , and skew
requirements. An I
enabled/disabled individually. An output disabled via the I
interface will be held in the LOW state. In addition, there is an OE
input which 3-States all outputs.

2

C interface is included to allow each output to be

2

C

version

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

t
t

I

PLH
PHL

t

r

t

f

CC

Propagation delay
BUF_IN to BUF_OUT

n

VCC = 3.3 V, CL = 30 pF

2.7

2.9
Rise time VCC = 3.3 V, CL = 30 pF 1.1 ns
Fall time VCC = 3.3 V, CL = 30 pF 1.0 ns
Total supply current VCC = 3.465 V 35 µA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER

48-Pin Plastic TSSOP 0 to +70 °C PCK2002DGG SOT362-1

48-Pin Plastic SSOP 0 to +70 °C PCK2002DL SOT370-1

2

C

ns

PIN CONFIGURATION

RESERVED
RESERVED

BUF_OUT0
BUF_OUT1

BUF_OUT2
BUF_OUT3

BUF_OUT4
BUF_OUT5

BUF_OUT6

BUF_OUT7

BUF_OUT16

I2C is a trademark of Philips Semiconductors Corporation.

V

DD0

V

SS0

V

DD1

V

SS1

BUF_IN

V

DD2

V

SS2

V

DD3

V

SS3

V

DD4

V

SS4

V

DDI2C

SDA

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19

20
21
22
23
24

48

RESERVED

47

RESERVED
V

46

DD9

45

BUF_OUT15

44

BUF_OUT14
V

43

SS9

V

42

DD8

41

BUF_OUT13

40

BUF_OUT12
V

39

SS8

OE

38

V

37

DD7

36

BUF_OUT11

35

BUF_OUT10
V

34

SS7

PCK2002

V

33

DD6

32

BUF_OUT9
BUF_OUT8

31

V

30

SS6

V

29

DD5

BUF_OUT17

28

V

27

SS5

V

SSI2C

26
25

SCL

SW00731

PIN DESCRIPTION

PIN

NUMBER

4, 5, 8, 9 Output BUF_OUT (0–3) Buffered clock outputs

13, 14, 17, 18 Output BUF_OUT (4–7) Buffered clock outputs

31, 32, 35,

36

40, 41, 44,

45

21, 28 Output

11 Input BUF_IN Buffered clock input
38 Input OE
24 I/O SDA I2C serial data

25 Input SCL I2C serial clock

3, 7, 12, 16,

20, 29, 33,

37, 42, 46

6, 10, 15,

19, 22,

27, 30, 34,

39, 43

23 Input V
26 Input V

1, 2, 47, 48 n/a RESERVED Undefined

I/O

TYPE

Output

Output

Input V

Input V

SYMBOL FUNCTION

BUF_OUT

(8–11)

BUF_OUT

(12–15)

BUF_OUT

(16–17)

Buffered clock outputs

Buffered clock outputs

Buffered clock outputs

Active high output
enable

DD (0–9)

SS (0–9)

DDI2C

SSI2C

3.3 V Power supply

Ground

3.3 V I2C Power
supply

I2C Ground

2001 Jul 19 853-2267 26745

2

Philips Semiconductors Product data

SYMBOL

PARAMETER

CONDITION

UNIT

SYMBOL

PARAMETER

CONDITIONS

UNIT

0–300 MHz I

2

C 1:18 clock buffer

PCK2002

FUNCTION TABLE

OE BUF_IN I2CEN BUF_OUTn

L X X Z
H L X L
H H H H
H H L L

ABSOLUTE MAXIMUM RA TINGS

In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to V

V

DD

I

IK

V

I

OK

V

O

I

O

T

STG

P

TOT

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC 3.3 V supply voltage –0.5 +4.6 V
DC input diode current VI < 0 –50 mA
DC input voltage Note 2 –0.5 +4.6 V

I

DC output diode current VO > VDD or VO < 0 ±50 mA
DC output voltage Note 2 –0.5 VCC + 0.5 V
DC output source or sink current VO >= 0 to V
Storage temperature range –65 +150 °C
Power dissipation per package

plastic medium-shrink SO (SSOP)

(VSS = 0V)

SS

1, 2

DD

For temperature range: 0 to +70°C

above +55°C derate linearly with 11.3mW/K

LIMITS

MIN MAX

±50 mA

850 mW

RECOMMENDED OPERATING CONDITIONS

V

T

C

V

V

amb

DD

L

I

O

Operating ambient temperature range in free air 0 +70 °C

DC 3.3 V supply voltage 3.135 3.465 V

Capacitive load 20 30 pF

DC input voltage range 0 V

DC output voltage range 0 V

LIMITS

MIN MAX

DD
DD

V
V

2001 Jul 19

3

Philips Semiconductors Product data

TEST CONDITIONS

VOH3.3V output HIGH voltage

V

VOL3.3V output LOW voltage

V

IOHOutput HIGH current

mA

IOLOutput LOW current

mA

2

0–300 MHz I

C 1:18 clock buffer

DC CHARACTERISTICS

SYMBOL PARAMETER

V

IH

V

IL

±I

I

±I

OZ

I

CC

∆I

CC

HIGH level input voltage 3.135 to 3.465 2.0 VDD + 0.3 V

LOW level input voltage 3.135 to 3.465 VSS – 0.3 0.8 V

p

p

p

p

Input leakage current 3.465 — ±5 µA

3-State output OFF-State current 3.465 V

Quiescent supply current 3.465 VI = VDD or GND IO = 0 — 100 µA

Additional quiescent supply

current given per control pin

PCK2002

LIMITS

T

= 0 to +70 °C UNIT

amb

VDD(V) OTHER MIN MAX

3.135 to 3.465 IOH = –1 mA VCC – 0.1 —

3.135 IOH = –36 mA 2.4 —

3.135 to 3.465 IOL= 1 mA — 0.1

3.135 IOL= 24 mA — 0.4

3.135 V

3.465 V

3.135 to 3.465 V

3.135 to 3.465 V

3.135 to 3.465 V

= 2.0 V –54 –126

OUT

= 3.135 V –21 –46

OUT

= 1.0 V 49 118

OUT

= 0.4 V 24 53

OUT

= VDDor GND IO = 0 — 10 µA

OUT

= VDD– 0.6V IO = 0 — 500 µA

I

AC CHARACTERISTICS

SYMBOL PARAMETER

TEST CONDITIONS

NOTES MIN TYP

T
T

T
T

PZL
PLZ

SDRISE
SDFALL

T

PLH

T

PHL

, T

PZH

, T

PHZ

SDRAM buffer LH propagation delay 4, 5 1.2 2.7 3.5 ns
SDRAM buffer HL propagation delay 4, 5 1.2 2.9 3.5 ns

SDRAM rise time 2, 4 1.5 2.0 4.0 V/ns

SDRAM fall time 2, 4 1.5 2.9 4.0 V/ns

SDRAM buffer enable time 4, 5 1.0 2.6 5.0 ns
SDRAM buffer disable time 4, 5 1.0 2.7 5.0 ns

DUTY CYCLE Output Duty Cycle Measured at 1.5 V 3, 4, 5 45 52 55 %

T

SDSKW

T

DDSKW

SDRAM Bus CLK skew 1, 4 — 150 250 ps

Device to device skew — — 500 ps

NOTES:

1. Skew is measured on the rising edge at 1.5 V .

SDRISE

and T

2. T

3. Duty cycle should be tested with a 50/50% input.

are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1mA) JEDEC specification.

SDFALL

4. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.

5. Input edge rate for these tests must be faster than 1 V/ns.

6. All typical values are at V

= 3.3 V and T

CC

amb

= 25 °C.

LIMITS

T

= 0 to +70 °C

amb

6

MAX

UNIT

2001 Jul 19

4

Philips Semiconductors Product data

0–300 MHz I

2

C 1:18 clock buffer

PCK2002

I2C CONSIDERA TIONS

I2C has been chosen as the serial bus interface to control the PCK2002. I2C was chosen to support the JEDEC proposal JC-42.5 168 Pin
Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I

1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only

one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I
the system.

The following address was confirmed by Philips on 09/04/96.

A6 A5 A4 A3 A2 A1 A0 R/W
11010010

NOTE: The R/W

bit is used by the I2C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’

indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the

bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.

R/W

2) Options: It is our understanding that metal mask options and other pinouts of this type of clock driver will be allowed to use the same address
as the original CKBF device. I

2

C addresses are defined in terms of function (master clock driver) rather than form (pinout, and option).

3) Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality. Slave/transmitter functionality is optional.

4) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.

5) Logic Levels: I2C logic levels are based on a percentage of VDD for the controller and other devices on the bus. Assume all devices are
based on a 3.3 Volt supply.

6) Data Byte Format: Byte format is 8 Bits as described in the following appendices.

7) Data Protocol: To simplify the clock I

2

C interface, the clock driver serial protocol was specified to use only block writes from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I2C protocol.

The clock driver must meet this protocol which is more rigorous than previously stated I

2

C protocol. Treat the description from the viewpoint of
controller. The controller “writes” to the clock driver and if possible would “read” from the clock driver (the clock driver is a slave/receiver only
and is incapable of this transaction.)

“The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte count which
describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h),
followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes.”

2

C devices.

2

C clock driver is used in

1 bit 7 bits 1 1 8 bits 1

Start bit Slave Address R/W Command Code Byte Count = N

Data Byte 1Ack Data Byte 2 Ack

1 bit 8 bits 1 1 8 bits 18 bits 1

Ack

...

NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver).

2001 Jul 19

5

Ack

Data Byte 2 Ack StopAck

SW00279

Philips Semiconductors Product data

2

0–300 MHz I

Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software
programmable via the controller , but will be specified as 0000 0000 in the clock specification. The byte count byte is the numb er of additional

bytes required to transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of

1 byte and a maximum of 32 bytes to satisfy the above requirement.
For example:

Byte count byte
MSB LSB
0000 0000 Not allowed. Must have at least one byte.
0000 0001 Data for functional and frequency select register (currently byte 0 in spec)
0000 0010 Reads first two bytes of data. (byte 0 then byte 1)
0000 0011 Reads first three bytes (byte 0, 1, 2 in order)
0000 0100 Reads first four bytes (byte 0, 1, 2, 3 in order)
0000 0101 Reads first five bytes (byte 0, 1, 2, 3, 4 in order)
0000 0110 Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)
0000 0111 Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
0010 0000 Max byte count supported = 32

A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller interface
can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the bytes that are
sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes than the clock driver
can handle. A clock vendor may choose to discard any number of bytes that exceed the defined byte count.

8) Clock stretching: The clock device must not hold/stretch the SCLOCK or SDATA lines low for more than 10 ms. Clock stretching is

discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an error/time-out

mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without the use of
clock/data stretching.

9) General Call: It is assumed that the clock driver will not have to respond to the “general call.”

10) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I
specification.

a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of
internal pull-ups on these pins of below 100 k Ω is discouraged. Assume that the board designer will use a single external pull-up resistor for
each line and that these values are in the 5–6 k Ω range. Assume one I
clock driver plus one/two more I

(b) Input Glitch Filters: Only fast mode I
mode device and is not required to support this feature.

11) PWR DWN
programming information. I

For specific I2C information consult the Philips I2C Peripherals Data Handbook IC12 (1997).

: If a clock driver is placed in PWR DWN mode, the SDATA and SCLK inputs must be Tri-Stated and the device must retain all

C 1:18 clock buffer

Notes:

2

2

C devices on the platform for capacitive loading purposes.

2

C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard

current due to the I2C circuitry must be characterized and in the data sheet.

dd

C device per DIMM (serial presence detect), one I2C controller, one

PCK2002

2

C

2001 Jul 19

6

Philips Semiconductors Product data

BIT(S)

CONTROL FUNCTION

BIT(S)

CONTROL FUNCTION

0–300 MHz I

2

C 1:18 clock buffer

PCK2002

SERIAL CONFIGURATION MAP

The serial bits will be read by the clock buffer in the following order:

Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 2 – Bits 7, 6, 5, 4, 3, 2, 1, 0

All unused register bits (Reserved and N/A) should be desined as “Don’t Care”. It is expected that the controller will force all of these bits to a
“0” level.

All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating
current. The controller will read back the last written value.

Byte 0: SDRAM Output active/inactive register

1 = enable; 0 = disable

AFFECTED PIN

PIN NO. PIN NAME

7 18 BUF_OUT7 Clock Output Disable Low Active
6 17 BUF_OUT6 Clock Output Disable Low Active
5 14 BUF_OUT5 Clock Output Disable Low Active
4 13 BUF_OUT4 Clock Output Disable Low Active
3 9 BUF_OUT3 Clock Output Disable Low Active
2 8 BUF_OUT2 Clock Output Disable Low Active
1 5 BUF_OUT1 Clock Output Disable Low Active
0 4 BUF_OUT0 Clock Output Disable Low Active

NOTE:

1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”.

BIT CONTROL

0 1

Byte 1: SDRAM Output active/inactive register

1 = enable; 0 = disable

AFFECTED PIN

PIN NO. PIN NAME

7 45 BUF_OUT15 Clock Output Disable Low Active
6 44 BUF_OUT14 Clock Output Disable Low Active
5 41 BUF_OUT13 Clock Output Disable Low Active
4 40 BUF_OUT12 Clock Output Disable Low Active
3 36 BUF_OUT11 Clock Output Disable Low Active
2 35 BUF_OUT10 Clock Output Disable Low Active
1 32 BUF_OUT9 Clock Output Disable Low Active
0 31 BUF_OUT8 Clock Output Disable Low Active

NOTE:

1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”.

BIT CONTROL

0 1

2001 Jul 19

7

Philips Semiconductors Product data

BIT(S)

CONTROL FUNCTION

2

0–300 MHz I

C 1:18 clock buffer

Byte 2: SDRAM Output active/inactive register

1 = enable; 0 = disable

AFFECTED PIN

PIN NO. PIN NAME

7 N/A BUF_OUT17 Clock Output Disable Low Active
6 12 BUF_OUT16 Clock Output Disable Low Active
5 N/A Reserved (Reserved) — —
4 N/A Reserved (Reserved) — —
3 N/A Reserved (Reserved) — —
2 N/A Reserved (Reserved) — —
1 N/A Reserved (Reserved) — —
0 N/A Reserved (Reserved) — —

NOTE:

1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”.

BIT CONTROL

0 1

PCK2002

2001 Jul 19

8

Philips Semiconductors Product data

2

0–300 MHz I

C 1:18 clock buffer

AC WAVEFORMS

VM = 1.5 V
VX = VOL + 0.3 V
VY = VOH –0.3 V
VOL and VOH are the typical output voltage drop that occur with the
output load.

V

DD

BUF_IN

INPUT

BUF_OUT

Figure 1. Load circuitry for switching times.

V

I

nOE INPUT

V

M

t

PLH

V

M

V

M

t

PHL

V

M

V

M

SW00246

V

DD

TEST CIRCUIT

PULSE

GENERATOR

Figure 4. Load circuitry for switching times

V

I

R

T

TEST S

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

V

DD

D.U.T.

Open

2<V

PCK2002

S

1

2<V

DD

Open

V

SS

V

O

C

L

1

DD

V

SS

500Ω

500Ω

SW00251

GND

t

V

DD

OUTPUT
LOW-to-OFF
OFF-to-LOW

V

OL

V

OH

OUTPUT
HIGH-to-OFF
OFF-to-HIGH

V

SS

PLZ

outputs
enabled

t

PHZ

V

X

V

Y

Figure 2. 3-State enable and disable times

T

SDKH

T

SDFALL

SDKP

DUTY CYCLE

T

2.4

1.5

0.4

T

SDRISE

outputs
disabled

T

SDKL

t

PZL

V

M

t

PZH

V

M

outputs
enabled

SW00245

2001 Jul 19

SW00247

Figure 3. Buffer Output clock

9

Philips Semiconductors Product data

2

0–300 MHz I

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1

C 1:18 clock buffer

PCK2002

2001 Jul 19

10

Philips Semiconductors Product data

2

0–300 MHz I

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1

C 1:18 clock buffer

PCK2002

2001 Jul 19

11

Philips Semiconductors Product data

0–300 MHz I

2

C 1:18 clock buffer

PCK2002

Data sheet status

Product

Data sheet status

Objective data

Preliminary data

Product data

[1] Please consult the most recently issued datasheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on

the Internet at URL http://www.semiconductors.philips.com.

[1]

status

Development

Qualification

Production

[2]

Definitions

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 2001

All rights reserved. Printed in U.S.A.

Date of release: 07-01

Document order number: 9397 750 08585




2001 Jul 19

12