Datasheet PCK2000MDB Datasheet (Philips)

INTEGRATED CIRCUITS

PCK2000M

CK97 (66/100MHz) Mobile System Clock
Generator

Product specification 1998 Sep 29

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Philips Semiconductors Product specification

PCK2000MCK97 (66/100MHz) Mobile System Clock Generator

FEA TURES

•Reduced pincount version of PCK2000 for mobile applications

•Mixed 2.5V and 3.3V operation

•Two CPU clocks at 2.5V

•Six synchronous PCI clocks at 3.3V, one free–running

•One 3.3V reference clock @ 14.318 MHz

•Reference 14.31818 MHz Xtal oscillator input

•100 MHz or 66 MHz operation

•Power management control input pins

•175 ps CPU clock jitter

•175 ps skew on outputs

•Available in 28–pin SSOP package

•1.5 – 4ns CPU–PCI delay

•Power down if PWRDWN is held LOW

•See PCK2000 for 48-pin version

DESCRIPTION

The PCK2000M is a clock synthesizer/driver chip for a Pentium Pro
or other similar processors, typically used in mobile applications.

The PCK2000M has two CPU clock outputs at 2.5V. There are six
PCI clock outputs running at 33 MHz. One of the PCI clock outputs
is free–running. The 3.3V reference clock outputs at 14.318 MHz.
All clock outputs meet Intel’s drive strength, rise/fall time, jitter,
accuracy, and skew requirements.

The part possesses dedicated powerdown, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on–chip and ensure glitch–free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs are
driven LOW. When the PCIST OP inputs is asserted, the PCI clock
outputs are driven LOW.

Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW, except the free running PCICLK_F clock output.

The PCK2000M is available in a 28–pin SSOP package.

PIN CONFIGURATION

XTAL IN

OUT V

XTAL

V

SSPCI0

PCICLK_F

PCICLK1

V

DDPCI0

PCICLK2
PCICLK3

V

DDPCI1

V

SSPCI1

DDCORE0

SSCORE0

10
11
12 17
13 16V
14 15V

PCICLK4

PCICLK5 CPUSTOP

V

1
227
3
4
5
6
7
8
9

TOP VIEW

28

SSREF

DDREF

REF

26
25

V

DDCPU

24

CPUCLK0

23

CPUCLK1

22

V

SSCPU

21

V

DDCORE1

20

V
19
18

SSCORE1

PCISTOP

PWRDWN

SEL

SEL100/66

SA00448

PCK2000M

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DRAWING NUMBER

28-Pin Plastic SSOP 0°C to +70°C PCK2000M DB PCK2000M DB SOT341-1

Intel and Pentium are registered trademarks of Intel Corporation.

1998 Sep 29 853-2128 20101

2

Philips Semiconductors Product specification

CK97 (66/100MHz) Mobile System Clock Generator

PCK2000M

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

26 REF 14.318 MHz clock output
28 V
27 V

SSREF
DDREF

1 XTAL_IN 14.318 MHz crystal input
2 XTAL_OUT 14.318 MHz crystal output

3, 12 V

[0–1] GROUND for PCI outputs

SSPCI

4 PCICLK_F Free-running PCI output

6, 9 V

[0–1] POWER for PCI outputs

DDPCI

5, 7, 8, 10, 11 PCICLK [1–5] PCI clock outputs.

13, 21 V
14, 20 V

[0–1] Isolated POWER for core

DDCORE

[0–1] Isolated GROUND for core

SSCORE

16 SEL Logic select pins
15 SEL100/66
17 PWRDWN Control pin to put device in powerdown state, active low

18 CPUSTOP Control pin to disable CPU clocks, active low
19 PCISTOP Control pin to disable PCI clocks, active low
25 V
22 V

DDCPU
SSCPU

23, 24 CPUCLK [0–1] CPU and Host clock outputs 2.5V

NOTE:

1. V

and VSS names in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on

DD

the performance of the device. In reality, the platform will be configured with the V
tied to a common 3.3V supply and all V

pins being common.

SS

GROUND for REF output
POWER for REF output

Select pin for enabling 66 MHz or 100MHz or 66 MHz. L = 66 Mhz
H = 100MHz

Power for CPU outputs
GROUND for CPU outputs

pins tied to a 2.5V supply, all remaining V

DDCPU

DD

pins

BLOCK DIAGRAM

XTAL_IN

XTAL_OUT

SEL100/66

CPUSTOP

PCISTOP

PWRDWN

SEL0

X

X

X

X

X
X
X

14.318
MHZ
OSC

LOGIC

PLL1

PWRDWN

LOGIC

STOP

LOGIC

PWRDWN

LOGIC

STOP

LOGIC

REFCLK (14.318 MHz)

X

CPUCLK [0–1]

X

PCICLK_F (33MHz)

X

PCICLK [1–5] (33MHz)

X

SW00275

1998 Sep 29

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Philips Semiconductors Product specification

CK97 (66/100MHz) Mobile System Clock Generator

SELECT FUNCTIONS

SEL100/66 SEL0 FUNCTION NOTES

0 0 TRI-State 1
0 1 Active 66MHz
1 0 Test mode 1
1 1 Active 100MHz

NOTES:

1. Internal decode logic for all two select inputs implemented.

FUNCTION

DESCRIPTION

Tri-State Hi-Z Hi-Z Hi-Z

Test mode TCLK/2 TCLK/6 TCLK

FUNCTION TABLE

SEL 100/66 CPU/PCI RATIO

0 2 66.66 33.33 14.318
1 3 100 33.33 14.318

CPU PCI, PCI_F REF

CPUCLK (0–1)

(MHz)

OUTPUTS

CPICLK (1–5)

PCICLK_F

(MHz)

PCK2000M

REF

(MHz)

CLOCK ENABLE CONFIGURATION

CPUSTOP PCISTOP PWRDWN CPUCLK PCICLK PCICLK_F

X X 0 LOW LOW LOW Stopped OFF OFF
0 0 1 LOW LOW 33MHz Running Running Running
0 1 1 LOW 33MHz 33MHz Running Running Running
1 0 1 100/66MHz LOW 33MHz Running Running Running
1 1 1 100/66MHz 33MHz 33MHz Running Running Running

OTHER

CLOCKS

PLL OSCILLATOR

POWER MANAGEMENT REQUIREMENTS

LATENCY

SIGNAL SIGNAL STATE

CPUSTOP 0 (DISABLED) 1

1 (ENABLED) 1

PCISTOP 0 (DISABLED) 1

1 (ENABLED) 1

PWRDWN 1 (NORMAL OPERATION) 3ms

0 (POWER DOWN) 2 MAX

NOTES:

1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.

2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.

NO. OF RISING EDGES OF FREE RUNNING

PCICLK

1998 Sep 29

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Philips Semiconductors Product specification

SYMBOL

PARAMETER

CONDITION

UNIT

SYMBOL

PARAMETER

CONDITIONS

UNIT

CK97 (66/100MHz) Mobile System Clock Generator

ABSOLUTE MAXIMUM RATINGS

1, 2

PCK2000M

In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to VSS (VSS = 0V)

LIMITS

MIN MAX

V
V
V

T

P

DD3
DDQ3
DDQ2

I

IK

V

I

I

OK

V

O

I

O

STG

TOT

DC 3.3V core supply voltage –0.5 +4.6 V

DC 3.3V I/O supply voltage –0.5 +4.6 V
DC 2.5V I/O supply voltage –0.5 +3.6 V

DC input diode current VI < 0 –50 mA

DC input voltage Note 2 –0.5 5.5 V

DC output diode current VO > VCC or VO < 0 ±50 mA

DC output voltage Note 2 –0.5 VCC + 0.5 V

DC output source or sink current VO >= 0 to V

CC

±50 mA

Storage temperature range –65 +150 °C

Power dissipation per package

plastic medium-shrink (SSOP)

For temperature range: –40 to +125°C

above +55°C derate linearly with 11.3mW/K

850 mW

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

NOTES:

1. V

DD3

2. V

DDQ3

3. V

DDQ2

V
V
V

T

DD3
DDQ3
DDQ2

V

I

V

O

amb

= V

= V
= V

DDCORE1

DDREF

DDCPU0

Operating ambient temperature range in free air 0 +70 °C

= V

= V

= V

DC 3.3V core supply voltage Note 1 3.135 3.465 V

DC 3.3V I/O supply voltage Note 2 3.135 3.465 V
DC 2.5V I/O supply voltage Note 3 2.135 2.625 V

DC input voltage range 0 V

DC output voltage range 0

= 3.3V

DDCPU1

= 3.3V

= 2.5V

DDCORE2

DDPCI0

LIMITS

MIN MAX

DD3

V

DDQ2

V

DDQ3

V
V

1998 Sep 29

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Philips Semiconductors Product specification

TEST CONDITIONS

SYMBOL

PARAMETER

I

mA

I

mA

I

mA

I

mA

O erating su ly current

O erating su ly current

CK97 (66/100MHz) Mobile System Clock Generator

PCK2000M

DC CHARACTERISTICS

LIMITS

T

= 0°C to +70°C UNIT

SYMBOL PARAMETER

V

V

V

V

V

V
V

V

V

±I

IH

IL

OH2

OL2

OH3

OL3

POH
POL

OH

OH

OL

OL

±I

OZ

DD

(V)

HIGH level input voltage 3.135 to 3.465

LOW level input voltage 3.135 to 3.465

2.5V output HIGH voltage
CPUCLK

2.5V output LOW voltage
CPUCLK

3.3V output HIGH voltage
REF

3.3V output LOW voltage
REF

2.375 to 2.625 IOH = –1mA

2.375 to 2.625 IOL = 1mA – 0.4 V

3.135 to 3.465 IOH = –1mA 2.0 – V

3.135 to 3.465 IOL = 1mA – 0.4 V

PCI output HIGH voltage 3.135 to 3.465 IOH = –1mA 2.4 – V

PCI output LOW voltage 3.135 to 3.465 IOL = 1mA – 0.55 V

output HIGH current

output HIGH current

output LOW current

output LOW current

I

Input leakage current 3.465 – 5 µA

3-State output OFF-State

CPUCLK

PCI

CPUCLK

PCI

current

2.375 V

2.625 V

3.135 V

3.465 V

2.375 V

2.625 V

3.135 V

3.465 V

3.465

OUT

= 2.375V – –27

OUT

OUT

= 3.135V – –33

OUT

OUT
OUT

OUT

OUT

V

OUT

Vdd or GND

OTHER MIN TYP MAX

V

= 2.5V

DDQ2

±5%

V

= 3.3V

DDQ3

±5%

V

= 3.3V

DDQ3

±5%

= 1.0V –27 –

= 1.0V –33 –

= 1.2V 27 –
= 0.3V – 30

= 1.95V 30 –

= 0.4V – 38

=

IO = 0 – 10 µA

Cin Input pin capacitance 5 pF

Cxtal

Xtal pin capacitance, as
seen by external crystal

Cout Output pin capacitance 6 pF

1
1

1
1

I

I

dd3

dd2

p

pp

3.465

66MHz mode Outputs loaded

100MHz mode Outputs loaded

Powerdown supply current All static inputs to V

p

pp

2.625

66MHz mode Output loaded

100MHz mode Output loaded

Powerdown supply current All static inputs to V

or GND 500 µA

DD

or GND 100 µA

DD

NOTE:

1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section.

amb

2.0 VDD + 0.3 V

VSS – 0.3 0.8 V

2.0 – V

18 pF

170 mA
170 mA

72 mA

100 mA

1998 Sep 29

6

Philips Semiconductors Product specification

CK97 (66/100MHz) Mobile System Clock Generator

PCK2000M

AC CHARACTERISTICS

VDDREF = VDDPCI (0–1)= 3.3V ± 5%; VDDCPU = 2.5V ± 5%; f

= 14.31818 MHz

crystal

CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL PARAMETER

TEST CONDITIONS

NOTES MIN MAX

T

(tP) CPUCLK period 2 15.0 15.5

HKP

T

(tH) CPUCLK HIGH time 66MHz 1, 5 5.2 ns

HKH

T

(tL) CPUCLK LOW time 1, 5 5.0

HKL

T

(tP) CPUCLK period 2 10.0 10.5

HKP

T

(tH) CPUCLK HIGH time 100MHz 1, 5 3.0 ns

HKH

T

(tL) CPUCLK LOW time 1, 5 2.8

HKL

T

(tR) CPUCLK rise time 9 0.4 1.6 ns

HRISE

T

(tF) CPUCLK fall time 9 0.4 1.6 ns

HFALL

T

(tJC) CPUCLK jitter 175 ps

JITTER

DUTY CYCLE (tD) Output Duty Cycle 1 45 55 %

T

(tSK) CPU Bus CLK skew 2 175 ps

HSKW

T

(fST) CPUCLK stabilization from Power-up 7 3 ms

HSTB

LIMITS

T

= 0°C to +70°C

amb

UNIT

PCI CLOCK OUTPUTS, PCI(1–5) AND PCI_F (LUMP CAPACITANCE TEST LOAD = 30pF)

SYMBOL PARAMETER

TEST CONDITIONS

NOTES MIN MAX

T

(tP) PCICLK period 3 30.0 ns

PKP

T

PKPS

T

(tH) PCICLK HIGH time 1 12.0 ns

PKH

T

(tL) PCICLK LOW time 1 12.0 ns

PKL

T

(tR) PCICLK rise time 10 0.5 2.0 ns

HRISE

T

(tF) PCICLK fall time 10 0.5 2.0 ns

HFALL

T

(tSK) PCI Bus CLK skew 2 500 ps

PSKW

T

HPOFFSET

T

(tO) CPUCLK to PCICLK Offset 2, 4 1.5 4.0 ns

(fST) PCICLK stabilization from Power-up 7 3 ms

PSTB

PCICLK period stability 8 500 ps

LIMITS

T

= 0°C to +70°C

amb

REF CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL PARAMETER

TEST CONDITIONS

NOTES MIN MAX

f Frequency, Actual

T

(tR) Output rise edge rate 1 4 ns

HRISE

T

(tF) Output fall edge rate 1 4 ns

HFALL

Frequency generated

by Crystal

DUTY CYCLE (tD) Duty Cycle 45 55 %

T

(fST) Frequency stabilization from Power-up (cold start) 3 ms

HSTB

LIMITS

T

= 0°C to +70°C

amb

14.31818 MHz

UNIT

UNIT

1998 Sep 29

7

Philips Semiconductors Product specification

CK97 (66/100MHz) Mobile System Clock Generator

PCK2000M

ALL CLOCK OUTPUTS

SYMBOL PARAMETER

TEST CONDITIONS

NOTES MIN MAX

T

, T

PZL

PZH

T

, T

PLZ

PHZ

Output enable time 1.0 8.0 ns

Output disable time 1.0 8.0 ns

NOTES:

1. See Figure 3 for measure points.

2. Period, jitter, offset, and skew are measured on the rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.

3. The PCICLK is the CPUCLK divided by two at CPUCLK = 66.6MHz. PCICLK is the CPUCLK divided by three at CPUCLK = 100MHz.

4. The CPUCLK must always lead the PCICLK as shown in Figure 2.

5. T

6. T

7. The time is specified from when V

is measured @ 2.0V as shown in Figure 4.

HKH

is measured @ 0.4V as shown in Figure 4.

HKL

stable and operating within specification.

achieves its nominal operating level (typical condition is V

DDQ

= 3.3V) until the frequency output is

DDQ

8. Defined as once the clock is at its nominal operating frequency, the adjacent period changes cannot exceed the time specified .

9. T

10.T

HRISE
HRISE

and T
and T

are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.0V (1mA) JEDEC specification.

HFALL

(REF, PCI) are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V

HFALL

LIMITS

T

= 0°C to +70°C

amb

AC WAVEFORMS

VM = 1.25V @ V
VX = VOL + 0.3V
VY = VOH –0.3V
V

and VOH are the typical output voltage drop that occur with the

OL

output load.

and 1.5V @ V

DDQ2

DDQ3

UNIT

1.25V

CPUCLK

1.25V

CPUCLK

T

HSKW

Figure 1. CPUCLK to CPUCLK skew

1.25V

CPUCLK

1.5V

PCICLK

T

HPOFFSET

Figure 2. CPUCLK to PCICLK offset

V

DDQ2

V

SS

V

DDQ2

V

SS

SW00240

V

DDQ2

V

SS

V

DDQ3

V

SS

SW00241

T

HKH

2.5V CLOCKING
INTERFACE

3.3V CLOCKING
INTERFACE

(TTL)

1.25

2.0

0.4

T

RISE

T

PKH

2.4

1.5

0.4

T

RISE

Figure 3. 2.5V/3.3V Clock waveforms

T

HKP

DUTY CYCLE

T

FALL

T

PKP

T

FALL

T

HKL

T

PKL

SW00242

1998 Sep 29

8

Philips Semiconductors Product specification

CK97 (66/100MHz) Mobile System Clock Generator

V

I

SEL 100, 66,
SEL1, SEL0

V

M

GND

t

V

DD

OUTPUT
LOW-to-OFF
OFF-to-LOW

V

OL

V

OH

OUTPUT
HIGH-to-OFF
OFF-to-HIGH

V

SS

PLZ

t

outputs
enabled

PHZ

V

X

V

Y

Figure 4. 3-State enable and disable times.

outputs
disabled

t

PZL

V

M

t

PZH

V

M

outputs
enabled

SW00239

COMPONENT

MEASUREMENT

POINTS

V

COMPONENT

MEASUREMENT

POINTS

V

Figure 5. Component versus system measure points

VOH = 2.0V

= 0.4V

OL

VOH = 2.4V

= 0.4V

OL

2.5VOLT MEASURE POINTS

V

SS

3.3VOLT MEASURE POINTS

V

SS

PCK2000M

V

DDQ2

V

= 1.7V

IH

1.25V

V

= 0.7V

IL

V

DDQ3

V

= 2.0V

IH

1.5V
= 0.7V

V

IL

SYSTEM

MEASUREMENT

POINTS

SYSTEM

MEASUREMENT

POINTS

SW00243

1998 Sep 29

9

Philips Semiconductors Product specification

CK97 (66/100MHz) Mobile System Clock Generator

CPUSTOP

CPUCLK
(INTERNAL)

PCICLK
(INTERNAL)

PCICLK
(FREE-RUNNING)

CPUSTOP

CPUCLK
(EXTERNAL)

PCISTOP

CPUCLK
(INTERNAL)

PCK2000M

PCICLK
(INTERNAL)

PCICLK
(FREE-RUNNING)

PCISTOP

PCICLK
(EXTERNAL)

PWRDWN

CPUCLK
(INTERNAL)

PCICLK
(INTERNAL)

PWRDWN

CPUCLK
(EXTERNAL)

PCICLK
(EXTERNAL)

1998 Sep 29

VCO

CRYSTAL

SW00244

Figure 6. Power Management

10

Philips Semiconductors Product specification

CK97 (66/100MHz) Mobile System Clock Generator

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm SOT341-1

PCK2000M

1998 Sep 29

11

Philips Semiconductors Product specification

PCK2000MCK97 (66/100MHz) Mobile System Clock Generator

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 05-96
Document order number: 9397–750-04604

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