Datasheet PCF8579H-F1, PCF8579U, PCF8579U-10, PCF8579U-12, PCF8579U-2-F1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1996 Oct 25
File under Integrated Circuits, IC12

1997 Apr 01

INTEGRATED CIRCUITS

PCF8579

LCD column driver for dot matrix
graphic displays

1997 Apr 01 2

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION

7.1 Multiplexed LCD bias generation

7.2 Power-on reset

7.3 Timing generator

7.4 Column drivers

7.5 Display RAM

7.6 Data pointer

7.7 Subaddress counter

7.8 I2C-bus controller

7.9 Input filters

7.10 RAM access

7.11 Display control

7.12 TEST pin
8I

2

C-BUS PROTOCOL

8.1 Command decoder
9 CHARACTERISTICS OF THE I2C-BUS

9.1 Bit transfer

9.2 Start and stop conditions

9.3 System configuration

9.4 Acknowledge

10 LIMITING VALUES
11 HANDLING
12 DC CHARACTERISTICS
13 AC CHARACTERISTICS
14 APPLICATION INFORMATION
15 CHIP DIMENSIONS AND BONDING PAD

LOCATIONS
16 CHIP-ON GLASS INFORMATION
17 PACKAGE OUTLINES
18 SOLDERING

18.1 Introduction

18.2 Reflow soldering

18.3 Wave soldering

18.3.1 LQFP

18.3.2 VSO

18.3.3 Method (LQFP and VSO)

18.4 Repairing soldered joints
19 DEFINITIONS
20 LIFE SUPPORT APPLICATIONS
21 PURCHASE OF PHILIPS I2C COMPONENTS

1997 Apr 01 3

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

1 FEATURES

• LCD column driver

• Used in conjunction with the PCF8578, this device forms

part of a chip set capable of driving up to 40960 dots

• 40 column outputs

• Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32

• Externally selectable bias configuration, 5 or 6 levels

• Easily cascadable for large applications (up to

32 devices)

• 1280-bit RAM for display data storage

• Display memory bank switching

• Auto-incremented data loading across hardware

subaddress boundaries (with PCF8578)

• Power-on reset blanks display

• Logic voltage supply range 2.5 to 6 V

• Maximum LCD supply voltage 9 V

• Low power consumption

• I

2

C-bus interface

• TTL/CMOS compatible

• Compatible with most microcontrollers

• Optimized pinning for single plane wiring in multiple

device applications (with PCF8578)

• Space saving 56-lead plastic mini-pack and 64-pin
plastic low profile quad flat package

• Compatible with chip-on-glass technology

• I2C-bus address: 011110 SA0.

2 APPLICATIONS

• Automotive information systems

• Telecommunication systems

• Point-of-sale terminals

• Computer terminals

• Instrumentation.

3 GENERAL DESCRIPTION

The PCF8579 is a low power CMOS LCD column driver,
designed to drive dot matrix graphic displays at multiplex
rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device has
40 outputs and can drive 32 × 40 dots in a 32 row
multiplexed LCD. Up to 16 PCF8579s can be cascaded
and up to 32 devices may be used on the same I

2

C-bus
(using the two slave addresses). The device is optimized
for use with the PCF8578 LCD row/column driver.
Together these two devices form a general purpose LCD
dot matrix driver chip set, capable of driving displays of up
to 40960 dots. The PCF8579 is compatible with most
microcontrollers and communicates via a two-line
bidirectional bus (I2C-bus). To allow partial VDD shutdown
the ESD protection system of the SCL and SDA pins does
not use a diode connected to VDD. Communication
overheads are minimized by a display RAM with
auto-incremented addressing and display bank switching.

4 ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

PCF8579T VSO56 plastic very small outline package; 56 leads SOT190
PCF8579U7 − chip with bumps on tape −
PCF8579H LQFP64 plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2

1997 Apr 01 4

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

5 BLOCK DIAGRAM

Fig.1 Block diagram.

C39 - C0

17 - 56
(30 to 33, 35 to 64, 1 to 6)

MSA919

V

DD

PCF8579

V

LCD

V

3

V

4

12 (20)
14 (22)
15 (23)
16 (24)

6 (12)

OUTPUT

CONTROLLER

COLUMN
DRIVERS

(1)

Y DECODER

AND SENSING

AMPLIFIERS

32 x 40 BIT

DISPLAY RAM

X DECODER

DISPLAY

DECODER

RAM DATA POINTER

SUBADDRESS

COUNTER

TIMING

GENERATOR

I C-BUS

CONTROLLER

2

INPUT

FILTERS

COMMAND

DECODER

POWER-ON

RESET

TEST

2 (8)
1 (7)

SCL

SDA

n.c.

SA0

(15, 19, 21, 25 to 29, 34)
13

7 (13)

(10) 4

(9) 3

CLK

SYNC

YX

8 (14)
9 (16)

10 (17)
11 (18)

A3
A2
A1
A0

5 (11)

V

SS

(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
The pin numbers given in parenthesis refer to the LQFP64 package.

1997 Apr 01 5

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

6 PINNING

Note

1. Do not connect, this pin is reserved.

SYMBOL

PINS

DESCRIPTION

VSO56 LQFP64

SDA 1 7 I

2

C-bus serial data input/output

SCL 2 8 I

2

C-bus serial clock input
SYNC 3 9 cascade synchronization input
CLK 4 10 external clock input
V

SS

5 11 ground (logic)

TEST 6 12 test pin (connect to V

SS

)

SA0 7 13 I

2

C-bus slave address input (bit 0)
A3 to A0 8 to 11 14, 16 to 18 I

2

C-bus subaddress inputs
V

DD

12 20 supply voltage

n.c. 13

(1)

15, 19, 21,25 to 29, 34 not connected

V

3

, V

4

14 and 15 22 and 23 LCD bias voltage inputs

V

LCD

16 24 LCD supply voltage

C39 to C0 17 to 56 30 to 33, 35 to 64 and 1 to 6 LCD column driver outputs

1997 Apr 01 6

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Fig.2 Pin configuration (VSO56).

1
2
3
4
5
6
7
8

9
10
11
12

13

44
43
42

41
40
39

38
37
36
35

34
33
32
31

14
15
16
17
18
19
20

22

23
24
25
26

21

46
45

47

48

49

50

51

52

53

54

55

56

27
28

30

29

MSA918

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

C0

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

n.c.

A0

SA0

TEST

SS

CLK

SYNC

SCL

SDA

V

PCF8579

V

LCD

V

4

V

3

V

DD

A1

A2

A3

1997 Apr 01 7

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Fig.3 Pin configuration (LQFP64).

handbook, full pagewidth

PCF8579

MBH590

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

SDA

SCL

A2

A3

SA0

TEST

CLK

SYNC

V

SS

n.c.

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35

C36

C37

C38

C39

n.c.

n.c.

n.c.

n.c.

A0

A1

V4V

3

V

DD

V

LCD

n.c.

n.c.

n.c.

n.c.

1997 Apr 01 8

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

7 FUNCTIONAL DESCRIPTION

The PCF8579 column driver is designed for use with the
PCF8578. Together they form a general purpose LCD dot
matrix chip set.

Typically up to 16 PCF8579s may be used with one
PCF8578. Each of the PCF8579s is identified by a unique
4-bit hardware subaddress, set by pins A0 to A3.
The PCF8578 can operate with up to 32 PCF8579s when
using two I2C-bus slave addresses. The two slave
addresses are set by the logic level on input SA0.

7.1 Multiplexed LCD bias generation

The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (V

th

). Vth is typically defined as the RMS voltage at
which the LCD exhibits 10% contrast. Table 1 shows the
optimum voltage bias levels for the PCF8578/PCF8579
chip set as functions of Vop(Vop=VDD− V

LCD

), together
with the discrimination ratios (D) for the different multiplex
rates. A practical value for Vop is obtained by equating
V

off(rms)

with Vth. Figure 4 shows the first 4 rows of Table 1

as graphs.

Table 1 Optimum LCD bias voltages

PARAMETER

MULTIPLEX RATE

1:8 1:16 1:24 1:32

0.739 0.800 0.830 0.850

0.522 0.600 0.661 0.700

0.478 0.400 0.339 0.300

0.261 0.200 0.170 0.150

0.297 0.245 0.214 0.193

0.430 0.316 0.263 0.230

1.447 1.291 1.230 1.196

3.370 4.080 4.680 5.190

V

2

V

op

---------

V

3

V

op

---------

V

4

V

op

---------

V

5

V

op

---------

V

off rms()

V

op

-----------------------

V

on rms()

V

op

---------------------- -

D

V

on rms()

V

off rms()

-----------------------

=

V

op

V

th

---------

7.2 Power-on reset

At power-on the PCF8579 resets to a defined starting
condition as follows:

1. Display blank (in conjunction with PCF8578)

2. 1 : 32 multiplex rate

3. Start bank, 0 selected

4. Data pointer is set to X, Y address 0, 0

5. Character mode

6. Subaddress counter is set to 0

7. I

2

C-bus is initialized.

Data transfers on the I2C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.

Fig.4 V

bias/Vop

as a function of the multiplex rate.

1:8 1:16 1:32

1.0

0

0.8

MSA838

1:24

0.6

0.4

0.2

multiplex rate

V

bias

V

op

V

5

V

4

V

3

V

2

V

bias=V2

, V3, V4, V5. See Table 1.

1997 Apr 01 9

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Fig.5 LCD row/column waveforms.

MSA841

V

DD

V

2

V
V
V
V

3
4
5
LCD

T

frame

COLUMN

SYNC

V

DD

V

2

V
V
V
V

3
4
5
LCD

ROW 0

0 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SYNC

V

DD

V

2

V
V
V
V

3
4
5

LCD

COLUMN

V

DD

V

2

V
V
V
V

3
4
5
LCD

ROW 0

23222120191817161514131211109876543210

SYNC

V

DD

V

2

V
V
V
V

3
4
5
LCD

COLUMN

V

DD

V

2

V
V
V
V

3
4
5
LCD

ROW 0

15

SYNC

14131211109876543210

V

DD

V

2

V
V
V
V

3
4

5
LCD

COLUMN

V

DD

V

2

V
V
V
V

3
4
5
LCD

ROW 0

0 1 2 3 4 5 67

ON
OFF

1:8

1:16

1:24

1:32

column

display

1997 Apr 01 10

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Fig.6 LCD drive mode waveforms for 1 : 8 multiplex rate.

MSA840

V

DD

V

2

V
V
V
V

3
4
5
LCD

T

frame

ROW 1
R1 (t)

V

DD

V

2

V
V
V
V

3
4
5
LCD

ROW 2
R2 (t)

V

DD

V

2

V
V
V
V

3
4
5
LCD

COL 1
C1 (t)

V

DD

V

2

V
V
V
V

3
4
5
LCD

COL 2
C2 (t)

dot matrix
1:8 multiplex rate

0.261 V

op

0.261 V

op

0 V

V

op

V

op

V

state 1

(t)

V

state 2

(t)

0.261 V

op

0.261 V

op

0 V

V

op

V

op

0.478 V

op

0.478 V

op

state 1 (OFF)
state 2 (ON)

V

state 1

(t) = C1(t) R1(t):

V

on(rms)

V

op

=

188 1

8 1

()

8

=

0.430

V

state 2

(t) = C2(t) R2(t):

V

off(rms)

V

op

=

8 1

8 1

()

8

=

0.297

2

2

()

general relationship (n = multiplex rate)

V

on(rms)

V

op

=

1

n

n

1

n

1

()

n

V

off(rms)

V

op

=

n

1

n

1

()

n

2

2

()

1997 Apr 01 11

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Fig.7 LCD drive mode waveforms for 1 : 16 multiplex rate.sa.

MSA836

V

DD

V

2

V
V
V
V

3
4
5
LCD

T

frame

ROW 1
R1 (t)

V

DD

V

2

V
V
V
V

3
4
5

LCD

ROW 2
R2 (t)

V

DD

V

2

V
V
V
V

3
4
5
LCD

COL 1
C1 (t)

V

DD

V

2

V
V
V
V

3
4
5
LCD

COL 2
C2 (t)

dot matrix
1:16 multiplex rate

state 1 (OFF)
state 2 (ON)

0.2 V

op

0.2 V

op

0 V

V

op

V

op

V

state 1

(t)

0.2 V

op

0.2 V

op

0 V

V

op

V

op

V

state 2

(t)

0.6 V

op

0.6 V

op

V

state 1

(t) = C1(t) R1(t):

V

on(rms)

V

op

=

1

16

16 1

16 1

()

16

=

0.316

V

state 2

(t) = C2(t) R2(t):

V

off(rms)

V

op

=

16 1

16 1

()

16

=

0.254

2

2

()

general relationship (n = multiplex rate)

V

on(rms)

V

op

=

1

n

n

1

n

1

()

n

V

off(rms)

V

op

=

n

1

n

1

()

n

2

2

()

1997 Apr 01 12

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

7.3 Timing generator

The timing generator of the PCF8579 organizes the
internal data flow from the RAM to the display drivers.
An external synchronization pulse SYNC is received from
the PCF8578. This signal maintains the correct timing
relationship between cascaded devices.

7.4 Column drivers

Outputs C0 to C39 are column drivers which must be
connected to the LCD. Unused outputs should be left
open-circuit.

7.5 Display RAM

The PCF8579 contains a 32 × 40-bit static RAM which
stores the display data. The RAM is divided into 4 banks of
40 bytes (4 × 8 × 40 bits). During RAM access, data is
transferred to/from the RAM via the I

2

C-bus.

7.6 Data pointer

The addressing mechanism for the display RAM is
realized using the data pointer. This allows an individual
data byte or a series of data bytes to be written into, or read
from, the display RAM, controlled by commands sent on
the I

2

C-bus.

7.7 Subaddress counter

The storage and retrieval of display data is dependent on
the content of the subaddress counter. Storage and
retrieval take place only when the contents of the
subaddress counter agree with the hardware subaddress
at pins A0, A1, A2 and A3.

7.8 I

2

C-bus controller

The I2C-bus controller detects the I2C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel) and the
data output (parallel-to-serial). The PCF8579 acts as an
I2C-bus slave transmitter/receiver. Device selection
depends on the I2C-bus slave address, the hardware
subaddress and the commands transmitted.

7.9 Input filters

To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.

7.10 RAM access

There are three RAM ACCESS modes:

• Character

• Half-graphic

• Full-graphic.

These modes are specified by bits G1 and G0 of the RAM
ACCESS command. The RAM ACCESS command
controls the order in which data is written to or read from
the RAM (see Fig.8).

To store RAM data, the user specifies the location into
which the first byte will be loaded (see Fig.9):

• Device subaddress (specified by the DEVICE SELECT
command)

• RAM X-address (specified by the LOAD X-ADDRESS
command)

• RAM bank (specified by bits Y1 and Y0 of the RAM
ACCESS command).

Subsequent data bytes will be written or read according to
the chosen RAM access mode. Device subaddresses are
automatically incremented between devices until the last
device is reached. If the last device has subaddress 15,
further display data transfers will lead to a wrap-around of
the subaddress to 0.

7.11 Display control

The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The number of rows scanned depends on the multiplex
rate set by bits M1 and M0 of the SET MODE command.

The display status (all dots on/off and normal/inverse
video) is set by bits E1 and E0 of the SET MODE
command. For bank switching, the RAM bank
corresponding to the top of the display is set by bits
B1 and B0 of the SET START BANK command. This is
shown in Fig.10 This feature is useful when scrolling in
alphanumeric applications.

7.12 TEST pin

The TEST pin must be connected to V

SS

.

1997 Apr 01 13

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic

displays

PCF8579

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MSA921

01234567891011

0

246810121416182022

1357911131517192123

0

4 8 12 16 20 24 28 32 36 40 44

1 5 9 13 17 21 25 29 33 37 41 45

2 6 10 14 18 22 26 30 34 38 42 46

3 7 11 15 19 23 27 31 35 39 43 47

RAM data bytes are

written or read as

indicated above

full-graphic mode

LSB

MSB

bank 0

bank 1

bank 2

bank 3

PCF8579 system RAM

1 k 16

half-graphic mode

character mode

1 byte

4 bytes

RAM

2 bytes

4 bytes

40-bits

driver 1

driver 2 driver k

PCF8579 PCF8579 PCF8579

Fig.8 RAM access mode.

1997 Apr 01 14

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic

displays

PCF8579

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MSA835

S
A
0

S

011110 0A

slave address

/RW

0

110110 A

DEVICE SELECT

1

0

000100 A

LOAD X-ADDRESS

1

1

111000 A

RAM ACCESS

0

last command

S
A
0

S

011110

1A

slave address

/RW

DATA

A

READ

WRITE

DATA A DATA A

DEVICE SELECT:

subaddress 12

RAM ACCESS:
character mode

bank 1

LOAD X-ADDRESS: X-address = 8

RAM

bank 0

bank 1

bank 2

bank 3

Fig.9 Example of commands specifying initial data byte RAM locations.

1997 Apr 01 15

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Fig.10 Relationship between display and SET START BANK; 1 : 32 multiplex rate and start bank = 2.

MSA851

bank 0

top of LCD

bank 1

bank 2

bank 3

LCD

RAM

1997 Apr 01 16

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

8I2C-BUS PROTOCOL

Two 7-bit slave addresses (0111100 and 0111101) are
reserved for both the PCF8578 and PCF8579. The least
significant bit of the slave address is set by connecting
input SA0 to either logic 0 (VSS) or logic 1 (VDD).
Therefore, two types of PCF8578 or PCF8579 can be
distinguished on the same I2C-bus which allows:

1. One PCF8578 to operate with up to 32 PCF8579s on
the same I2C-bus for very large applications.

2. The use of two types of LCD multiplex schemes on the
same I2C-bus.

In most applications the PCF8578 will have the same slave
address as the PCF8579.

The I2C-bus protocol is shown in Fig.11.
All communications are initiated with a start condition (S)
from the I2C-bus master, which is followed by the desired
slave address and read/write bit. All devices with this slave
address acknowledge in parallel. All other devices ignore
the bus transfer.

In WRITE mode (indicated by setting the read/write bit
LOW) one or more commands follow the slave address
acknowlegement. The commands are also acknowledged
by all addressed devices on the bus.
The last command must clear the continuation bit C. After
the last command a series of data bytes may follow.
The acknowlegement after each byte is made only by the
(A0, A1, A2 and A3) addressed PCF8579 or PCF8578
with its implicit subaddress 0. After the last data byte has
been acknowledged, the I2C-bus master issues a stop
condition (P).

In READ mode, indicated by setting the read/write bit
HIGH, data bytes may be read from the RAM following the
slave address acknowlegement. After this
acknowlegement the master transmitter becomes a
master receiver and the PCF8579 becomes a slave
transmitter. The master receiver must acknowledge the
reception of each byte in turn. The master receiver must
signal an end of data to the slave transmitter, by not
generating an acknowledge on the last byte clocked out of
the slave. The slave transmitter then leaves the data line
HIGH, enabling the master to generate a stop
condition (P).

Display bytes are written into, or read from, the RAM at the
address specified by the data pointer and subaddress
counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be
transferred either to, or from, the intended devices.

In multiple device applications, the hardware subaddress
pins of the PCF8579s (A0 to A3) are connected to V

SS

or
VDD to represent the desired hardware subaddress code.
If two or more devices share the same slave address, then
each device must be allocated a unique hardware
subaddress.

1997 Apr 01 17

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Fig.11 (a) Master transmits to slave receiver (WRITE mode); (b) Master reads after sending command string

(WRITE commands; READ data); (c) Master reads slave immediately after sending slave address (READ
mode).

MSA830

S
A
0

S

011110 0AC

COMMAND

A

P

ADISPLAY DATA

slave address

/RW

acknowledge by

all addressed

PCF8578s / PCF8579s

acknowledge

by A0, A1, A2 and A3

selected PCF8578s /

PCF8579s only

n 0 byte(s)n 0 byte(s)1 byte

update data pointers

and if necessary,

subaddress counter

(a)

MSA831

S
A

0

S

011110 1A

DATA

A

P

1DATA

slave address

/RW

acknowledge by

all addressed

PCF8578s / PCF8579s

last byten bytes

update data pointers

and if necessary,

subaddress counter

(c)

acknowledge

from master

no acknowledge

from master

MSA832

S
A
0

S

011110 0AC

COMMAND

A

slave address

/RW

acknowledge by

all addressed

PCF8578s / PCF8579s

n 1 byte

(b)

ADATA

S
A

0

S

011110 1A

slave address

/RW

P

1DATA

n bytes last byte

update data pointers

and if necessary

subaddress counter

acknowledge

from master

no acknowledge

from master

at this moment master
transmitter becomes a
master receiver and
PCF8578/PCF8579 slave
receiver becomes a
slave transmitter

1997 Apr 01 18

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

8.1 Command decoder

The command decoder identifies command bytes that
arrive on the I2C-bus. The most significant bit of a
command is the continuation bit C (see Fig.12). When this
bit is set, it indicates that the next byte to be transferred will
also be a command. If the bit is reset, it indicates the
conclusion of the command transfer. Further bytes will be
regarded as display data. Commands are transferred in
WRITE mode only.

The five commands available to the PCF8579 are defined
in Tables 2 and 3.

C = 0; last command.
C = 1; commands continue.

Fig.12 General format of command byte.

MSA833

REST OF OPCODE

C

MSB LSB

Table 2 Summary of commands

Note

1. C = command continuation bit. D = may be a logic 1 or 0.

COMMAND OPCODE

(1)

DESCRIPTION

SET MODE C 1 0 DDDDDmultiplex rate, display status, system type
SET START BANK C 1 1111DDdefines bank at top of LCD
DEVICE SELECT C 1 1 0 DDDDdefines device subaddress
RAM ACCESS C 1 1 1 DDDDgraphic mode, bank select (D D D D ≥ 12 is not allowed;

see SET START BANK opcode)

LOAD X-ADDRESS C 0 DDDDDD0to39

1997 Apr 01 19

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Table 3 Definition of PCF8578/PCF8579 commands

COMMAND OPCODE OPTIONS DESCRIPTION

SET MODE C 1 0 T E1 E0 M1 M0 see Table 4 defines LCD drive mode

see Table 5 defines display status
see Table 6 defines system type

SET START BANK C 11111B1B0see Table 7 defines pointer to RAM bank

corresponding to the top of the LCD;
useful for scrolling, pseudo motion and
background preparation of new display

DEVICE SELECT C 110A3A2A1A0see Table 8 four bits of immediate data, bits

A0 to A3, are transferred to the
subaddress counter to define one of
sixteen hardware subaddresses

RAM ACCESS C 111G1G0Y1Y0see Table 9 defines the auto-increment behaviour of

the address for RAM access

see Table 10 two bits of immediate data, bits Y0 to Y1,

are transferred to the X-address pointer
to define one of forty display RAM
columns

LOAD X-ADDRESS C 0 X5 X4 X3 X2 X1 X0 see Table11 six bits of immediate data, bits X0 to X5,

are transferred to the X-address pointer
to define one of forty display RAM
columns

1997 Apr 01 20

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Table 4 Set mode option 1

Table 5 Set mode option 2

Table 6 Set mode option 3

Table 7 Set start bank option 1

LCD DRIVE MODE

BITS

M1 M0

1 : 8 MUX ( 8 rows) 0 1
1 : 16 MUX (16 rows) 1 0
1 : 24 MUX (24 rows) 1 1
1 : 32 MUX (32 rows) 0 0

DISPLAY STATUS

BITS

E1 E0

Blank 0 0
Normal 0 1
All segments on 1 0
Inverse video 1 1

SYSTEM TYPE BIT T

PCF8578 row only 0
PCF8578 mixed mode 1

START BANK POINTER

BITS

B1 B0

Bank 0 0 0
Bank 1 0 1
Bank 2 1 0
Bank 3 1 1

Table 8 Device select option 1

Table 9 RAM access option 1

Note

1. See opcode for SET START BANK in Table 3.

Table 10RAM access option 2

Table 11Load X-address option 1

DESCRIPTION BITS

Decimal value of 0 to 15 A3 A2 A1 A0

RAM ACCESS MODE

BITS

G1 G0

Character 0 0
Half-graphic 0 1
Full-graphic 1 0
Not allowed (note 1) 1 1

DESCRIPTION BITS

Decimal value of 0 to 3 Y1 Y0

DESCRIPTION BITS

Decimal value of 0 to 39 X5 X4 X3 X2 X1 X0

1997 Apr 01 21

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

9 CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL) which
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this moment will be interpreted as control signals.

9.2 Start and stop conditions

Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the start condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH, is defined as the stop condition (P).

9.3 System configuration

A device transmitting a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message flow is the ‘master’ and the devices
which are controlled by the master are the ‘slaves’.

9.4 Acknowledge

The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down
the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal the end of a data transmission to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.

Fig.13 Bit transfer.

MBA607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

1997 Apr 01 22

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Fig.14 Definition of start and stop condition.

MBA608

SDA

SCL

P

STOP condition

SDA

SCL

S

START condition

Fig.15 System configuration.

MBA605

MASTER

TRANSMITTER /

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER /

RECEIVER

SDA

SCL

The general characteristics and detailed specification of the I2C-bus are available on request.

Fig.16 Acknowledgement on the I2C-bus.

handbook, full pagewidth

MBA606 - 1

START

condition

S

SCL FROM

MASTER

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

clock pulse for

acknowledgement

1

2

8

9

1997 Apr 01 23

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

11 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe it is
desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12
under

“Handling MOS Devices”.

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

supply voltage −0.5 +8.0 V

V

LCD

LCD supply voltage VDD− 11 V

DD

V

V

i1

input voltage pins SDA, SCL, SYNC, CLK, TEST, SA0, A0,
A1, A2 and A3

VSS− 0.5 VDD+ 0.5 V

V

i2

input voltage pins V3 and V

4

V

LCD

− 0.5 VDD+ 0.5 V

V

o1

output voltage pin SDA VSS− 0.5 VDD+ 0.5 V

V

o2

output voltage pins C0 to C39 V

LCD

− 0.5 VDD+ 0.5 V

I

I

DC input current −10 +10 mA

I

O

DC output current −10 +10 mA

I

DD

, ISS, I

LCD

current at pins VDD, VSS or V

LCD

−50 +50 mA

P

tot

total power dissipation per package − 400 mW

P

o

power dissipation per output − 100 mW

T

stg

storage temperature −65 +150 °C

1997 Apr 01 24

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

12 DC CHARACTERISTICS

V

DD

= 2.5 to 6 V; VSS=0V;V

LCD=VDD

− 3.5 V to VDD− 9V;T

amb

= −40 to +85 °C; unless otherwise specified.

Notes

1. Outputs are open; inputs at V

DD

or VSS; I2C-bus inactive; clock with 50% duty factor.

2. Resets all logic when VDD<V

POR

.

3. Periodically sampled; not 100% tested.

4. Resistance measured between output terminal (C0 to C39) and bias input (V3, V4, VDD and V

LCD

) when the specified

current flows through one output under the following conditions (see Table 1):
a) − Vop=VDD− V

LCD

=9V;

b) − V3− V

LCD

≥ 4.70 V; V4− V

LCD

≤ 4.30 V; I

LOAD

= 100 µA.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DD

supply voltage 2.5 − 6.0 V

V

LCD

LCD supply voltage VDD− 9 − VDD− 3.5 V

I

DD

supply current f

CLK

= 2 kHz; note 1 − 920 µA

V

POR

power-on reset level note 2 − 1.3 1.8 V

Logic

V

IL

LOW level input voltage V

SS

− 0.3V

DD

V

V

IH

HIGH level input voltage 0.7V

DD

− V

DD

V

I

LI1

leakage current at pins SDA, SCL,
SYNC, CLK, TEST, SA0, A0, A1, A2
and A3

Vi=VDD or V

SS

−1 − +1 µA

I

OL

LOW level output current at pin SDA VOL= 0.4 V; VDD=5V 3 −− mA

C

i

input capacitance note 3 −−5pF

LCD outputs

I

LI2

leakage current at pins V3 to V

4

Vi=VDD or V

LCD

−2 − +2 µA

V

DC

DC component of LCD drivers pins
C0 to C39

−±20 − mV

R

COL

output resistance at pins C0 to C39 note 4 − 36 kΩ

1997 Apr 01 25

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

13 AC CHARACTERISTICS

All timing values are referred to V

IH

and VIL levels with an input voltage swing of VSS to VDD.

V

DD

= 2.5 to 6 V; VSS=0V;V

LCD=VDD

− 3.5 V to VDD− 9 V; T

amb

= −40 to +85 °C; unless otherwise specified.

Note

1. Typically 0.9 to 3.3 kHz.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

f

clk

clock frequency 50% duty factor − note 1 10 kHz

t

PLCD

driver delays VDD− V

LCD

= 9 V; with test loads −−100 µs

I

2

C-bus

f

SCL

SCL clock frequency −−100 kHz

t

SW

tolerable spike width on bus −−100 ns

t

BUF

bus free time 4.7 −−µs

t

SU;STA

START condition set-up time repeated start codes only 4.7 −−µs

t

HD;STA

START condition hold time 4.0 −−µs

t

LOW

SCL LOW time 4.7 −−µs

t

HIGH

SCL HIGH time 4.0 −−µs

t

r

SCL and SDA rise time −−1.0 µs

t

f

SCL and SDA fall time −−0.3 µs

t

SU;DAT

data set-up time 250 −−ns

t

HD;DAT

data hold time 0 −−ns

t

SU;STO

STOP condition set-up time 4.0 −−µs

Fig.17 AC test loads.

MSA916

Ω1.5 k

V

DD

SDA

1 nF

C0 to C39

(2%)

1997 Apr 01 26

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Fig.18 Driver timing waveforms.

MSA917

0.7 V

DD

0.3 V

DD

1/ f

CLK

CLK

0.5 V

0.5 V

t

PLCD

C0 to C39

(V V = 9 V)

DD LCD

Fig.19 I2C-bus timing waveforms.

, full pagewidth

SDA

MGA728

SDA

SCL

t

SU;STA

t

SU;STO

t

HD;STA

t

BUF

t

LOW

t

HD;DAT

t

HIGH

t

r

t

f

t

SU;DAT

1997 Apr 01 27

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic

displays

PCF8579

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14 APPLICATION INFORMATION

R

OSC

OSC

V

SS

SCL SDA SA0

CLKSYNC

V

3

V

4

V

DD

V

LCD

A0
A1
A2
A3

V

SS

V

SS

PCF8579

1

40
columns

subaddress 0

V

SS

SCLSDA

SA0

CLK SYNC

V

3

V

4

V

DD

V

LCD

PCF8578

(ROW MODE)

V

LCD

V

DD

V

2

V

5

V

SS

unused columns

8

SCL
SDA

V

DD

V

SS

32

rows

R

R

R

R

C

C

C

C

C

V

SS

SCL SDA SA0

CLKSYNC

V

3

V

4

V

DD

V

LCD

A0
A1
A2
A3

V

SS

V

SS

PCF8579

2

40
columns

subaddress 1

V

DD

V

SS

SCL SDA SA0

CLKSYNC

V

3

V

4

V

DD

V

LCD

A0
A1
A2
A3

V

SS

V

SS

PCF8579

k

40
columns

V

DD

subaddress k 1

1:32 multiplex rate
32 x 40 x k dots (k 16)
(20480 dots max.)

LCD DISPLAY

V

DD

(4 2 3)R

V

SS

MSA845

Fig.20 Typical LCD driver system with 1 : 32 multiplex rate.

1997 Apr 01 28

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic

displays

PCF8579

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R

OSC

OSC

V

SS

SCL

SDA SA0

CLKSYNC

V

3

V

4

V

DD

V

LCD

A0
A1
A2
A3

V

SS

V

SS

PCF8579

1

40
columns

subaddress 0

V

SS

SCL

SDA

SA0

CLK SYNC

V

3

V

4

V

DD

V

LCD

PCF8578

(ROW MODE)

V

LCD

V

DD

V

2

V

5

VSSV

DD

/

V

SS

unused columns

16

8

rows

SCL
SDA

V

DD

V

SS

1:16 multiplex rate
16 x 40 x k dots (k 16)
(10240 dots max.)

16

rows

R

R

R

R

R

C

C

C

C

C

V

SS

SCLSDASA0

CLK

SYNC

V

3

V

4

V

DD

V

LCD

A0

A1

A2

A3

V

DD

PCF8579

1

40
columns

subaddress 0

V

DD

V

SS

V

SS

SCLSDASA0

CLK

SYNC

V

3

V

4

V

DD

V

LCD

A0

A1

A2

A3

V

DD

PCF8579

40
columns

V

DD

V

SS

subaddress k 1

k

V

SS

SCL

SDA SA0

CLKSYNC

V

3

V

4

V

DD

V

LCD

A0
A1
A2
A3

V

SS

V

SS

PCF8579

2

40
columns

subaddress 1

V

DD

V

SS

SCL

SDA SA0

CLKSYNC

V

3

V

4

V

DD

V

LCD

A0
A1
A2
A3

V

SS

V

SS

PCF8579

k

40
columns

V

DD

subaddress k 1

1:16 multiplex rate
16 x 40 x k dots (k 16)
(10240 dots max.)

LCD DISPLAY

V

SS

SCLSDASA0

CLK

SYNC

V

3

V

4

V

DD

V

LCD

A0

A1

A2

A3

V

DD

PCF8579

2

40
columns

subaddress 1

V

DD

V

SS

V

DD

MSA847

Fig.21 Split screen application with 1 : 16 multiplex rate for improved contrast.

1997 Apr 01 29

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic

displays

PCF8579

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R

OSC

OSC

V

SS

SCL

SDA SA0

CLKSYNC

V

3

V

4

V

DD

V

LCD

A0
A1
A2
A3

V

SS

V

SS

PCF8579

1

40
columns

subaddress 0

V

SS

SCL

SDA

SA0

CLK SYNC

V

3

V

4

V

DD

V

LCD

PCF8578

(ROW MODE)

V

LCD

V

DD

V

2

V

5

VSSV

DD

/

V

SS

unused columns

8

SCL
SDA

V

DD

V

SS

1:32 multiplex rate
32 x 40 x k dots (k 16)
(20480 dots max.)

32

rows

R

R

R

R

C

C

C

C

C

V

SS

SCLSDASA0

CLK

SYNC

V

3

V

4

V

DD

V

LCD

A0

A1

A2

A3

V

DD

PCF8579

1

40
columns

subaddress 0

V

DD

V

SS

V

SS

SCLSDASA0

CLK

SYNC

V

3

V

4

V

DD

V

LCD

A0

A1

A2

A3

V

DD

PCF8579

40
columns

V

DD

V

SS

subaddress k 1

k

V

SS

SCL

SDA SA0

CLKSYNC

V

3

V

4

V

DD

V

LCD

A0
A1
A2
A3

V

SS

V

SS

PCF8579

2

40
columns

subaddress 1

V

DD

V

SS

SCL

SDA SA0

CLKSYNC

V

3

V

4

V

DD

V

LCD

A0
A1
A2
A3

V

SS

V

SS

PCF8579

k

40
columns

V

DD

subaddress k 1

1:32 multiplex rate
32 x 40 x k dots (k 16)
(20480 dots max.)

LCD DISPLAY

V

SS

SCLSDASA0

CLK

SYNC

V

3

V

4

V

DD

V

LCD

A0

A1

A2

A3

V

DD

PCF8579

2

40
columns

subaddress 1

V

DD

V

SS

V

DD

32

(4 2 3)R

MSA846

Fig.22 Split screen application with 1 : 32 multiplex rate.

1997 Apr 01 30

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic

displays

PCF8579

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SDA

V

LCD

SCL

V

SS

V

DD

PCF8578

LCD DISPLAY

MSA852

OSC

R

n.c.
n.c.

R31/C31

R0

RRRR

(4 2 3)R

n.c.

C0 C27 C28 C39

PCF8579

n.c.

C0 C27 C28 C39

PCF8579

to other
PCF8579s

Fig.23 Example of single plane wiring, single screen with 1 : 32 multiplex rate (PCF8578 in row driver mode).

1997 Apr 01 31

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

15 CHIP DIMENSIONS AND BONDING PAD LOCATIONS

Chip area: 14.37 mm2.
Bonding pad dimensions: 120 µm × 120 µm.
Gold bump dimensions (if ordered): 94 × 94 × 25 µm.
The numbers given in the square boxes refer to the pad number.

MSA920

V

SS

SDA

PCF8579

4.76
mm

3.02 mm

V

LCD

A2

A3

TEST

CLK

SCL

n.c.

V

3

V

4

C39
C38
C37

C36

C35

C33

C32

C31

C30

C29

C28

C27

C26

C25

C24

C23

C0

C1

C2

C3

SA0

C5

SYNC

C6
C7
C8
C9

C10

C11

C12
C13

C14

C15
C16

C17
C18
C19
C20

C21

C22

V

DD

A1

A0

C4

C34

x

y

0

0

5612555453

52

51

50

34567

49

48

47

46

45

44
43

42

41
40

39

38

37

36

35

34

33323130292827262524232221

20

19

18

17

16

15

14

13

12

11

10

9

8

Fig.24 Bonding pad locations.

1997 Apr 01 32

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

Table 12 Bonding pad locations (dimensions in µm)
All x/y coordinates are referenced to centre of chip, see Fig.24.

PAD NUMBER SYMBOL x y

PINS

VSO56 LQFP64

1 SDA 252 2142 1 7
2 SCL 48 2142 2 8
3

SYNC −156 2142 3 9
4 CLK −360 2142 4 10
5V

SS

−564 2142 5 11
6 TEST −786 2142 6 12
7 SA0 −1032 2142 7 13
8A3−1314 2142 8 14
9A2−1314 1920 9 16

10 A1 −1314 1716 10 17
11 A0 −1314 1512 11 18
12 V

DD

−1314 708 12 20
13 n.c. −1314 504 13 21
14 V

3

−1314 300 14 22
15 V

4

−1314 96 15 23
16 V

LCD

−1314 −108 16 24
17 C39 −1314 −1308 17 30
18 C38 −1314 −1512 18 31
19 C37 −1314 −1716 19 32
20 C36 −1314 −1920 20 33
21 C35 −1314 −2142 21 35
22 C34 −1032 −2142 22 36
23 C33 −786 −2142 23 37
24 C32 −564 −2142 24 38
25 C31 −360 −2142 25 39
26 C30 −156 −2142 26 40
27 C29 48 −2142 27 41
28 C28 252 −2142 28 42
29 C27 498 −2142 29 43
30 C26 702 −2142 30 44
31 C25 906 −2142 31 45
32 C24 1110 −2142 32 46
33 C23 1314 −2142 33 47
34 C22 1314 −1830 34 48
35 C21 1314 −1570 35 49
36 C20 1314 −1326 36 50
37 C19 1314 −1122 37 51

1997 Apr 01 33

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

38 C18 1314 −918 38 52
39 C17 1314 −714 39 53
40 C16 1314 −510 40 54
41 C15 1314 −306 41 55
42 C14 1314 −102 42 56
43 C13 1314 102 43 57
44 C12 1314 306 44 58
45 C11 1314 510 45 59
46 C10 1314 714 46 60
47 C9 1314 918 47 61
48 C8 1314 1122 48 62
49 C7 1314 1326 49 63
50 C6 1314 1566 50 64
51 C5 1314 1830 51 1
52 C4 1314 2142 52 2
53 C3 1110 2142 53 3
54 C2 906 2142 54 4
55 C1 702 2142 55 5
56 C0 498 2142 56 6

− n.c. −−−15, 19, 21,
25 to 29, 34

PAD NUMBER SYMBOL x y

PINS

VSO56 LQFP64

1997 Apr 01 34

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic

displays

PCF8579

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16 CHIP-ON GLASS INFORMATION

MSA850

V

DD

PCF8578

V

LCD

V

3

V

4

PCF8579

C39

C38

C37

V

DD

V

LCD

n.c.

A2

A3

V

3

V

4

A1

A0

V

SS

TEST

SA0

CLK

SCL

SDA

C0

C1

SYNC

V

DD

V

LCD

V

4

V

5

V

3

V

2

SA0

OSC

C39

C38

V

SS

TEST

CLK

SCL

SDA

R0

SYNC

R

OSC

R1

R2

R0 to R31

SYNC

SCL

SDA

V

SS

CLK

V

LCD

V

3

V

4

SYNC
SCL
SDA

V

SS

CLK

C0 C1 C2

LCD
DISPLAY

V

DD

If inputs SA0 and A0 to A3 are left unconnected they are internally pulled-up to VDD.

Fig.25 Typical chip-on glass application (viewed from underside of chip).

1997 Apr 01 35

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

17 PACKAGE OUTLINES

UNIT A

1

A2A3b

p

cD

(1)E(2)

(1)

eHELLpQZywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

0.3

0.1

3.0

2.8

0.25

0.42

0.30

0.22

0.14

21.65

21.35

11.1

11.0

0.75

15.8

15.2

1.45

1.30

0.90

0.55

7
0

o
o

0.1 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

1.6

1.4

SOT190-1

96-04-02
97-08-11

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

X

(A )

3

A

y

56

29

281

pin 1 index

0.012

0.004

0.12

0.11

0.017

0.012

0.0087

0.0055

0.85

0.84

0.44

0.43

0.0295

2.25

0.089

0.62

0.60

0.057

0.051

0.035

0.022

0.004

0.2

0.008 0.004

0.063

0.055

0.01

0 5 10 mm

scale

VSO56: plastic very small outline package; 56 leads

SOT190-1

A

max.

3.3

0.13

Note

1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

1997 Apr 01 36

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

UNIT

A

max.

A1A2A3b

p

cE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

1.60

0.20

0.05

1.45

1.35

0.25

0.27

0.17

0.18

0.12

10.1

9.9

0.5

12.15

11.85

1.45

1.05

7
0

o
o

0.12 0.11.0 0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT314-2

95-12-19
97-08-01

D

(1) (1)(1)

10.1

9.9

H

D

12.15

11.85

E

Z

1.45

1.05

D

b

p

e

θ

E

A

1

A

L

p

detail X

L

(A )

3

B

16

c

D

H

b

p

E

H

A

2

v M

B

D

Z

D

A

Z

E

e

v M

A

X

1

64

49

48 33

32

17

y

pin 1 index

w M

w M

0 2.5 5 mm

scale

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

1997 Apr 01 37

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

18 SOLDERING

18.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

18.2 Reflow soldering

Reflow soldering techniques are suitable for all LQFP and
VSO packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

18.3 Wave soldering

18.3.1 LQFP
Wave soldering is not recommended for LQFP packages.

This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

18.3.2 VSO
Wave soldering techniques can be used for all VSO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

18.3.3 METHOD (LQFP AND VSO)

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

18.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 Apr 01 38

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

19 DEFINITIONS

20 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

21 PURCHASE OF PHILIPS I

2

C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

1997 Apr 01 39

Philips Semiconductors Product specification

LCD column driver for dot matrix graphic
displays

PCF8579

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1997 SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,
Tel. [phone], Fax. [phone]

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
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Spain: Balmes 22, 08007 BARCELONA,
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Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
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Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

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United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]/xxx
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]
Middle East: see Italy

Printed in The Netherlands 417067/1200/03/pp40 Date of release: 1997 Apr 01 Document order number: 9397 750 01757