Datasheet PCF8576U-10, PCF8576U-12, PCF8576U-2, PCF8576U-5, PCF8576U-7 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

PCF8576

Universal LCD driver for low
multiplex rates

Product specification
Supersedes data of 1997 Nov 18
File under Integrated Circuits, IC12

1998 Feb 06

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 PINNING
6 FUNCTIONAL DESCRIPTION

6.1 Power-on reset

6.2 LCD bias generator

6.3 LCD voltage selector

6.4 LCD drive mode waveforms

6.4.1 Static drive mode

6.4.2 1 : 2 multiplex drive mode

6.4.3 1 : 3 multiplex drive mode

6.4.4 1 : 4 multiplex drive mode

6.5 Oscillator

6.5.1 Internal clock

6.5.2 External clock

6.6 Timing

6.7 Display latch

6.8 Shift register

6.9 Segment outputs

6.10 Backplane outputs

6.11 Display RAM

6.12 Data pointer

6.13 Subaddress counter

6.14 Output bank selector

6.15 Input bank selector

6.16 Blinker

PCF8576

7 CHARACTERISTICS OF THE I2C-BUS

7.1 Bit transfer

7.2 START and STOP conditions

7.3 System configuration

7.4 Acknowledge

7.5 PCF8576 I2C-bus controller

7.6 Input filters

7.7 I2C-bus protocol

7.8 Command decoder

7.9 Display controller

7.10 Cascaded operation
8 LIMITING VALUES
9 HANDLING
10 DC CHARACTERISTICS
11 AC CHARACTERISTICS

11.1 Typical supply current characteristics

11.2 Typical characteristics of LCD outputs
12 APPLICATION INFORMATION

12.1 Chip-on-glass cascadability in single plane
13 BONDING PAD LOCATIONS
14 PACKAGE OUTLINES
15 SOLDERING

15.1 Introduction

15.2 Reflow soldering

15.3 Wave soldering

15.4 Repairing soldered joints
16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS
18 PURCHASE OF PHILIPS I2C COMPONENTS

1998 Feb 06 2

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

1 FEATURES

• Single-chip LCD controller/driver

• Selectable backplane drive configuration: static or 2/3/4

backplane multiplexing

• Selectable display bias configuration: static,1⁄2 or1⁄

• Internal LCD bias generation with voltage-follower

buffers

• 40 segment drives: up to twenty 8-segment numeric
characters; up to ten 15-segment alphanumeric
characters; or any graphics of up to 160 elements

• 40 × 4-bit RAM for display data storage

• Auto-incremented display data loading across device

subaddress boundaries

• Display memory bank switching in static and duplex
drive modes

• Versatile blinking modes

• LCD and logic supplies may be separated

• Wide power supply range: from 2 V for low-threshold

LCDs and up to 9 V for guest-host LCDs and
high-threshold (automobile) twisted nematic LCDs

• Low power consumption

• Power-saving mode for extremely low power

consumption in battery-operated and telephone
applications

2

C-bus interface

• I

• TTL/CMOS compatible

3

PCF8576

• Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers

• May be cascaded for large LCD applications (up to
2560 segments possible)

• Cascadable with 24-segment LCD driver PCF8566

• Optimized pinning for plane wiring in both single and

multiple PCF8576 applications

• Space-saving 56-lead plastic very small outline package
(VSO56)

• Very low external component count (at most one
resistor, even in multiple device applications)

• Compatible with chip-on-glass technology

• Manufactured in silicon gate CMOS process.

2 GENERAL DESCRIPTION

The PCF8576 is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments and can easily be cascaded for larger LCD
applications. The PCF8576 is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I2C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).

3 ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

PCF8576T VSO56 plastic very small outline package; 56 leads SOT190-1
PCF8576U − chip in tray −
PCF8576U/2 − chip with bumps in tray −
PCF8576U/5 − unsawn wafer −
PCF8576U/7 − chip with bumps on tape −
PCF8576U/10 FFC chip on film frame carrier (FFC) −
PCF8576U/12 FFC chip with bumps on film frame carrier (FFC) −

1998 Feb 06 3

PACKAGE

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1998 Feb 06 4

4 BLOCK DIAGRAM

Universal LCD driver for low multiplex

rates

Philips Semiconductors Product specification

V

DD

V

LCD

CLK

SYNC

OSC

V

SS

SCL

SDA

5

R

R

LCD BIAS

R

12

4
3

6

11

2
1

GENERATOR

TIMING BLINKER

OSCILLATOR

INPUT

FILTERS

VOLTAGE

SELECTOR

POWER-

ON

RESET

2

I C - BUS

CONTROLLER

LCD

10

BP014BP215BP116BP3

13

BACKPLANE

OUTPUTS

PCF8576

DISPLAY

CONTROLLER

COMMAND

DECODER

INPUT

BANK

SELECTOR

S0 to S39

40

17 to 56

DISPLAY SEGMENT OUTPUTS

DISPLAY LATCH

SHIFT REGISTER

DISPLAY

RAM

40 x 4 BITS

DATA

POINTER

OUTPUT

BANK

SELECTOR

SUB­ADDRESS
COUNTER

9

SA0

Fig.1 Block diagram (for VSO56 package; SOT190-1).

handbook, full pagewidth

A07A18A2

MBK276

PCF8576

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

5 PINNING

SYMBOL PIN DESCRIPTION

2

SDA 1 I
SCL 2 I
SYNC 3 cascade synchronization input/output
CLK 4 external clock input/output
V

DD

5 supply voltage
OSC 6 oscillator input
A0 to A2 7 to 9 I
SA0 10 I
V
V

SS
LCD

11 logic ground

12 LCD supply voltage
BP0, BP2, BP1 and BP3 13 to 16 LCD backplane outputs
S0 to S39 17 to 56 LCD segment outputs

C-bus serial data input/output

2

C-bus serial clock input

2

C-bus subaddress inputs

2

C-bus slave address input; bit 0

PCF8576

1998 Feb 06 5

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, halfpage

SDA

SCL

SYNC

CLK

V

DD

OSC

A0
A1
A2

SA0

V

SS

V

LCD

BP0
BP2
BP1
BP3

S0
S1
S2
S3
S4
S5
S6
S7
S8

S9
S10
S11

1
2
3
4
5
6
7
8

9
10
11
12
13
14

PCF8576T

15
16
17
18
19
20
21
22
23
24
25
26
27
28

MBK278

PCF8576

56

S39

55

S38

54

S37

53

S36

52

S35

51

S34

50

S33

49

S32

48

S31

47

S30

46

S29

45

S28

44

S27

43

S26

42

S25

41

S24

40

S23

39

S22

38

S21

37

S20

36

S19

35

S18

34

S17

33

S16

32

S15

31

S14

30

S13

29

S12

Fig.2 Pin configuration; SOT190-1.

1998 Feb 06 6

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

6 FUNCTIONAL DESCRIPTION

The PCF8576 is a versatile peripheral device designed to
interface to any microprocessor/microcontroller to a wide
variety of LCDs. It can directly drive any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments. The display configurations possible with
the PCF8576 depend on the number of active backplane
outputs required; a selection of display configurations is
given in Table 1.

All of the display configurations given in Table 1 can be
implemented in the typical system shown in Fig.3.

Table 1 Selection of display configurations

NUMBER OF 7-SEGMENTS NUMERIC

BACKPLANES SEGMENTS DIGITS

4 160 20 20 10 20 160 dots (4 × 40)
3 120 15 15 8 8 120 dots (3 × 40)
2 80 10 10 5 10 80 dots (2 × 40)
1 40 5 5 2 12 40 dots (1 × 40)

INDICATOR

SYMBOLS

PCF8576

The host microprocessor/microcontroller maintains the

2

2-line I
The internal oscillator is selected by connecting pin OSC
to pin VSS. The appropriate biasing voltages for the
multiplexed LCD waveforms are generated internally.
The only other connections required to complete the
system are to the power supplies (VDD, VSS and V
the LCD panel chosen for the application.

C-bus communication channel with the PCF8576.

LCD

14-SEGMENTS

ALPHANUMERIC

DOT MATRIX

CHARACTERS

INDICATOR

SYMBOLS

) and

handbook, full pagewidth

V

DD

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

V

SS

t

r

R

2C

B

SDA
SCL

OSC

R

OSC

V

DD

512

1 17 to 56

2

PCF8576

6

78

A0 A1 A2SSSA0 V

Fig.3 Typical system configuration.

1998 Feb 06 7

V

LCD

13 to 16

91011

40 segment drives

4 backplanes

LCD PANEL

(up to 160
elements)

MBK277

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

6.1 Power-on reset

At power-on the PCF8576 resets to a starting condition as
follows:

1. All backplane outputs are set to VDD.

2. All segment outputs are set to VDD.

3. The drive mode ‘1 : 4 multiplex with1⁄3bias’ is selected.

4. Blinking is switched off.

5. Input and output bank selectors are reset (as defined
in Table 5).

6. The I2C-bus interface is initialized.

7. The data pointer and the subaddress counter are
cleared.

2

Data transfers on the I
following power-on to allow completion of the reset action.

6.2 LCD bias generator

The full-scale LCD voltage (V
VDD− V

. The LCD voltage may be temperature

LCD

compensated externally through the V
Fractional LCD biasing voltages are obtained from an
internal voltage divider of the three series resistors
connected between VDD and V
be switched out of the circuit to provide a1⁄2bias voltage
level for the 1 : 2 multiplex configuration.

C-bus should be avoided for 1 ms

) is obtained from

op

supply to pin 12.

LCD

. The centre resistor can

LCD

PCF8576

6.3 LCD voltage selector

The LCD voltage selector co-ordinates the multiplexing of
the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing

− V

characteristics as functions of V

op=VDD

resulting discrimination ratios (D), are given in Table 2.
A practical value for Vop is determined by equating V

with a defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is Vop>3Vth approximately.

Multiplex drive ratios of 1 : 3 and 1 : 4 with
possible but the discrimination and hence the contrast

ratios are smaller ( = 1.732 for 1 : 3 multiplex or

21

= 1.528 for 1 : 4 multiplex).

---------­3

3

The advantage of these modes is a reduction of the LCD
full-scale voltage V

• 1 : 3 multiplex (
Vop= = 2.449 V

6V

×

as follows:

op

1

⁄2bias):

off rms〈〉

off(rms)

• 1 : 4 multiplex (1⁄2bias):

V

43×()

= = 2.309 V

op

----------------------- ­3

off(rms)

and the

LCD

1

⁄2bias are

off(rms)

These compare with Vop=3V

Table 2 Preferred LCD drive modes: summary of characteristics

NUMBER OF

LCD DRIVE MODE

BACKPLANES LEVELS

CONFIGURATION

static 1 2 static 0 1 ∞

1:2 2 3
1:2 2 4
1:3 3 4
1:4 4 4

1998 Feb 06 8

LCD BIAS

1

⁄

2

1

⁄

3

1

⁄

3

1

⁄

3

when1⁄3bias is used.

off(rms)

V

off(rms)

-------------------- ­V

op

V

on(rms)

-------------------- ­V

op

=

D

0.354 0.791 2.236

0.333 0.745 2.236

0.333 0.638 1.915

0.333 0.577 1.732

V

on(rms)

-------------------- ­V

off(rms)

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

6.4 LCD drive mode waveforms

6.4.1 S
The static LCD drive mode is used when a single

backplane is provided in the LCD. Backplane and
segment drive waveforms for this mode are shown in
Fig.4.

6.4.2 1 : 2
When two backplanes are provided in the LCD, the 1 : 2

multiplex mode applies. The PCF8576 allows use of

1

⁄2bias or1⁄3bias in this mode as shown in Figs 5 and 6.

TATIC DRIVE MODE

MULTIPLEX DRIVE MODE

S

BP0

S

n 1

V

DD

V

LCD

V

DD

n

V

LCD

V

DD

V

LCD

(a) waveforms at driver

V

op

PCF8576

6.4.3 1 : 3
When three backplanes are provided in the LCD, the 1 : 3

multiplex drive mode applies, as shown in Fig.7.

6.4.4 1 : 4
When four backplanes are provided in the LCD, the 1 : 4

multiplex drive mode applies, as shown in Fig.8.

T

frame

MULTIPLEX DRIVE MODE

MULTIPLEX DRIVE MODE

LCD segments

state 1

(on)

state 2

(off)

state 1 0

V

op

V

op

state 2 0

V

op

(b) resultant waveforms

at LCD segment

V

t() V

t() V

t() V

BP0

BP0

t()–=

t()–=

state1

V

on(rms)Vop

t() V

V

state2

V

off(rms)

S

n

=

S

n1+

0V=

Fig.4 Static drive mode waveforms (Vop=VDD− V

1998 Feb 06 9

MBE539

LCD

).

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

V

DD

(V )/2V

BP0

BP1

S

S

n 1

state 1 0

state 2

n

DD LCD

V

LCD

V

DD

(V )/2V

DD

V

LCD

V

DD

V

LCD

V

DD

V

LCD

V

op

V /2

op

V /2

op

V

op

V

op

V /2

op

0

V /2

op

V

op

LCD

(a) waveforms at driver

(b) resultant waveforms

T

frame

at LCD segment

PCF8576

LCD segments

state 1
state 2

MBE540

V

t() V

t() V

op

t() V

op

BP0

BP1

t()–=

t()–=

state1

V

on(rms)

V

state2

V

off(rms)

0.791V

=

t() V

0.354V

=

S

n

S

n

Fig.5 Waveforms for the 1 : 2 multiplex drive mode with1⁄2bias (Vop=VDD− V

1998 Feb 06 10

LCD

).

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

V

DD

V V /3

op

BP0

BP1

S

n

S

n 1

state 1 0

state 2 0

DD
V 2V /3
V

V
V V /3

V 2V /3
V

V
V V /3

V 2V /3
V

V
V V /3

V 2V /3
V

DD

LCD

DD

DD

DD

LCD

DD

DD

DD

LCD

DD

DD

DD

LCD

V

op

2V /3

op

V /3

op

V /3

op

2V /3

op

V

op

V

op

2V /3

op

V /3

op

V /3

op

2V /3

op

V

op

op

op

op

op

op

op

op

(a) waveforms at driver

(b) resultant waveforms

T

frame

at LCD segment

PCF8576

LCD segments

state 1
state 2

MBE541

V

t() V

t() V

op

t() V

op

BP0

BP1

t()–=

t()–=

state1

V

on(rms)

V

state2

V

off(rms)

0.745V

=

t() V

0.333V

=

S

n

S

n

Fig.6 Waveforms for the 1 : 2 multiplex drive mode with1⁄3bias (Vop=VDD− V

1998 Feb 06 11

LCD

).

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

T

V

DD

V V /3

op

n

DD
V 2V /3
V

V
V V /3

V 2V /3
V

V
V V /3

V 2V /3
V

V
V V /3

V 2V /3
V

V
V V /3

V 2V /3
V

V
V V /3

V 2V /3
V

DD

LCD

DD

DD

DD

LCD

DD

DD

DD

LCD

DD

DD

DD

LCD

DD

DD

DD

LCD

DD

DD

DD

LCD

V

op

2V /3

op

V /3

op

V /3

op

2V /3

op

V

op

V

op

2V /3

op

V /3

op

V /3

op

2V /3

op

V

op

op

op

op

op

op

op

op

op

op

op

op

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

V

state1

V

on(rms)

V

state2

V

off(rms)

t() V

0.638V

=

t() V

0.333V

=

S

S

t() V

n

t() V

n

op

op

BP0

BP1

BP2/S23

S

S

n 1

S

n 2

state 1 0

state 2 0

t()–=

BP0

t()–=

BP1

PCF8576

frame

LCD segments

state 1
state 2

MBE542

Fig.7 Waveforms for the 1 : 3 multiplex drive mode (Vop=VDD− V

1998 Feb 06 12

LCD

).

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

T

V

DD

V V /3

n

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

op

2V /3

op

V /3

op

V /3

op

2V /3

op

V

op

V

op

2V /3

op

V /3

op

V /3

op

2V /3

op

V

op

BP0

BP1

BP2

BP3

S

S

n 1

S

n 2

S

n 3

state 1 0

state 2 0

op

op

op

op

op

op

op

op

op

op

op

op

op

op

op

op

frame

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

state 1
state 2

LCD segments

MBE543

V

state1

V

on(rms)

V

state2

V

off(rms)

PCF8576

t() V

t() V

S

n

0.577V

=

t() V

t() V

S

n

0.333V

=

t()–=

BP0

op

t()–=

BP1

op

Fig.8 Waveforms for the 1 : 4 multiplex drive mode (Vop=VDD− V

1998 Feb 06 13

LCD

).

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

6.5 Oscillator

6.5.1 I
The internal logic and the LCD drive signals of the

PCF8576 are timed either by the internal oscillator or from
an external clock. When the internal oscillator is used,
pin OSC should be connected to pin VSS. In this event, the
output from pin CLK provides the clock signal for
cascaded PCF8566s in the system.

Where resistor R
is selected. The relationship between the oscillator
frequency on pin CLK (f

NTERNAL CLOCK

3

10

f

clk

(kHz)

to VSS is present, the internal oscillator

osc

) and R

clk

is shown in Fig.9.

osc

MBE531

PCF8576

6.6 Timing

The timing of the PCF8576 organizes the internal data flow
of the device. This includes the transfer of display data
from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal
SYNC maintains the correct timing relationship between
the PCF8576s in the system. The timing also generates
the LCD frame frequency which it derives as an integer
multiple of the clock frequency (see Table 3). The frame
frequency is set by the MODE SET commands when
internal clock is used, or by the frequency applied to
pin CLK when external clock is used.

The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power-saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.
The lower clock frequency has the disadvantage of
increasing the response time when large amounts of
display data are transmitted on the I

2

C-bus.

2

10

10

2

10



3.4 107×



f

----------------------- -

clk

R



osc

Fig.9 Oscillator frequency as a function of R

6.5.2 E

XTERNAL CLOCK

max

min

3

10

kHz()≈

R(kΩ)

osc

4

10

.

osc

The condition for external clock is made by connecting
pin OSC to pin VDD; pin CLK then becomes the external
clock input.

The clock frequency (f

) determines the LCD frame

clk

frequency and the maximum rate for data reception from
the I2C-bus. To allow I2C-bus transmissions at their
maximum data rate of 100 kHz, f

should be chosen to be

clk

above 125 kHz.
A clock signal must always be supplied to the device;

removing the clock may freeze the LCD in a DC state.

When a device is unable to digest a display data byte
before the next one arrives, it holds the SCL line LOW until
the first display data byte is stored. This slows down the
transmission rate of the I2C-bus but no data loss occurs.

Table 3 LCD frame frequencies

NOMINAL

PCF8576 MODE

FRAME

FREQUENCY

FRAME

FREQUENCY

(Hz)

f

Normal mode

Power-saving mode 64

clk

------------ ­2880

f

clk

--------- ­480

64

6.7 Display latch

The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.

6.8 Shift register

The shift register serves to transfer display information
from the display RAM to the display latch while previous
data is displayed.

1998 Feb 06 14

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

6.9 Segment outputs

The LCD drive section includes 40 segment outputs
pins S0 to S39 which should be connected directly to the
LCD. The segment output signals are generated in
accordance with the multiplexed backplane signals and
with data resident in the display latch. When less than
40 segment outputs are required the unused segment
outputs should be left open-circuit.

6.10 Backplane outputs

The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open-circuit. In the 1 : 3 multiplex drive mode
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be connected together to give
enhanced drive capabilities. In the 1 : 2 multiplex drive
mode BP0 and BP2, BP1 and BP3 respectively carry the
same signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.

6.11 Display RAM

The display RAM is a static 40 × 4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the on
state of the corresponding LCD segment; similarly, a
logic 0 indicates the off state. There is a one-to-one

PCF8576

correspondence between the RAM addresses and the
segment outputs, and between the individual bits of a RAM
word and the backplane outputs. The first RAM column
corresponds to the 40 segments operated with respect to
backplane BP0 (see Fig.10). In multiplexed LCD
applications the segment data of the second, third and
fourth column of the display RAM are time-multiplexed
with BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8576 the
display bytes received are stored in the display RAM in
accordance with the selected LCD drive mode.
To illustrate the filling order, an example of a 7-segment
numeric display showing all drive modes is given in Fig.11;
the RAM filling organization depicted applies equally to
other LCD types.

With reference to Fig.11, in the static drive mode the eight
transmitted data bits are placed in bit 0 of eight successive
display RAM addresses. In the 1 : 2 multiplex drive mode
the eight transmitted data bits are placed in bits 0 and 1 of
four successive display RAM addresses. In the 1 : 3
multiplex drive mode these bits are placed in
bits 0, 1 and 2 of three successive addresses, with bit 2 of
the third address left unchanged. This last bit may, if
necessary, be controlled by an additional transfer to this
address but care should be taken to avoid overriding
adjacent data because full bytes are always transmitted.
In the 1 : 4 multiplex drive mode the eight transmitted data
bits are placed in bits 0, 1, 2 and 3 of two successive
display RAM addresses.

display RAM addresses (rows) / segment outputs (S)

1234 3536373839

0

0

display RAM bits

(columns) /

backplane outputs

(BP)

1
2
3

MBE525

Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,

and between bits in a RAM word and backplane outputs.

1998 Feb 06 15

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

6.12 Data pointer

The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM. The sequence
commences with the initialization of the data pointer by the
LOAD DATA POINTER command. Following this, an
arriving data byte is stored starting at the display RAM
address indicated by the data pointer thereby observing
the filling order shown in Fig.11. The data pointer is
automatically incremented in accordance with the chosen
LCD configuration. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode), by four (1 : 2 multiplex drive mode) or
by two (1 : 4 multiplex drive mode).

6.13 Subaddress counter

The storage of display data is conditioned by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to A0, A1
and A2. The subaddress counter value is defined by the
DEVICE SELECT command. If the contents of the
subaddress counter and the hardware subaddress do not
agree then data storage is inhibited but the data pointer is
incremented as if data storage had taken place.
The subaddress counter is also incremented when the
data pointer overflows.

The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are sent to the display RAM,
automatic wrap-over to the next PCF8576 occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character (such as during the 14th display data byte
transmitted in 1 : 3 multiplex mode).

PCF8576

The PCF8576 includes a RAM bank switching feature in
the static and 1 : 2 multiplex drive modes. In the static
drive mode, the BANK SELECT command may request
the contents of bit 2 to be selected for display instead of
bit 0 contents. In the 1 : 2 drive mode, the contents of
bits 2 and 3 may be selected instead of bits 0 and 1.
This gives the provision for preparing display information
in an alternative bank and to be able to switch to it once it
is assembled.

6.15 Input bank selector

The input bank selector loads display data into the display
RAM in accordance with the selected LCD drive
configuration. Display data can be loaded in bit 2 in static
drive mode or in bits 2 and 3 in 1 : 2 drive mode by using
the BANK SELECT command. The input bank selector
functions independent of the output bank selector.

6.16 Blinker

The display blinking capabilities of the PCF8576 are very
versatile. The whole display can be blinked at frequencies
selected by the BLINK command. The blinking frequencies
are integer multiples of the clock frequency; the ratios
between the clock and blinking frequencies depend on the
mode in which the device is operating, as shown in
Table 4.

An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and
1 : 2 LCD drive modes and can be implemented without
any communication overheads. By means of the output
bank selector, the displayed RAM banks are exchanged
with alternate RAM banks at the blinking frequency.
This mode can also be specified by the BLINK command.

In the 1 : 3 and 1 : 4 multiplex modes, where no alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.

6.14 Output bank selector

This selects one of the four bits per display RAM address
for transfer to the display latch. The actual bit chosen
depends on the particular LCD drive mode in operation
and on the instant in the multiplex sequence. In 1 : 4
multiplex, all RAM addresses of bit 0 are the first to be
selected, these are followed by the contents of bit 1, bit 2
and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2
are selected sequentially. In 1 : 2 multiplex, bits 0 and 1
are selected and, in the static mode, bit 0 is selected.

1998 Feb 06 16

If the entire display is to be blinked at a frequency other
than the nominal blinking frequency, this can be effectively
performed by resetting and setting the display enable bit E
at the required rate using the MODE SET command.

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

Table 4 Blinking frequencies

BLINKING MODE

Off −−blinking off

2Hz 2Hz

1Hz 1Hz

0.5 Hz 0.5 Hz

NORMAL OPERATING

MODE RATIO

f

clk

---------------­92160

f

clk

------------------- ­184320

f

clk

------------------- ­368640

POWER-SAVING MODE

RATIO

f

clk

---------------­15360

f

clk

---------------­30720

f

clk

---------------­61440

PCF8576

NOMINAL BLINKING

FREQUENCY

1998 Feb 06 17

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1998 Feb 06 18

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

rates

drive mode

static

1 : 2

multiplex

1 : 3

multiplex

1 : 4

multiplex

LCD segments LCD backplanes display RAM filling order transmitted display byte

S

n

S

n

S

n

S

n

S

n

S

n

S

n

S

n

S

n

S

n

S

n

a

2

3

4

5

6

S

n

1

2

3

1

2

S

n

1

b

f

g

e

c

d

a

b

f

g

e

c

d

a

b

f

g

e

c

d

a

b

f

g

e

c

d

BP0

S

1

n

S

n

S

7

n

DP

BP0

bit/
BP

bit/

BP1

DP

BP0

S

n

BP

bit/
BP

DP

BP1

BP0

BP2

BP2

bit/
BP

BP1

DP

BP3

n1

n

c

0

x

1

x

2

x

3

n

a

0

b

1

x

2

x

3

n

b

0

DP

1

c

2

x

3

n

a

0

c

1

b

2

DP

3

n2 n3 n4 n5 n6 n7

b

a

f

g

e

x

x

x

x
x
x

n1

f
g
x
x

n1

a
d
g
x

x

x

x

x

n2 n3

e

d

c

DP

x

x

x

x

n2

f
e
x
x

x

x

x

x

x

n1

f
e
g
d

d

DP

x

x

x

x

x

x

MSB LSB

cbaf gedDP

MSB LSB

abf gecdDP

MSB LSB

bDPcadgf e

MSB LSB

acbDPf egd

x = data bit unchanged.

Fig.11 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus.

handbook, full pagewidth

MBK389

PCF8576

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

7 CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.

7.1 Bit transfer (see Fig.12)
One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.

7.2 START and STOP conditions (see Fig.13)
Both data and clock lines remain HIGH when the bus is not

busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).

7.3 System configuration (see Fig.14)

PCF8576

7.5 PCF8576 I

The PCF8576 acts as an I2C-bus slave receiver. It does
not initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the PCF8576
are the acknowledge signals of the selected devices.
Device selection depends on the I2C-bus slave address,
on the transferred command data and on the hardware
subaddress.

In single device application, the hardware subaddress
inputs A0, A1 and A2 are normally connected to VSS which
defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are connected to VSS or VDD in
accordance with a binary coding scheme such that no two
devices with a common I2C-bus slave address have the
same hardware subaddress.

In the power-saving mode it is possible that the PCF8576
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8576 forces the SCL line to LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I2C-bus and
serves to slow down fast transmitters. Data loss does not
occur.

2

C-bus controller

A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.

7.4 Acknowledge (see Fig.15)
The number of data bytes transferred between the START

and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.

7.6 Input filters

To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.

7.7 I

Two I2C-bus slave addresses (0111000 and 0111001) are
reserved for the PCF8576. The least significant bit of the
slave address that a PCF8576 will respond to is defined by
the level connected at its input pin SA0. Therefore, two
types of PCF8576 can be distinguished on the same
I2C-bus which allows:

• Up to 16 PCF8576s on the same I2C-bus for very large

• The use of two types of LCD multiplex on the same

The I2C-bus protocol is shown in Fig.16. The sequence is
initiated with a START condition (S) from the I2C-bus
master which is followed by one of the two PCF8576 slave
addresses available. All PCF8576s with the corresponding
SA0 level acknowledge in parallel with the slave address
but all PCF8576s with the alternative SA0 level ignore the
whole I2C-bus transfer.

2

C-bus protocol

LCD applications

I2C-bus.

1998 Feb 06 19

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

After acknowledgement, one or more command bytes (m)
follow which define the status of the addressed PCF8576s.

The last command byte is tagged with a cleared most
significant bit, the continuation bit C. The command bytes
are also acknowledged by all addressed PCF8576s on the
bus.

After the last command byte, a series of display data bytes
(n) may follow. These display bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data is directed to the intended PCF8576 device.
The acknowledgement after each byte is made only by the
(A0, A1 and A2) addressed PCF8576. After the last display
byte, the I2C-bus master issues a STOP condition (P).

PCF8576

7.8 Command decoder

The command decoder identifies command bytes that
arrive on the I
continuation bit C in their most significant bit position
(Fig.17). When this bit is set, it indicates that the next byte
of the transfer to arrive will also represent a command.
If this bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.

The five commands available to the PCF8576 are defined
in Table 5.

2

C-bus. All available commands carry a

handbook, full pagewidth

SDA

SCL

SDA

SCL

S

START condition

data line

stable;

data valid

change
of data

allowed

Fig.12 Bit transfer.

MBA607

P

STOP condition

SDA

SCL

MBC622

Fig.13 Definition of START and STOP conditions.

1998 Feb 06 20

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

SLAVE

TRANSMITTER/

RECEIVER

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

PCF8576

MGA807

handbook, full pagewidth

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

S

START

condition

Fig.14 System configuration.

not acknowledge

acknowledge

acknowledgement

9821

clock pulse for

MBC602

Fig.15 Acknowledgement on the I2C-bus.

1998 Feb 06 21

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, full pagewidth

slave address

S

011100 0AC

S

A

0

/RW

acknowledge by

all addressed

PCF8576s

COMMAND

PCF8576

acknowledge

by A0, A1 and A2

selected

PCF8576 only

A

n 0 byte(s)n 1 byte(s)1 byte

MBK279

ADISPLAY DATA

P

update data pointers

and if necessary,

subaddress counter

C = 0; last command.
C = 1; commands continue.

Fig.16 I2C-bus protocol.

MSB LSB

C

REST OF OPCODE

MSA833

Fig.17 General format of command byte.

1998 Feb 06 22

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

Table 5 Definition of PCF8576 commands

COMMAND OPCODE OPTIONS DESCRIPTION

MODE SET C 1 0 LP E B M1 M0 Table 6 Defines LCD drive mode.

Table 7 Defines LCD bias configuration.
Table 8 Defines display status. The possibility to disable the

display allows implementation of blinking under
external control.

Table 9 Defines power dissipation mode.

LOAD DATA
POINTER

DEVICE
SELECT

BANK
SELECT

BLINK C 1 1 1 0 A BF1 BF0 Table 14 Defines the blinking frequency.

C 0 P5 P4 P3 P2 P1 P0 Table 10 Six bits of immediate data, bits P5 to P0, are

transferred to the data pointer to define one of forty
display RAM addresses.

C 1 1 0 0 A2 A1 A0 Table 11 Three bits of immediate data, bits A2 to A0, are

transferred to the subaddress counter to define one of
eight hardware subaddresses.

C11110 I O Table 12 Defines input bank selection (storage of arriving

display data).

T able 13 Defines output bank selection (retrieval of LCD display

data). The BANK SELECT command has no effect in
1 : 3 and 1 : 4 multiplex drive modes.

Table 15 Selects the blinking mode; normal operation with

frequency set by BF1, BF0 or blinking by alternation of
display RAM banks. Alternation blinking does not
apply in 1 : 3 and 1 : 4 multiplex drive modes.

PCF8576

Table 6 MODE SET option 1

LCD DRIVE MODE BITS

DRIVE MODE BACKPLANE M1 M0

Static 1 BP 0 1
1 : 2 MUX (2 BP) 1 0
1 : 3 MUX (3 BP) 1 1
1 : 4 MUX (4 BP) 0 0

Table 7 MODE SET option 2

LCD BIAS BIT B

1

⁄3bias 0

1

⁄2bias 1

Table 8 MODE SET option 3

DISPLAY STATUS BIT E

Disabled (blank) 0
Enabled 1

Table 9 MODE SET option 4

MODE BIT LP

Normal mode 0
Power-saving mode 1

Table 10 LOAD DATA POINTER option 1

DESCRIPTION BITS

6-bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0

Table 11 DEVICE SELECT option 1

DESCRIPTION BITS

3-bit binary value of 0 to 7 A2 A1 A0

Table 12 BANK SELECT option 1

STATIC 1 : 2 MUX BIT I

RAM bit 0 RAM bits 0 and 1 0
RAM bit 2 RAM bits 2 and 3 1

1998 Feb 06 23

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

Table 13 BANK SELECT option 2

STATIC 1 : 2 MUX BIT O

RAM bit 0 RAM bits 0 and 1 0
RAM bit 2 RAM bits 2 and 3 1

Table 14 BLINK option 1

BITS

BLINK FREQUENCY

BF1 BF0

Off 0 0
2Hz 0 1
1Hz 1 0

0.5 Hz 1 1

Table 15 BLINK option 2

BLINK MODE BIT A

Normal blinking 0
Alternation blinking 1

7.9 Display controller

The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8576 and co-ordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.

PCF8576

7.10 Cascaded operation

In large display configurations, up to 16 PCF8576s can be
distinguished on the same I2C-bus by using the 3-bit
hardware subaddress (A0, A1 and A2) and the
programmable I2C-bus slave address (SA0). When
cascaded PCF8576s are synchronized so that they can
share the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodes of the display. The other PCF8576s of the
cascade contribute additional segment outputs but their
backplane outputs are left open-circuit (see Fig.18).

SYNC line is provided to maintain the correct

The
synchronization between all cascaded PCF8576s.
This synchronization is guaranteed after the Power-on
reset. The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when PCF8576s with differing SA0 levels
are cascaded). SYNC is organized as an input/output pin;
the output selection being realized as an open-drain driver
with an internal pull-up resistor. A PCF8576 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times. Should
synchronization in the cascade be lost, it will be restored
by the first PCF8576 to assert SYNC. The timing
relationship between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8576
are shown in Fig.19.

1998 Feb 06 24

For single plane wiring of packaged PCF8576s and
chip-on-glass cascading, see Chapter 12.

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, full pagewidth

SDA
SCL

SYNC

CLK
OSC

V

LCD

V

DDVLCD

512

1
2
3

PCF8576

4
6

7 8 9 10 11

A0 A1 A2 SA0 V

17 to 56

13, 15
14, 16

PCF8576

40 segment drives

LCD PANEL

(up to 2560

elements)
BP0 to BP3
(open-circuit)

SS

V

DD

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

V

SS

t

r

R

2C

B

SDA

SCL

SYNC

CLK

OSC

V

512

1

2
3
4
6

78

A0 A1 A2SSSA0 V

DD

PCF8576

91011

V

LCD

17 to 56

13, 15
14, 16

40 segment drives

4 backplanes

BP0 to BP3

MBK280

Fig.18 Cascaded PCF8576 configuration.

1998 Feb 06 25

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, full pagewidth

BP0

SYNC

BP1

(1/2 bias)

BP1

(1/3 bias)

T=

framefframe

(a) static drive mode.

PCF8576

1

SYNC

BP2

SYNC

BP3

SYNC

(b) 1 : 2 multiplex drive mode.

(c) 1 : 3 multiplex drive mode.

MBE535

(d) 1 : 4 multiplex drive mode.

Excessive capacitive coupling between SCL or CLK and SYNC may cause erroneous synchronization. If this proves to be a problem, the capacitance

SYNC line should be increased (e.g. by an external capacitor between SYNC and VDD). Degradation of the positive edge of the SYNC pulse may

of the
be countered by an external pull-up resistor.

Fig.19 Synchronization of the cascade for the various PCF8576 drive modes.

1998 Feb 06 26

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

PCF8576

rates

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

V

LCD

V

I

V

O

I

I

I

O

I

, ISS, I

DD

P

tot

P

O

T

stg

9 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see

supply voltage −0.5 +11.0 V
LCD supply voltage VDD− 11.0 V

DD

input voltage SDA, SCL, CLK, SYNC, SA0, OSC, A0 to A2 VSS− 0.5 VDD+ 0.5 V
output voltage S0 to S39, BP0 to BP3 V

− 0.5 VDD+ 0.5 V

LCD

DC input current − 20 mA
DC output current − 25 mA

LCDVDD

, VSS or V

current − 50 mA

LCD

total power dissipation − 400 mW
power dissipation per output − 100 mW
storage temperature −65 +150 °C

“Handling MOS Devices”

V

).

1998 Feb 06 27

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

PCF8576

rates

10 DC CHARACTERISTICS

V

= 2 to 9 V; VSS=0V; V

DD

LCD=VDD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DD

V

LCD

I

DD

supply voltage 2 − 9V
LCD supply voltage note 1 VDD− 9 − VDD− 2V
supply current note 2

normal mode f
power-saving mode f

Logic

V

IL

V

IH

V

OL

V

OH

I

OL1

LOW-level input voltage V
HIGH-level input voltage 0.7V
LOW-level output voltage IOL=0mA −−0.05 V
HIGH-level output voltage IOH=0mA VDD− 0.05 −− V
LOW-level output current

CLK, SYNC

I

OH1

I

OL2

HIGH-level output current CLK VOH=4V; VDD=5V 1 −− mA
LOW-level output current

SDA and SCL

I

L1

leakage current SA0, A0 to A2,
CLK, SDA and SCL

I

L2

I

pd

leakage current OSC VI=V
A0, A1, A2 and OSC pull-down

current
R
V
C

SYNC

POR

I

pull-up resistor (SYNC) 20 50 150 kΩ

Power-on reset voltage level note 3 − 1.0 1.6 V

input capacitance note 4 −−7pF

LCD outputs

V

BP

V

S

R

BP

R

S

DC voltage component BP0 to BP3 CBP=35nF − 20 − mV

DC voltage component S0 to S39 CS=5nF − 20 − mV

output resistance BP0 to BP3 note 5; V

output resistance S0 to S39 note 5; V

− 2VtoVDD− 9 V; T

= 200 kHz −−180 µA

clk

= 35 kHz; VDD= 3.5 V;

clk

V

= 0 V; A0, A1 and A2

LCD

connected to V

VOL=1V; VDD=5V 1 −− mA

VOL= 0.4 V; VDD=5V 3 −− mA

VI=VDD or V

DD

VI=1V; VDD= 5 V 20 50 150 µA

= −40 to +85 °C; unless otherwise specified.

amb

−−60 µA

SS

− 0.3V

− V

SS

SS

DD

−−1µA

−−1µA

LCD=VDD
LCD=VDD

− 5V −−5kΩ

− 5V −−7.5 kΩ

DD

DD

V
V

Notes

1. V

≤ VDD− 3 V for1⁄3bias.

LCD

2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.

3. Resets all logic when VDD<V

POR

.

4. Periodically sampled, not 100% tested.

5. Outputs measured one at a time.

1998 Feb 06 28

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

PCF8576

rates

11 AC CHARACTERISTICS

V

= 2 to 9 V; VSS=0V; V

DD

LCD=VDD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

f

clk

oscillator frequency on pin CLK

normal mode V
power-saving mode V

t

clkH

t

clkL

t

PSYNC

t

SYNCL

t

PLCD

Timing characteristics: I

t

SW

t

BUF

t

HD;STA

t

SU;STA

t

LOW

t

HIGH

t

r

t

f

C

B

t

SU;DAT

t

HD;DAT

t

SU;STO

CLK HIGH time see Fig.21 1 −−µs

CLK LOW time 1 −−µs

SYNC propagation delay time −−400 ns

SYNC LOW time 1 −−µs

driver delays with test loads V

2

C-bus; note 2; see Fig.22

tolerable spike width on bus −−100 ns

bus free time 4.7 −−µs

START condition hold time 4.0 −−µs

set-up time for a repeated START condition 4.7 −−µs

SCL LOW time 4.7 −−µs

SCL HIGH time 4.0 −−µs

SCL and SDA rise time −−1µs

SCL and SDA fall time −−0.3 µs

capacitive bus line load −−400 pF

data set-up time 250 −−ns

data hold time 0 −−ns

set-up time for STOP condition 4.0 −−µs

− 2VtoVDD− 9 V; T

= −40 to +85 °C; unless otherwise specified.

amb

= 5 V; note 1 125 200 288 kHz

DD

= 3.5 V 21 31 48 kHz

DD

LCD=VDD

− 5 V; see Fig.20 −−30 µs

Notes

1. At f

< 125 kHz, I2C-bus maximum transmission speed is derated.

clk

2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSSto VDD.

SYNC

CLK

BP0 to BP3, and
S0 to S39

Ω6.8

V

(2%)

DD

Ω3.3 k Ω1.5 k

0.5V

DD

1 nF

V

DD

SDA,
SCL

V

(2%)(2%)

DD

MBE544

Fig.20 Test loads.

1998 Feb 06 29

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, full pagewidth

CLK

SYNC

BP0 to BP3,

and S0 to S39

t

clkH

1/ f

clk

t

PSYNC

t

clkL

t

t

PLCD

t

PSYNC

SYNCL

MBE545

0.7V

DD

0.3V

DD

0.7V

DD

0.3V

DD

0.5 V
(VDD = 5 V)

0.5 V

PCF8576

dbook, full pagewidth

SDA

SCL

SDA

MGA728

t

BUF

Fig.21 Driver timing waveforms.

t

LOW

t

HD;STA

t

r

t

SU;STA

t

HD;DAT

t

HIGH

t

f

t

SU;DAT

t

SU;STO

Fig.22 I2C-bus timing waveforms.

1998 Feb 06 30

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

11.1 Typical supply current characteristics

50

I

SS

(µA)

40

30

20

10

0

0 200

normal
mode

100

power-saving
mode

f (Hz)

frame

MBE530

50

I

LCD

(µA)

40

30

20

10

0

0 200

100

f (Hz)

PCF8576

MBE529

frame

VDD= 5 V; V

Fig.23 −ISS as a function of f

50

handbook, halfpage

I

SS

(µA)

40

30

20

10

0

010

LCD

= 0 V; T

=25°C.

amb

normal mode

f = 200 kHz

clk

power-saving mode

f = 35 kHz

clk

5

V (V)

DD

frame

MBE528 - 1

VDD= 5 V; V

.

50

handbook, halfpage

I

LCD

(µA)

40

30

20

10

= 0 V; T

LCD

Fig.24 −I

0

010

=25°C.

amb

as a function of f

LCD

85 C

25 C

5

o

o

o

40 C

frame

V (V)

DD

.

MBE527 - 1

V

= 0 V; external clock; T

LCD

amb

=25°C.

Fig.25 ISS as a function of VDD.

1998 Feb 06 31

V

= 0 V; external clock; f

LCD

Fig.26 I

= nominal frequency.

clk

as a function of VDD.

LCD

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

11.2 Typical characteristics of LCD outputs

S

BP

V (V)

DD

MBE532 - 1

60

10

handbook, halfpage

R

O(max)
(kΩ)

1

-1

10

R

R

3

R

O(max)

(kΩ)

PCF8576

2.5

2.0

1.5

1.0

0.5

0

40 0 40 120

R

S

R

BP

80

T

amb

MBE526

o

( C)

V

LCD

= 0 V; T

=25°C.

amb

Fig.27 R

as a function of VDD.

O(max)

VDD= 5 V; V

=0V.

LCD

Fig.28 R

as a function of T

O(max)

amb

.

1998 Feb 06 32

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1998 Feb 06 33

book, full pagewidth

SDA
SCL

SYNC
CLK

V

DD

V

SS

V

LCD

12 APPLICATION INFORMATION

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

rates

SDA
SCL

SYNC

CLK

V

DD

OSC

A0
A1
A2

SA0
V

SS

V

LCD
BP0

BP2
BP1
BP3

S0
S1
S2
S3

S7
S8

S9
S10
S11

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

24
25
26
27
28

PCF8576T

56

S39

55

S38

54

S37

53

S36

52

S35

51

S34

50

S33

49

S32

48

S31

47

S30

46

S29

45

S28

44

S27

43

S26

42

S25

41

S24

40

S23

39

S22

38

S21

S17

34

S16

33
32

S15

31

S14

30

S13

29

S12

open

BP0
BP2
BP1
BP3
S40
S41
S42
S43

S47
S48
S49
S50
S51

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

24
25
26
27
28

PCF8576T

56

S79

55

S78

54

S77

53

S76

52

S75

51

S74

50

S73

49

S72

48

S71

47

S70

46

S69

45

S68

44

S67

43

S66

42

S65

41

S64

40

S63

39

S62

38

S61

S57

34

S56

33
32

S55

31

S54

30

S53

29

S52

PCF8576

S10 S11S0 S79

backplanes segments

Fig.29 Single plane wiring of packaged PCF8576Ts.

S50S39 S40S13S12

S51 S52 S53

MBK281

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

12.1 Chip-on-glass cascadability in single plane

In chip-on-glass technology, where driver devices are
bonded directly onto glass of the LCD, it is important that
the devices may be cascaded without the crossing of
conductors, but the paths of conductors can be continued
on the glass under the chip. All of this is facilitated by the
PCF8576 bonding pad layout (see Fig.30). Pads needing
bus interconnection between all PCF8576s of the cascade
are VDD, VSS, V
lines may be led to the corresponding pads of the next
PCF8576 through the wide opening between V

13 BONDING PAD LOCATIONS

handbook, full pagewidth

, CLK, SCL, SDA and SYNC. These

LCD

S17

S16

S15

35

S18

36

S19

37

S20

38

S21

39

S22

40

S23

41

S24

42

S25

4.12
mm

S26
S27
S28
S29
S30
S31

S32

S33

43

44

45

46

47

48

49

50

51

52 53 54 55 56

LCD

S14

pad

S13

x

PCF8576

and the backplane output pads. The only bus line that does
not require a second opening to lead through to the next
PCF8576 is V
of V

adjacent to VSS allows the two supplies to be

LCD

connected together.
When an external clocking source is to be used, OSC of all

devices should be connected to VDD.
The pads OSC, A0, A1, A2 and SA0 have been placed
between VSSand VDD to facilitate wiring of oscillator,
hardware subaddress and slave address.

S12

S11

S10S9S8

0

0

y

PCF8576

1 2 3 4 5 6 7

, being the cascade centre. The placing

LCD

S7

S6

S5

S4

2122232425262728293031323334

20

S3

19

S2

18

S1

17

S0

16

BP3

15

BP1

14

BP2

13

BP0

cascade

centre

V

12

LCD

V

11

SS

10

SA0

9

A2

8

S39

S38

S37

S36

S35

S34

3.07 mm

Bonding pad dimensions: 120 × 120 µm.

Fig.30 Bonding pad locations.

1998 Feb 06 34

SDA

SCL

SYNC

CLK

OSC

A0

MBK282

DD

V

A1

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

Table 16 Bonding pad locations (dimensions in µm)
All x/y coordinates are referenced to centre of chip

(see Fig.30).

SYMBOL PAD x y

SDA 1 −155 −1900
SCL 2 45 −1900
SYNC 3 245 −1900
CLK 4 445 −1900
V

DD

OSC 6 865 −1900
A0 7 1105 −1900
A1 8 1375 −1900
A2 9 1375 −1700
SA0 10 1375 −1500
V

SS

V

LCD

BP0 13 1375 300
BP2 14 1375 500
BP1 15 1375 700
BP3 16 1375 900
S0 17 1375 1100
S1 18 1375 1300
S2 19 1375 1500
S3 20 1375 1700
S4 21 1375 1900
S5 22 1105 1900
S6 23 865 1900
S7 24 645 1900
S8 25 445 1900
S9 26 245 1900
S10 27 45 1900
S11 28 −155 1900

5 645 −1900

11 1375 −1300

12 1375 −1100

PCF8576

SYMBOL PAD x y

S12 29 −355 1900
S13 30 −555 1900
S14 31 −755 1900
S15 32 −955 1900
S16 33 −1155 1900
S17 34 −1375 1900
S18 35 −1375 1660
S19 36 −1375 1420
S20 37 −1375 1200
S21 38 −1375 1000
S22 39 −1375 800
S23 40 −1375 600
S24 41 −1375 400
S25 42 −1375 200
S26 43 −1375 −200
S27 44 −1375 −400
S28 45 −1375 −600
S29 46 −1375 −800
S30 47 −1375 −1000
S31 48 −1375 −1200
S32 49 −1375 −1420
S33 50 −1375 −1660
S34 51 −1375 −1900
S35 52 −1155 −1900
S36 53 −955 −1900
S37 54 −755 −1900
S38 55 −555 −1900
S39 56 −355 −900

1998 Feb 06 35

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

14 PACKAGE OUTLINE

VSO56: plastic very small outline package; 56 leads

D

y

Z

56

PCF8576

SOT190-1

E

c

H

E

29

A

X

v M

A

pin 1 index

281

w M

b

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

A

max.

3.3

0.13

1

0.3

0.1

0.012

0.004

A2A3b

3.0

0.25

2.8

0.12

0.01

0.11

p

0.42

0.30

0.017

0.012

0.22

0.14

0.0087

0.0055

UNIT A

inches

Note

1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

(1)E(2)

cD

21.65

21.35

0.85

0.84

p

scale

eHELLpQZywv θ

11.1

0.75

11.0

0.44

0.0295

0.43

15.8

15.2

0.62

0.60

2.25

0.089

Q

A

2

A

1

1.6

1.4

0.063

0.055

detail X

1.45

0.2

1.30

0.057

0.008 0.004

0.051

L

p

L

0.1 0.1

0.004

(A )

A

3

θ

(1)

0.90

0.55

0.035

0.022

o

7

o

0

OUTLINE
VERSION

SOT190-1

IEC JEDEC EIAJ

REFERENCES

1998 Feb 06 36

EUROPEAN

PROJECTION

ISSUE DATE

96-04-02
97-08-11

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

15 SOLDERING

15.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

15.2 Reflow soldering

Reflow soldering techniques are suitable for all VSO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

(order code 9398 652 90011).

PCF8576

15.3 Wave soldering

Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1998 Feb 06 37

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

PCF8576

rates

16 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

18 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1998 Feb 06 38

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

NOTES

PCF8576

1998 Feb 06 39

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
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Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
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India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
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Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 415106/1200/03/pp40 Date of release: 1998 Feb 06 Document order number: 9397 750 03252