Datasheet PCF85116-3P-01, PCF85116-3T-01, PCF85116-3W-01-280 Datasheet (Philips)

Page 1
DATA SH EET
Product specification Supersedes data of 1997 Feb 24 File under Integrated Circuits, IC12
1997 Apr 02
INTEGRATED CIRCUITS
PCF85116-3
2048 × 8-bit CMOS EEPROM with I
2
C-bus interface
Page 2
1997 Apr 02 2
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF85116-3
CONTENTS
1 FEATURES 2 DESCRIPTION
2.1 Remark 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 DEVICE SELECTION 6 BLOCK DIAGRAM 7 PINNING 8I
2
C-BUS PROTOCOL
8.1 Bus conditions
8.2 Data transfer
8.3 Device addressing
8.4 Write operations
8.4.1 Byte/word write
8.4.2 Page Write
8.4.3 Remark
8.5 Read operations
8.5.1 Remark
9 LIMITING VALUES 10 CHARACTERISTICS 11 I2C-BUS CHARACTERISTICS 12 WRITE CYCLE LIMITS 13 PACKAGE OUTLINES 14 SOLDERING
14.1 Introduction
14.2 DIP
14.2.1 Soldering by dipping or by wave
14.2.2 Repairing soldered joints
14.3 SO
14.3.1 Reflow soldering
14.3.2 Wave soldering
14.3.3 Repairing soldered joints 15 DEFINITIONS 16 LIFE SUPPORT APPLICATIONS 17 PURCHASE OF PHILIPS I2C COMPONENTS
Page 3
1997 Apr 02 3
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
1 FEA TURES
Low power CMOS: – maximum operating current 1.0 mA – maximum standby current 10 µA (at 5.5 V),
typical 4 µA
Non-volatile storage of 16 kbits organized as eight blocks of 256 × 8-bit each
Single supply with full operation down to 2.7 V
On-chip voltage multiplier
Serial input/output I2C-bus (100 kbits/s standard-mode
and 400 kbits/s fast-mode)
Write operations: multi byte write mode up to 32 bytes
Write-protection input
Read operations:
– sequential read – random read
Internal timer for writing (no external components)
Power-on-reset
High reliability by using redundant EEPROM cells
Endurance: 1000000 Erase/Write (E/W) cycles at
T
amb
=22°C
20 years non-volatile data retention time (minimum)
Pin and address compatible to the PCx85xxC-2 family
(see also Section 2.1)
2 kV ESD protection (Human Body model).
2 DESCRIPTION
The PCF85116-3 is an 16 kbits (2048 × 8-bit) floating gate Electrically Erasable Programmable Read Only Memory (EEPROM). By using redundant EEPROM cells it is fault tolerant to single bit errors. In most cases multi bit errors are also covered. This feature dramatically increases reliability compared to conventional EEPROM memories. Power consumption is low due to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier.
As data bytes are received and transmitted via the serial I2C-bus, a package using eight pins is sufficient. Only one PCF85116-3 device is required to support all eight blocks of 256 × 8-bit each.
Timing of the E/W cycle is carried out internally, thus no external components are required. A write-protection input at pin 7 (WP) allows disabling of write-commands from the master by a hardware signal. When pin 7 is HIGH the data bytes received will not be acknowledged by the PCF85116-3 and the EEPROM contents are not changed.
2.1 Remark
The PCF85116-3 is pin and address compatible to the PCx85xxC-2 family. The PCF85116-3 covers the whole address space of 16 kbits; address inputs are no longer needed. Therefore, pins 1 to 3 are not connected. The write-protection input is at pin 7.
3 QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DD
supply voltage 2.7 5.5 V
I
DDR
supply current read f
SCL
= 400 kHz; VDD= 5.5 V 1.0 mA
I
DDW
supply current E/W f
SCL
= 400 kHz; VDD= 5.5 V 1.0 mA
I
stb
standby supply current VDD= 2.7 V 6 µA
V
DD
= 5.5 V 10 µA
Page 4
1997 Apr 02 4
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
4 ORDERING INFORMATION
5 DEVICE SELECTION Table 1 Device selection code
Note
1. The Most Significant Bit (MSB) ‘b7’ is sent first.
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
PCF85116-3P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 PCF85116-3T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
SELECTION DEVICE CODE CHIP ENABLE R/
W
Bit b7
(1)
b6 b5 b4 b3 b2 b1 b0
Device 1 0 1 0 MEM SEL MEM SEL MEM SEL R/
W
Page 5
1997 Apr 02 5
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
6 BLOCK DIAGRAM
Fig.1 Block diagram.
MBH922
TEST MODE
REGISTER
INPUT
FILTER
ADDRESS
COMPARATOR
COLUMN DECODER
I
2
C-BUS CONTROL LOGIC
PAGE REGISTER
EEPROM ARRAY
(8 × 256 × 8)
SHIFT
REGISTER
ADDRESS
POINTER
HV
GENERATOR
ROW
DEC
SEQUENCER
DIVIDER
OSCILLATOR
5
6
n
V
DD
V
SS
4
7
WP
8
6
5
SDA
SCL
POWER-ON-RESET
PCF85116-3
Page 6
1997 Apr 02 6
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
7 PINNING
SYMBOL PIN DESCRIPTION
n.c. 1 not connected n.c. 2 not connected n.c. 3 not connected V
SS
4 negative supply voltage
SDA 5 serial data input/output (I
2
C-bus)
SCL 6 serial clock input (I
2
C-bus) WP 7 write-protection input V
DD
8 positive supply voltage
Fig.2 Pin configuration.
handbook, halfpage
MBH923
PCF85116-3
1 2 3 4
8 7 6 5
n.c. n.c. n.c.
V
SS
SDA
WP SCL
V
DD
8I2C-BUS PROTOCOL
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The serial bus consists of two bidirectional lines: one for data signals (SDA), and one for clock signals (SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals.
8.1 Bus conditions
The following bus conditions have been defined:
Bus not busy: both data and clock lines remain HIGH.
Start data transfer: a change in the state of the data line,
from HIGH-to-LOW, while the clock is HIGH, defines the START condition
Stop data transfer: a change in the state of the data line, from LOW-to-HIGH, while the clock is HIGH, defines the STOP condition
Data valid: the state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.
8.2 Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP condition; the number of the data bytes, transferred between the START and STOP conditions is limited to 32 bytes in the E/W mode.
Data transfer is unlimited in the read mode. The information is transmitted in bytes and each receiver acknowledges with a ninth bit.
Within the I
2
C-bus specifications a low-speed mode (2 kHz clock rate), a high speed mode (100 kHz clock rate) and a fast speed mode (400 kHz clock rate) are defined. The PCF85116-3 operates in all three modes.
By definition a device that sends a signal is called a ‘transmitter’, and the device which receives the signal is called a ‘receiver’. The device which controls the signal is called the ‘master’. The devices that are controlled by the master are called ‘slaves’.
Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level, put on the bus by the transmitter. The master generates an extra acknowledge related clock pulse. The slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte.
The master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master generation of the STOP condition.
Page 7
1997 Apr 02 7
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
8.3 Device addressing
Following a START condition the bus master must output the address of the slave it is accessing. The 4 MSBs of the slave address are the device type identifier (see Fig.3). For the PCF85116-3 this is fixed to ‘1010’.
The next three significant bits of the slave address field are the block selection bits. It is used by the host to select one out of eight blocks (1 block = 256 bytes of memory). These are, in effect, the three most significant bits of the word address.
The last bit of the slave address defines the operation to be performed. When R/
W is set to logic 1 a read operation
is selected.
8.4 Write operations
8.4.1 B
YTE/WORD WRITE
For a write operation the PCF85116-3 requires a second address field. This address field is a word address providing access to any one of the eight blocks of memory. Upon receipt of the word address the PCF85116-3 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. Word address is automatically incremented. The master terminates the transfer by generating a STOP condition.
After this stop condition the E/W cycle starts and the bus is free for another transmission. Its duration is maximum 10 ms.
During the E/W cycle the slave receiver does not send an acknowledge bit if addressed via the I2C-bus.
Fig.3 Slave address.
handbook, halfpage
MBH924
1010BBBR/W
8.4.2 PAGE WRITE
The PCF85116-3 is capable of an 32-byte page write operation. It is initiated in the same manner as the byte write operation. The master can transmit up to 32 data bytes within one transmission. After receipt of each byte the PCF85116-3 will respond with an acknowledge. The master terminates the transfer by generating a STOP condition. The maximum total E/W time in this mode is 10 ms.
After the receipt of each data byte the six high order bits of the memory address providing access to one of the 64 pages of the memory remain unchanged. The five low order bits of the memory address will be incremented only (see Fig.3). By these five bits a single byte within the page in access is selected. By an increment the memory address may change from 31 to 0, from 63 to 32, etc. If the master transmits more than 32 bytes prior to generating the STOP condition, data within the addressed page may be overwritten and unpredictable results may occur. As in the byte write operation, all inputs are disabled until completion of the internal write cycles.
8.4.3 R
EMARK
Write accesses to the EEPROM are enabled if the pin WP is LOW. When WP is HIGH the EEPROM is write-protected and no acknowledge will be given by the PCF85116-3 when data is sent. However, an acknowledge will be given after the slave address and the word address.
Fig.4 Auto increment of memory address.
handbook, halfpage
MBH925
B B B WORD ADDRESS
read: auto increment
write: unchanged write: auto increment
Page 8
1997 Apr 02 8
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
Fig.5 Auto increment memory address; two byte write.
handbook, full pagewidth
S
0A
SLAVE ADDRESS
WORD ADDRESS
AADATA P
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
ADATA
R/W
auto increment
word address
auto increment
word address
MBH926
BBB
Fig.6 Page write operation; 32 bytes.
handbook, full pagewidth
S 0 A WORD ADDRESS A A
DATA N
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
auto increment
word address
acknowledge
from slave
A
DATA N + 1
auto increment
word address
MBH927
P
acknowledge
from slave
ADATA N + 31
auto increment
word address
last byte
BBB
SLAVE ADDRESS
R/W
Page 9
1997 Apr 02 9
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
8.5 Read operations
Read operations are initiated in the same manner as write operations with the exception that the LSB of the slave address (R/W) is set to logic 1. There are three basic read operations; current address read, random read and sequential read.
8.5.1 REMARK During read operations all bits of the memory address are
incremented after each transmission of a data byte. Contrary to write operations an overflow of the memory address occurs from 2047 to 0 (see Fig.3).
Fig.7 Master reads PCx85116-3 slave after setting word address (write word address; read data).
handbook, full pagewidth
S 0 A WORD ADDRESS A A
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from master
A
DATA
auto increment
word address
MBH928
P
no acknowledge
from master
1DATA
auto increment
word address
last byte
R/W
S1
n bytes
at this moment master transmitter becomes master receiver and EEPROM slave receiver becomes slave transmitter
B BBB BB
SLAVE ADDRESS
R/W
SLAVE ADDRESS
Fig.8 Master reads PCx85116-3 immediately after first byte (read mode).
handbook, full pagewidth
S
1A
DATA
A1DATA
acknowledge
from slave
acknowledge
from master
no acknowledge
from master
auto increment
word address
MBH929
auto increment
word address
n bytes last bytes
PBBB
SLAVE ADDRESS
R/W
Page 10
1997 Apr 02 10
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. ESD Human Body model Q22 at T
amb
=22°C; discharge procedure according to MIL-STD-883C Method 3015.
10 CHARACTERISTICS
V
DD
= 2.7 to 5.5 V; VSS=0V; T
amb
= 40 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DD
supply voltage 0.3 +6.5 V
V
I
input voltage on any pin Zi > 500 Ω VSS− 0.8 +6.5 V
I
I
input current on any pin 1mA
I
O
output current 10 mA
T
stg
storage temperature 65 +150 °C
T
amb
operating ambient temperature 40 +85 °C
V
esd
electrostatic discharge voltage note 1 2 kV
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Supplies
V
DD
supply voltage 2.7 5.5 V
I
DDR
supply current read f
SCL
= 400 kHz;
VDD= 5.5 V
1.0 mA
I
DDW
supply current E/W f
SCL
= 400 kHz;
VDD= 5.5 V
1.0 mA
I
DD(stb)
standby supply current VDD= 2.7 V 6 µA
V
DD
= 5.5 V 10 µA
SDA input/output (pin 5)
V
IL
LOW level input voltage 0.8 +0.3V
DD
V
V
IH
HIGH level input voltage 0.7V
DD
6.5 V
V
OL1
LOW level output voltage IOL= 3 mA; V
DD(min)
0.4 V
V
OL2
IOL= 6 mA; V
DD(min)
0.6 V
I
LO
output leakage current VOH=V
DD
1 µA
t
o(f)
output fall time from V
IHmin
to V
ILmax
note 1
with up to 3 mA sink current at V
OL1
20 + 0.1Cb250 ns
with up to 6 mA sink current at V
OL2
20 + 0.1Cb250 ns
t
SP
pulse width of spikes suppressed by filter 0 100 ns
C
I
input capacitance VI=V
SS
10 pF
Page 11
1997 Apr 02 11
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
Note
1. The bus capacitance ranges from 10 to 400 pF (Cb= total capacitance of one bus line in pF).
11 I
2
C-BUS CHARACTERISTICS
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing from VSSto VDD.
Notes
1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by a transmitter.
2. Cb= total capacitance of one bus line in pF.
SCL input (pin 6)
V
IL
LOW level input voltage 0.8 +0.3V
DD
V
V
IH
HIGH level input voltage 0.7V
DD
6.5 V
I
LI
input leakage current VI=VDDor V
SS
−±1µA
f
SCL
clock input frequency 0 400 kHz
t
SP
pulse width of spikes suppressed by filter 0 100 ns
C
I
input capacitance VI=V
SS
7pF
WP input (pin 7)
V
IL
LOW level input voltage 0.8 +0.1V
DD
V
V
IH
HIGH level input voltage 0.9V
DD
VDD+ 0.8 V
Data retention time
t
S
data retention time T
amb
=55°C20years
SYMBOL PARAMETER CONDITIONS
STANDARD MODE FAST MODE
UNIT
MIN. MAX. MIN. MAX.
f
SCL
clock frequency 0 100 0 400 kHz
t
BUF
time the bus must be free before new transmission can start
4.7 1.3 −µs
t
HD;STA
START condition hold time after which first clock pulse is generated
4.0 0.6 −µs
t
LOW
LOW level clock period 4.7 1.3 −µs
t
HIGH
HIGH level clock period 4.0 0.6 −µs
t
SU; STA
set-up time for START condition repeated start 4.7 0.6 −µs
t
HD; DAT
data hold time
for CBUS compatible masters 5 −− −µs for I2C-bus devices note 1 0 0 ns
t
SU; DAT
data set-up time 250 100 ns
t
r
SDA and SCL rise time 1000 20 + 0.1C
b
(2)
300 ns
t
f
SDA and SCL fall time 300 20 + 0.1C
b
(2)
300 ns
t
SU; STO
set-up time for STOP condition 4.0 0.6 −µs
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Page 12
1997 Apr 02 12
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
handbook, full pagewidth
MBA705
t
BUF
HD;STA
t
SCL
SDA
P S
t
LOW
t
r
HD;DAT
t
SU;DAT
t
t
f
t
HIGH
S
HD;STA
t
SU;STA
t
SU;STO
t
P
Fig.9 Timing requirements for the I
2
C-bus.
P = STOP condition; S = START condition.
Page 13
1997 Apr 02 13
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
12 WRITE CYCLE LIMITS
The Power-on-reset circuit resets the I
2
C-bus logic with a set-up time of 10 µs.Enabling the chip is achieved by
connecting the WP input to V
SS
.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
E/W cycle timing
t
E/W
E/W cycle time −−10 ms
Endurance
N
E/W
E/W cycle per byte T
amb
= 40 to +85 °C 100000 −−cycles
T
amb
=22°C 1000000 −−cycles
Page 14
1997 Apr 02 14
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
13 PACKAGE OUTLINES
UNIT
A
max.
A1A2A3b
p
cD
(1)E(2)
(1)
eHELLpQZywv θ
REFERENCES
OUTLINE VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
0.7
0.6
0.7
0.3
8 0
o o
0.25 0.10.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.4
SOT96-1
92-11-17 95-02-04
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
4
5
pin 1 index
1
8
y
076E03S MS-012AA
0.069
0.0098
0.0039
0.057
0.049
0.01
0.019
0.014
0.0098
0.0075
0.20
0.19
0.16
0.15
0.050
0.24
0.23
0.028
0.024
0.028
0.012
0.010.010.041 0.004
0.039
0.016
0 2.5 5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
Page 15
1997 Apr 02 15
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
REFERENCES
OUTLINE VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
SOT97-1
92-11-17 95-02-04
UNIT
A
max.
12
b
1
(1) (1)
(1)
b
2
cD E e M
Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min.
A
max.
b
max.
w
M
E
e
1
1.73
1.14
0.53
0.38
0.36
0.23
9.8
9.2
6.48
6.20
3.60
3.05
0.2542.54 7.62
8.25
7.80
10.0
8.3
1.154.2 0.51 3.2
inches
0.068
0.045
0.021
0.015
0.014
0.009
1.07
0.89
0.042
0.035
0.39
0.36
0.26
0.24
0.14
0.12
0.010.10 0.30
0.32
0.31
0.39
0.33
0.0450.17 0.020 0.13
b
2
050G01 MO-001AN
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w M
b
1
e
D
A
2
Z
8
1
5
4
b
E
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
pin 1 index
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
Page 16
1997 Apr 02 16
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
14 SOLDERING
14.1 Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“IC Package Databook”
(order code 9398 652 90011).
14.2 DIP
14.2.1 S
OLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T
stg max
). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
14.2.2 R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
14.3 SO
14.3.1 REFLOW SOLDERING Reflow soldering techniques are suitable for all SO
packages. Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
14.3.2 W
AVE SOLDERING
Wave soldering techniques can be used for all SO packages if the following conditions are observed:
A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
The longitudinal axis of the package footprint must be parallel to the solder flow.
The package footprint must incorporate solder thieves at the downstream end.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
14.3.3 R
EPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
Page 17
1997 Apr 02 17
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
15 DEFINITIONS
16 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
17 PURCHASE OF PHILIPS I
2
C COMPONENTS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Purchase of Philips I
2
C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
Page 18
1997 Apr 02 18
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
NOTES
Page 19
1997 Apr 02 19
Philips Semiconductors Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus interface
PCF851 16-3
NOTES
Page 20
Internet: http://www.semiconductors.philips.com
Philips Semiconductors – a worldwide company
© Philips Electronics N.V. 1997 SCA53 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
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Printed in The Netherlands 417067/1200/02/pp20 Date of release: 1997 Apr 02 Document order number: 9397 750 01994
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