Datasheet PCF85102C-2P-03, PCF85102C-2T-03, PCF85103C-2P-00, PCF85103C-2T-00 Datasheet (Philips)

DATA SH EET

Product specification
File under Integrated Circuits, IC12

2000 Feb 15

INTEGRATED CIRCUITS

PCF85102C-2; PCF85103C-2

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

2000 Feb 15 2

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 DEVICE SELECTION
6 BLOCK DIAGRAM
7 PINNING

7.1 Pin description PCF85102C-2

7.2 Pin description PCF85103C-2
8I

2

C-BUS PROTOCOL

8.1 Bus conditions

8.2 Data transfer

8.3 Device addressing

8.3.1 Remark

8.4 Write operations

8.4.1 Byte/word write

8.4.2 Page write

8.5 Read operations

8.5.1 Remark

9 LIMITING VALUES
10 CHARACTERISTICS
11 I2C-BUS CHARACTERISTICS
12 WRITE CYCLE LIMITS
13 PACKAGE OUTLINES
14 SOLDERING

14.1 Introduction

14.2 Through-hole mount packages

14.2.1 Soldering by dipping or by solder wave

14.2.2 Manual soldering

14.3 Surface mount packages

14.3.1 Reflow soldering

14.3.2 Wave soldering

14.3.3 Manual soldering
15 DEFINITIONS
16 LIFE SUPPORT APPLICATIONS
17 PURCHASE OF PHILIPS I2C COMPONENTS

2000 Feb 15 3

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

1 FEATURES

• Low power CMOS:
– maximum operating current: 2.0 mA
– maximum standby current 10 µA (at 6.0 V),

typical 4 µA.

• Non-volatile storage of:
– 2 kbits organized as 256 × 8-bit.

• Single supply with full operation down to 2.5 V

• On-chip voltage multiplier

• Serial input/output I2C-bus

• Write operations:

– byte write mode
– 8-byte page write mode

(minimizes total write time per byte).

• Read operations:
– sequential read
– random read.

• Internal timer for writing (no external components)

• Power-on reset

• High reliability by using a redundant storage code

• Endurance: 1000000 Erase/Write (E/W) cycles at

T

amb

=22°C

• 10 years non-volatile data retention time

• Standard industrial pinning (pin 7 not connected)

• Up to sixteen EEPROMs addressable in one I2C-bus

using both PCF85102 and PCF85103 in combination.

2 GENERAL DESCRIPTION

The PCF85102C-2 andPCF85103C-2 (further referred to
as PCF8510xC-2) are 2 kbits (256 × 8-bit) floating gate
Electrically Erasable Programmable Read Only Memories
(EEPROMs). Power consumption is low due to the full
CMOS technology used. The programming voltage is
generated on-chip, using a voltage multiplier.
The PCF8510x-2 is pin compatible to widely used
industrial pinning (pin 7 not connected).

As data bytes are received and transmitted via the serial
I2C-bus, a package using eight pins is sufficient. Up to
sixteen PCF8510xC-2 devices may be connected to the
I2C-bus. This is possible with the introduction of a second
device selection code. Chip select is accomplished by
three address inputs (A0, A1 and A2) for each
PCF8510xC-2 type.

3 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

supply voltage 2.5 6.0 V

I

DDR

supply current read f

SCL

= 100 kHz

V

DD

= 2.5 V − 60 µA

V

DD

= 6.0 V − 200 µA

I

DDW

supply current E/W f

SCL

= 100 kHz

V

DD

= 2.5 V − 0.6 mA

V

DD

= 6.0 V − 2.0 mA

I

DDstb

standby supply current VDD= 2.5 V − 3.5 µA

V

DD

= 6.0 V − 10 µA

2000 Feb 15 4

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

4 ORDERING INFORMATION

5 DEVICE SELECTION
Table 1 Device selection code

Note

1. The Most Significant Bit (MSB) ‘b7’ is sent first.

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

PCF85102C-2P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
PCF85103C-2P
PCF85102C-2T SO8 plastic small outline package; 8 leads;

body width 3.9 mm

SOT96-1

PCF85103C-2T

SELECTION DEVICE CODE CHIP ENABLE R/W

Bit b7

(1)

b6 b5 b4 b3 b2 b1 b0

PCF85102-C 1 0 1 0 A2 A1 A0 R/

W

PCF85103-C 0 0 1 0 A2 A1 A0 R/

W

2000 Feb 15 5

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with

I

2

C-bus interface

PCF85102C-2; PCF85103C-2

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6 BLOCK DIAGRAM

handbook, full pagewidth

MGL967

TEST MODE DECODER

POWER-ON-RESET

I

2

C-BUS CONTROL LOGIC

SEQUENCER

ADDRESS

HIGH

REGISTER

BYTE

COUNTER

DIVIDER

( 128)

EE

CONTROL

TIMER
( 16)

EEPROM

ADDRESS

POINTER

BYTE

LATCH

(8 bytes)

SHIFT

REGISTER

ADDRESS

SWITCH

INPUT

FILTER

OSCILLATOR

8

4

3

n

PCF85102C-2;

PCF85103C-2

4

V

SS

7

n.c.

A1

A2

A0

3
2
1

8

V

DD

6
5

SCL
SDA

Fig.1 Block diagram.

The pin numbers in this block diagram refer to the PCF85102C-2.
For PCF85103C-2, please see Chapter 7.

2000 Feb 15 6

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

7 PINNING

PCF8510xC-2 has standard industrial pinning which will be compatible for most applications.

7.1 Pin description PCF85102C-2

SYMBOL PIN DESCRIPTION

A0 1 address input 0
A1 2 address input 1
A2 3 address input 2
V

SS

4 negative supply voltage

SDA 5 serial data input/output (I

2

C-bus)

SCL 6 serial clock input (I

2

C-bus)
n.c. 7 not connected
V

DD

8 positive supply voltage

handbook, halfpage

1
2
3
4

8
7
6
5

A0
A1
A2

V

SS

SDA

SCL

n.c.

V

DD

PCF85102C-2

MGL968

Fig.2 Pin configuration PCF85102C-2.

7.2 Pin description PCF85103C-2
SYMBOL PIN DESCRIPTION

WP 1 address input 0
A1 2 address input 1
A2 3 address input 2
V

SS

4 negative supply voltage

SDA 5 serial data input/output (I

2

C-bus)

SCL 6 serial clock input (I

2

C-bus)
n.c. 7 not connected
V

DD

8 positive supply voltage

handbook, halfpage

1
2
3
4

8
7
6
5

WP

A1
A2

V

SS

SDA

SCL

n.c.

V

DD

PCF85103C-2

MGL969

Fig.3 Pin configuration PCF85103C-2.

2000 Feb 15 7

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

8I2C-BUS PROTOCOL

The I2C-bus is designed for 2-way, 2-line communication
between different ICs or modules. The serial bus consists
of two bidirectional lines: one for data signals (SDA), and
one for clock signals (SCL).

Both the SDA and SCL lines must be connected to a
positive supply voltage via a pull-up resistor.

The following protocol has been defined:

• Data transfer may be initiated only when the bus is not
busy

• During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
control signals.

8.1 Bus conditions

The following bus conditions have been defined:

• Bus not busy: both data and clock lines remain HIGH.

• Start data transfer: a change in the state of the data

line, from HIGH-to-LOW, while the clock is HIGH,
defines the START condition.

• Stop data transfer: a change in the state of the data
line, from LOW-to-HIGH, while the clock is HIGH,
defines the STOP condition.

• Data valid: the state of the data line represents valid
data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per bit of data.

8.2 Data transfer

Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of the data
bytes, transferred between the START and STOP
conditions is limited to seven bytes in the E/W mode and
eight bytes in the page E/W mode.

Data transfer is unlimited in the read mode.
The information is transmitted in bytes and each receiver
acknowledges with a ninth bit.

Within the I

2

C-bus specifications, a low-speed mode
(2 kHz clock rate) and a high speed mode (100 kHz clock
rate) are defined. The PCF8510xC-2 operates in both
modes.

By definition, a device that sends a signal is called a
‘transmitter’, and the device that receives the signal is
called a ‘receiver’. The device that controls the signal is
called the ‘master’. The devices that are controlled by the
master are called ‘slaves’.

Each byte is followed by one acknowledge bit, which is
placed on the bus at a HIGH level by the transmitter.
The mastergeneratesanextraacknowledge-relatedclock
pulse. The slave receiver that is addressed is obliged to
generate an acknowledge after the reception of each byte.

The master receiver must generate an acknowledge after
the reception of each byte that has been clocked out of the
slave transmitter.

The device that acknowledges has to pull the SDA line
down during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period of
the acknowledge-related clock pulse.

Set-up and hold times must be taken into account. A
master receiver must signal an end of data to the slave
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event,
thetransmittermustleavethedatalineHIGHtoenablethe
master generation of the STOP condition.

2000 Feb 15 8

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

8.3 Device addressing

Following a START condition, the bus master must output
the address of the slave it is accessing. The four MSBs of
the slave address are the device type identifier (see Fig.4
and Fig.5). For the PCF85102C-2, this is fixed to ‘1010’,
for the PCF85103C-2 to ‘0010’.

The next three significant bits address a particular device
or memory page (page = 256 bytes of memory). A system
could have up to sixteen PCF8510xC-2 devices on the
bus. This can be achieved with eight PCF85102C devices
and eight PCF85103C devices, combined on one I2C-bus.
The eight addresses are defined by the state of the A0, A1
and A2 inputs per type.

The last bit of the slave address defines the operation to
be performed. When set to logic 1, a read operation is
selected.

Address bits must be connected to either VDD or VSS.

8.3.1 R

EMARK

TheI2C-busdeviceselectaddress‘0010’is not exclusively
reserved for device PCF85103C-2. Therefore, multiple
use has to be checked in advance.

8.4 Write operations

8.4.1 B

YTE/WORD WRITE

Forawriteoperation,thePCF8510xC-2requiresa second
address field. This address field is a word address
providing access to the 256 words of memory. On receipt
of the word address, the PCF8510xC-2 responds with an
acknowledge and awaits the next eight bits of data, again
responding with an acknowledge. The word address is
automatically incremented. The master can now terminate
the transfer by generating a STOP condition or
transmitting up to six more bytes of data and then
terminating by generating a STOP condition.

AfterthisSTOPcondition,the E/W cycle starts andthebus
is free for another transmission. The duration of the
E/W cycle is 10 ms per byte.

During the E/W cycle, the slave receiver does not send an
acknowledge bit if addressed via the I2C-bus.

8.4.2 PAGE WRITE
The PCF8510xC-2 is capable of an 8-byte page write

operation. It is initiated in the same manner as the byte
write operation. The master can transmit eight data bytes
within one transmission. After receipt of each byte, the
PCF8510xC-2 will respond with an acknowledge.
The typicalE/W timeinthismodeis9 × 3.5 ms = 31.5 ms.
Erasing a block of eight bytes in page mode takesa typical

3.5 ms and sequential writing of these eight bytes another
typical 28 ms.

After the receipt of each data byte, the three low order bits
of the word address are internally incremented. The five
high order bits of the address remain unchanged.
The slave acknowledges the reception of each data byte
with an ACK. The I2C-bus data transfer is terminated by
the master after the eighth byte with a STOP condition.
If the master transmits more than eight bytes prior to
generating the STOP condition, no acknowledge will be
given on the ninth (and following) data bytes. Also, the
whole transmission will be ignored and no programming
will be done. As in the byte write operation, all inputs are
disabled until completion of the internal write cycles.

handbook, halfpage

MBC793

1010A2A1A0R/W

Fig.4 Slave address for PCF85102C-2.

handbook, halfpage

MGL970

0010A2A1A0R/W

Fig.5 Slave address for PCF85103C-2.

2000 Feb 15 9

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

handbook, full pagewidth

S0ASLAVE ADDRESS WORD ADDRESS

AADATA P

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

ADATA

R/W

auto increment

word address

auto increment

word address

MBA701

Fig.6 Auto increment memory word address; two byte write.

handbook, full pagewidth

S0ASLAVE ADDRESS WORD ADDRESS A A

DATA N

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

R/W

auto increment

word address

acknowledge

from slave

A

DATA N + 1

auto increment

word address

MBA702

A

acknowledge

from slave

1DATA N + 7

auto increment

word address

last byte

Fig.7 Page write operation; eight bytes.

2000 Feb 15 10

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

8.5 Read operations

The read operations are initiated in the same way as write
operations, with the exception that the LSB of the slave
address is set to logic 1.

There are three basic read operations; current address
read, random read and sequential read sequential read.

8.5.1 REMARK
The lower eight bits of the word address are incremented

after each transmission of a data byte (read or write).
The MSB of the word address, which is defined in the
slave address, is not changed when the word address
count overflows. Thus, the word address overflows from
255 to 0.

handbook, full pagewidth

S0ASLAVE ADDRESS WORD ADDRESS A A

SLAVE ADDRESS

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

R/W

acknowledge

from master

A

DATA

auto increment

word address

MBA703 - 1

P

no acknowledge

from master

1DATA

auto increment

word address

last byte

R/W

S1

n bytes

at this moment master
transmitter becomes
master receiver and
EEPROM slave receiver
becomes slave transmitter

Fig.8 Master reads PCF8510xC-2 slave after setting word address (write word address; read data).

handbook, full pagewidth

S

1A

SLAVE ADDRESS DATA

A1DATA

acknowledge

from slave

acknowledge

from master

no acknowledge

from master

R/W

auto increment

word address

MBA704 - 1

auto increment

word address

n bytes last bytes

P

Fig.9 Master reads PCF8510xC-2 immediately after first byte (read mode).

2000 Feb 15 11

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

10 CHARACTERISTICS

V

DD

= 2.5 to 6.0 V; VSS=0V; T

amb

= −40 to +85 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

supply voltage −0.3 +6.5 V

V

I

input voltage on input pins Zi > 500 Ω VSS− 0.8 +6.5 V

I

I

input current on input pins − 1mA

I

O

output current − 10 mA

T

stg

storage temperature −65 +150 °C

T

amb

ambient temperature −40 +85 °C

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Supplies

V

DD

supply voltage 2.5 6.0 V

I

DDR

supply current read f

SCL

= 100 kHz

V

DD

= 2.5 V − 60 µA

V

DD

= 6.0 V − 200 µA

I

DDW

supply current E/W f

SCL

= 100 kHz

V

DD

= 2.5 V − 0.6 mA

V

DD

= 6.0 V − 2.0 mA

I

DDstb

standby supply current VDD= 2.5 V − 3.5 µA

V

DD

= 6.0 V − 10 µA

SCL input (pin 6)

V

IL

LOW-level input voltage −0.8 +0.3V

DD

V

V

IH

HIGH-level input voltage 0.7V

DD

6.5 V

I

LI

 input leakage current VI=VDDor V

SS

−±1µA

f

SCL

clock frequency 0 100 kHz

C

i

input capacitance VI=V

SS

− 7pF

SDA input/output (pin 5)

V

IL

LOW-level input voltage −0.8 +0.3V

DD

V

V

IH

HIGH-level input voltage 0.7V

DD

6.5 V

V

OL

LOW-level output voltage IOL= 3 mA; V

DD(min)

− 0.4 V

I

LO

output leakage current VOH=V

DD

− 1 µA

C

i

input capacitance VI=V

SS

− 7pF

Data retention time

t

D(ret)

data retention time T

amb

=55°C10 − years

2000 Feb 15 12

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

11 I2C-BUS CHARACTERISTICS

All timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and V

IH

with an input voltage swing from VSSto VDD; see Fig.10; unless otherwise specified.

Note

1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be
internally provided by a transmitter.

12 WRITE CYCLE LIMITS

Selection of the chip address is achieved by connecting the A0, A1 and A2 inputs to either V

SS

or VDD.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

f

SCL

clock frequency 0 100 kHz

t

BUF

bus free time between a STOP and START
condition

4.7 −µs

t

HD;STA

START condition hold time after which first clock
pulse is generated

4.0 −µs

t

LOW

LOW-level clock period 4.7 −µs

t

HIGH

HIGH-level clock period 4.0 −µs

t

SU;STA

set-up time for START condition repeated start 4.7 −µs

t

HD;DAT

data hold time

for bus compatible masters 5 −µs
for bus devices note 1 0 − ns

t

SU;DAT

data set-up time 250 − ns

t

r

SDA and SCL rise time − 1 µs

t

f

SDA and SCL fall time − 300 ns

t

SU;STO

set-up time for STOP condition 4.0 −µs

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

E/W cycle timing

t

E/W

E/W cycle time internal oscillator − 7 − ms

Endurance

N

E/W

E/W cycle per byte T

amb

= −40 to +85 °C 100000 −−cycles

T

amb

=22°C − 1000000 − cycles

2000 Feb 15 13

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with

I

2

C-bus interface

PCF85102C-2; PCF85103C-2

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handbook, full pagewidth

MBA705

t

BUF

HD;STA

t

SCL

SDA

P S

t

LOW

t

r

HD;DAT

t

SU;DAT

t

t

f

t

HIGH

S

HD;STA

t

SU;STA

t

SU;STO

t

P

Fig.10 Timing requirements for the I2C-bus.

P = STOP condition; S =START condition.

2000 Feb 15 14

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

13 PACKAGE OUTLINES

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

SOT97-1

95-02-04
99-12-27

UNIT

A

max.

12

b

1

(1) (1)

(1)

b

2

cD E e M

Z

H

L

mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

min.

A

max.

b

max.

w

M

E

e

1

1.73

1.14

0.53

0.38

0.36

0.23

9.8

9.2

6.48

6.20

3.60

3.05

0.2542.54 7.62

8.25

7.80

10.0

8.3

1.154.2 0.51 3.2

inches

0.068

0.045

0.021

0.015

0.014

0.009

1.07

0.89

0.042

0.035

0.39

0.36

0.26

0.24

0.14

0.12

0.010.10 0.30

0.32

0.31

0.39

0.33

0.0450.17 0.020 0.13

b

2

050G01 MO-001 SC-504-8

M

H

c

(e )

1

M

E

A

L

seating plane

A

1

w M

b

1

e

D

A

2

Z

8

1

5

4

b

E

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

pin 1 index

DIP8: plastic dual in-line package; 8 leads (300 mil)

SOT97-1

2000 Feb 15 15

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

UNIT

A

max.

A

1

A

2

A3b

p

cD

(1)E(2)

(1)

eHELLpQZywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

1.27

6.2

5.8

1.05

0.7

0.6

0.7

0.3

8
0

o
o

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

1.0

0.4

SOT96-1

X

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

(A )

3

A

4

5

pin 1 index

1

8

y

076E03 MS-012

0.069

0.010

0.004

0.057

0.049

0.01

0.019

0.014

0.0100

0.0075

0.20

0.19

0.16

0.15

0.050

0.244

0.228

0.028

0.024

0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

97-05-22
99-12-27

2000 Feb 15 16

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

14 SOLDERING

14.1 Introduction

Thistextgivesaverybriefinsightto a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when
through-holeandsurfacemount components are mixedon
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.

14.2 Through-hole mount packages

14.2.1 SOLDERING BY DIPPING OR BY SOLDER WAVE

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg(max)

). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

14.2.2 MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the

package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.

14.3 Surface mount packages

14.3.1 REFLOW SOLDERING
Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied
totheprinted-circuitboardbyscreenprinting,stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

14.3.2 WAVE SOLDERING
Conventional single wave soldering is not recommended

forsurfacemountdevices(SMDs)or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfour sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

14.3.3 MANUAL SOLDERING

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2000 Feb 15 17

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

14.4 Suitability of IC packages for wave, reflow and dipping soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

MOUNTING PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

DIPPING

Through-hole mount DBS, DIP, HDIP, SDIP, SIL suitable

(2)

− suitable

Surface mount BGA, LFBGA, SQFP, TFBGA not suitable suitable −

HBCC, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, SMS

not suitable

(3)

suitable −

PLCC

(4)

, SO, SOJ suitable suitable −

LQFP, QFP, TQFP not recommended

(4)(5)

suitable −

SSOP, TSSOP, VSO not recommended

(6)

suitable −

2000 Feb 15 18

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

15 DEFINITIONS

16 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

17 PURCHASE OF PHILIPS I

2

C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2000 Feb 15 19

Philips Semiconductors Product specification

256 × 8-bit CMOS EEPROMs with
I

2

C-bus interface

PCF85102C-2; PCF85103C-2

NOTES

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract,isbelievedto be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000

69

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Printed in The Netherlands 465006/25/01/pp20 Date of release: 2000 Feb 15 Document order number: 9397750 06682