Datasheet PCF2113DU-10-F3, PCF2113DU-F2, PCF2113DU-F3, PCF2113EU-10-F2, PCF2113EU-10-F3 Datasheet (Philips)

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Page 1

DATA SH EET

Product speciﬁcation Supersedes data of 1996 Oct 21 File under Integrated Circuits, IC12

1997 Apr 04

INTEGRATED CIRCUITS

PCF2113x

LCD controller/driver

Page 2

1997 Apr 04 2

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

CONTENTS

1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 PIN FUNCTIONS 8 FUNCTIONAL DESCRIPTION

8.1 LCD supply voltage generator

8.2 Programming ranges

8.3 LCD bias voltage generator

8.4 Oscillator

8.5 External clock

8.6 Power-on reset

8.7 Power-down mode

8.8 Registers

8.9 Busy Flag

8.10 Address Counter (AC)

8.11 Display Data RAM (DDRAM)

8.12 Character Generator ROM (CGROM)

8.13 Character Generator RAM (CGRAM)

8.14 Cursor control circuit

8.15 Timing generator

8.16 LCD row and column drivers

8.17 Reset function 9 INSTRUCTIONS

9.1 Clear display

9.2 Return home

9.3 Entry mode set

9.3.1 I/D

9.3.2 S

9.4 Display control (and partial power-down mode)

9.4.1 D

9.4.2 C

9.4.3 B

9.5 Cursor/display shift

9.6 Function set

9.6.1 DL (parallel mode only)

9.6.2 M

9.6.3 H

9.7 Set CGRAM address

9.8 Set DDRAM address

9.9 Read busy flag and address

9.10 Write data to CGRAM or DDRAM

9.11 Read data from CGRAM or DDRAM 10 EXTENDED FUNCTION SET

INSTRUCTIONS AND FEATURES

10.1 New instructions

10.2 Icon control

10.3 IM

10.4 IB

10.5 Normal/Icon mode operation

10.6 Screen configuration

10.7 Display configuration

10.8 TC1, TC2

10.9 Set V

LCD

10.10 Reducing current consumption 11 INTERFACE TO MICROCONTROLLER

(PARALLEL INTERFACE)

12 INTERFACE TO MICROCONTROLLER

(I2C-BUS INTERFACE)

12.1 Characteristics of the I2C-bus

12.2 I2C-bus protocol

12.3 Definitions 13 LIMITING VALUES 14 HANDLING 15 DC CHARACTERISTICS 16 AC CHARACTERISTICS 17 TIMING CHARACTERISTICS 18 APPLICATION INFORMATION

18.1 8-bit operation, 1-line display using internal reset

18.2 4-bit operation, 1-line display using internal reset

18.3 8-bit operation, 2-line display

18.4 I2C operation, 1-line display

19 BONDING PAD LOCATIONS 20 PACKAGE OUTLINE 21 SOLDERING

21.1 Introduction

21.2 Reflow soldering

21.3 Wave soldering

21.4 Repairing soldered joints

22 DEFINITIONS 23 LIFE SUPPORT APPLICATIONS 24 PURCHASE OF PHILIPS I2C COMPONENTS

Page 3

1997 Apr 04 3

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

1 FEATURES

• Single-chip LCD controller/driver

• 2-line display of up to 12 characters + 120 icons,

or 1-line display of up to 24 characters + 120 icons

• 5 × 7 character format plus cursor; 5 × 8 for kana (Japanese syllabary) and user defined symbols

• Icon mode: reduced current consumption while displaying icons only

(1)

• Icon blink function

• On-chip:

– generation of LCD supply voltage, programmable by

instruction (external supply also possible)

– temperature compensation of on-chip generated

LCD

: −8to−12 mV/K at 5.0 V

(programmable by instruction) – generation of intermediate LCD bias voltages – oscillator requires no external components

(external clock also possible)

• Display data RAM: 80 characters

• Character generator ROM: 240, 5 × 8 characters

• Character generator RAM: 16, 5 × 8 characters;

3 characters used to drive 120 icons, 6 characters used if icon-blink feature is used in application

• 4 or 8-bit parallel bus and 2-wire I2C-bus interface

• CMOS compatible

• 18 row, 60 column outputs

(1) Icon mode is used to save current. When only icons

are displayed, a much lower operating voltage V

LCD

can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as V

LCD

. Never use the voltage generator

in icon mode.

• MUX rates 1 : 18 (for normal operation) and 1 : 2 (for icon-only mode)

• Uses common 11 code instruction set (extended)

• Logic supply voltage range, V

− VSS= 1.8 to 4.0 V

(up to 5.5 V if external V

LCD

is used); chip may be driven

with two battery cells

• Display supply voltage range, V

LCD

− VSS= 2.2 to 6.5 V

• Very low current consumption (20 to 200 µA):

– icon mode: <25 µA – power-down mode: <2.5 µA.

2 APPLICATIONS

• Telecom equipment

• Portable instruments

• Point-of-sale terminals.

3 GENERAL DESCRIPTION

The PCF2113x is a low power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2 line by 12 and 1 line by 24 characters with 5 × 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2113x interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I

C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. Three character sets (A, D and E) are currently available (see Figs 7, 8 and 9). Various other character sets can be manufactured on request.

4 ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

PCF2113AU/10/F2 − chip on ﬂexible ﬁlm carrier − PCF2113DU/10/F2 − chip on ﬂexible ﬁlm carrier − PCF2113DU/F2 − chip in tray − PCF2113DH/F2 LQFP100 plastic low proﬁle quad ﬂat package; 100 leads; body

14 × 14 × 1.4 mm

SOT407-1

PCF2113EU/2/F2 − chip with bumps in tray −

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1997 Apr 04 4

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

5 BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGE990

CURSOR AND DATA CONTROL

SHIFT REGISTER 5 × 12 BIT

DATA LATCHES

COLUMN DRIVERS

CHARACTER GENERATOR

RAM (128 × 5)

(CGRAM)

16 CHARACTERS

CHARACTER GENERATOR

ROM

(CGROM)

240 CHARACTERS

DISPLAY DATA RAM

(DDRAM)

80 CHARACTERS/BYTES

ADDRESS COUNTER

(AC)

INSTRUCTION

DECODER

INSTRUCTION

ROW DRIVERS

SHIFT REGISTER 18-BIT

BIAS

VOLTAGE

GENERATOR

LCD

GENERATOR

BUSY FLAG

DATA

(DR)

I/O BUFFER

OSCILLATOR

TIMING

GENERATOR

DISPLAY ADDRESS COUNTER

POWER-ON

RESET

DD1, 2

LCD2

SS1, 2

LCD1

5, 6

1, 100

C1 to C60 R1 to R18

OSC

PCF2113x

DB0 to DB3/SA0

DB4 to DB7

R/W

SCL

SDA

96 to 99

18 to 77 9 to 17

78 to 86

92 to 95 8887909189

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1997 Apr 04 5

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

6 PINNING

Notes

1. This is the V

LCD

output pin, if V

LCD

is generated internally and has to be connected to V

LCD1

. If V

LCD1

is generated

externally, V

LCD2

has to be left open or connected to ground.

2. This is the voltage used for the generation of LCD bias levels.

3. This is the supply for the high voltage generator. If V

LCD

is generated externally, connect V

DD2

to VSS.

SYMBOL PIN TYPE DESCRIPTION

DD1

1 P supply voltage for all except high voltage generator OSC 2 I oscillator/external clock input PD 3 I power-down pad input T1 4 I test pad (connected to V

)

SS1

5 P ground for all except high voltage generator V

SS2

6 P ground for high voltage generator V

LCD2

7OV

LCD

output; note 1

LCD1

8IV

LCD

input; note 2 R9 to R16 9 to 16 O LCD row driver outputs 9 to 16 R18 17 O LCD row driver output 18 C60 to C1 18 to 77 O LCD column driver outputs 60 to 1 R8 to R1 78 to 85 O LCD row driver outputs 8 to 1 R17 86 O LCD row driver output 17 SCL 87 I I

C serial clock input

SDA 88 I/O I

C serial data input/output E 89 I data bus clock input RS 90 I register select input R/

W 91 I read/write input DB7 92 I/O 1 bit of 8-bit bidirectional data bus DB6 93 I/O 1 bit of 8-bit bidirectional data bus DB5 94 I/O 1 bit of 8-bit bidirectional data bus DB4 95 I/O 1 bit of 8-bit bidirectional data bus DB3/SA0 96 I/O 1 bit of 8-bit bi-directional data bus/I

C address pin DB2 97 I/O 1 bit of 8-bit bidirectional data bus DB1 98 I/O 1 bit of 8-bit bidirectional data bus DB0 99 I/O 1 bit of 8-bit bidirectional data bus V

DD2

100 P supply voltage for high voltage generator; note 3

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1997 Apr 04 6

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.2 Pin configuration (LQFP100).

handbook, full pagewidth

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

8079787776

R6R7R8C1C2

C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27

DD1

OSC

SS1

SS2

LCD2

LCD1

R9 R10 R11 R12 R13 R14 R15 R16 R18 C60 C59 C58 C57 C56 C55 C54 C53

C47

C46

C45

C44

C43

C42

C41

C40

C39

C38

C37

C36

C35

C34

C33

C32

C31

C30

C29

C28

DD2

DB0

DB1

DB2

DB3/SA0

DB4

DB5

DB6

DB7

R/WRSE

SDA

SCL

R17R1R2R3R4

C52

C51

C50

C49

C48

100

99989796959493929190898887868584838281

31323334353637383940414243444546474849

PCF2113x

MGE989

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1997 Apr 04 7

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

7 PIN FUNCTIONS

Note

1. If the 4-bit interface is used without reading out from the PCF2113x (i.e. R/

W is set permanently to logic 0), the

unused ports DB0 to DB3 can either be set to VSS or VDD instead of leaving them open.

NAME FUNCTION DESCRIPTION

RS register select RS selects the register to be accessed for read and write when the device is

controlled by the parallel interface. There is an internal pull-up on this pin.

RS = logic 0 selects the instruction register for write and the Busy Flag and Address Counter for read.

RS = logic 1 selects the data register for both read and write.

W read/write R/W selects either the read (R/W = logic 1) or write (R/W = logic 0) operation when

the device is controlled by the parallel interface. There is an internal pull-up on this pin.

E data bus clock The E pin is set HIGH to signal the start of a read or write operation when the device

is controlled by the parallel interface. Data is clocked in or out of the chip on the negative edge of the clock. Note that this pin must be tied to logic 0 (V

) when

I2C-bus control is used.

DB7 to DB0 data bus The parallel interface of the device. This bi-directional, 3-state data bus transfers

data between the system controller and the PCF2113x. There is an internal pull-up on each of the data lines.

DB7 to DB0 must be connected to V

or left open circuit when I2C-bus control is

used. Note that DB3 shares the same pin as SA0. In 4-bit operations only DB7 to DB4 are used, and DB3 to DB0 must be left open

circuit. See note 1. DB7 may be used as the Busy Flag, signalling that internal operations are not yet

completed.

C1 to C60 column driver

outputs

These pins output the data for columns.

R1 to R18 row driver

outputs

These pins output the row select waveforms to the display. R17 and R18 drive the icons.

LCD

LCD power supply

Positive power supply for the liquid crystal display. This may be generated on-chip or supplied externally.

OSC oscillator When the on-chip oscillator is used this pin must be connected to V

An external clock signal, if used, is input at this pin.

SCL serial clock line Input for the I

C-bus clock signal.

SCL must be connected to V

or VDD when the parallel interface is used.

SDA serial data line I/O for the I

C-bus data line.

SDA must be connected to V

or VDD when the parallel interface is used.

SA0 address pin The hardware sub-address line is used to program the device sub-address for two

different PCF2113xs on the same I

C bus. Note that SA0 shares the same pin as

DB3.

T1 test pad T1 must be connected to V

and is not user accessible.

PD power-down pad PD selects chip power-down mode. For normal operation PD = logic 0.

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1997 Apr 04 8

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

8 FUNCTIONAL DESCRIPTION (see Fig.1)

8.1 LCD supply voltage generator

The LCD supply voltage may be generated on-chip. The voltage generator is controlled by two internal 6-bit registers, V

and VB. The nominal LCD operating voltage

at room temperature is given by the relationships:

OP(nom)

= [(integer value of register) × 0.08 + 1.9] V

8.2 Programming ranges (T

ref

=27°C)

Programmed value range: 1 to 63. Voltage range: 1.90 to 6.84 V.

Values producing more than 6.5 V at operating temperature are not allowed. Operation above this

voltage may damage the device. When programming the operating voltage the V

LCD

temperature coefficient must

be taken into account.

Values below 2.2 V are below the specified operating range of the chip and are therefore not allowed.

Value 0 for VA and VB switches the generator off.

Usually register V

is programmed with the voltage for character mode and register VB with the voltage for icon mode. VB must be programmed to FF in character mode and VA must be programmed to 00 in icon mode.

When V

LCD

is generated on-chip the V

LCD

pins should be decoupled to VSS with a suitable capacitor. The generated V

LCD

is independent of VDD and is temperature compensated. When the generator is switched off an external voltage may be supplied at connected pins V

LCD1,2

. V

LCD1,2

may be higher or lower than VDD if

external V

LCD

is used. If internally generated it must not

be lower than VDDand .

8.3 LCD bias voltage generator

The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of V

LCD

depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels and is given by the relationships given in Tables 1 and 2. Using a 5-level bias scheme for 1 : 18 maximum rate allows V

LCD

< 5 V for

most LCD liquids.

4V≤

Table 1 Optimum/maximum values for V

(off pixels start darkening; V

off=Vth

)

Table 2 Minimum values for V

(on pixels clearly visible; Von>Vth)

MUX RATE NUMBER OF LEVELS V

on/Vth

VOP/V

VOP(typical; for Vth= 1.4 V)

1 : 18 5 1.272 3.7 5.2 V 1 : 2 3 2.236 2.283 3.9 V

MUX RATE NUMBER OF LEVELS V

on/Vth

VOP/V

VOP(typical; for Vth= 1.4 V)

1 : 18 5 1.12 3.2 4.6 V 1 : 2 3 1.2 1.5 2.1 V

8.4 Oscillator

The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pin must be connected to VDD.

8.5 External clock

If an external clock is to be used this is input at the OSC pin. The resulting display frame frequency is given by

frame

OSC

3072

-------------

Only in the power-down state is the clock allowed to be stopped (OSC connected to V

), otherwise the LCD is

frozen in a DC state.

8.6 Power-on reset

The on-chip power-on reset block initializes the chip after power-on or power failure. This is a synchronous reset and requires 3 OSC cycles to be executed.

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1997 Apr 04 9

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

8.7 Power-down mode

The chip can be put into power-down mode where all static currents are switched off (no internal oscillator, no bias level generation, all LCD-outputs are internally connected to VSS) when PD = logic 1.

During power-down, the whole chip is reset and will restart with a clear display after power-down. Therefore, the whole chip has to be initialized after a power-down as after initial power- up.

The device should be put into ‘display off’ mode (instruction ‘Display control’) before putting the chip in power-down mode, otherwise the LCD output voltages are not defined.

8.8 Registers

The PCF2113x has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select signal (RS) determines which register will be accessed. The instruction register stores instruction codes such as ‘Display clear’ and ‘Cursor shift’, and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written from but not read by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the ‘Read data’ instruction.

8.9 Busy Flag

The Busy Flag indicates the free/busy status of the PCF2113x. Logic 1 indicates that the chip is busy and further instructions will not be accepted. The Busy Flag is output to pin DB7 when RS = logic 0 and R/

W = logic 1. Instructions should only be written after checking that the Busy Flag is logic 0 or waiting for the required number of cycles.

8.10 Address Counter (AC)

The Address Counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the instructions ‘Set CGRAM address’ and ‘Set DDRAM address’. After a read/write operation the Address Counter is automatically incremented or decremented by 1. The Address Counter contents are output to the bus (DB6 to DB0) when RS = logic 0 and R/

W = logic 1.

8.11 Display Data RAM (DDRAM)

The DDRAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic DDRAM-to-display mapping is shown in Fig.3. With no display shift the characters represented by the codes in the first 24 RAM locations starting at address 00 in line 1 are displayed. Figures 4 and 5 show the display mapping for right and left shift respectively.

When data is written to or read from the DDRAM wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap- around operations for the various modes are shown in Table 3.

Table 3 Address space and wrap-around operation

8.12 Character Generator ROM (CGROM)

The Character Generator ROM (CGROM) generates 240 character patterns in 5 × 8 dot format from 8-bit character codes. Figures 7, 8 and 9 show the character sets that are currently implemented.

8.13 Character Generator RAM (CGRAM)

Up to 16 user defined characters may be stored in the Character Generator RAM (CGRAM). Some CGRAM characters (see Fig.17) are also used to drive icons (6 if icons blink and both icon rows are used in application; 3 if no blink but both icon rows are used in application; 0 if no icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.7). Figure 10 shows the addressing principle for the CGRAM.

MODE 1 × 24 2 × 12

address space 00 to 4F 00 to 27; 40 to 67 read/write wrap-around

(moves to next line)

4F to 00 27 to 40; 67 to 00

display shift wrap-around (stays within line)

4F to 00 27 to 00; 67 to 40

Page 10

1997 Apr 04 10

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

8.14 Cursor control circuit

The cursor control circuit generates the cursor (underline and/or cursor blink as shown in Fig.6) at the DDRAM address contained in the Address Counter. When the Address Counter contains the CGRAM address the cursor will be inhibited.

8.15 Timing generator

The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses.

8.16 LCD row and column drivers

The PCF2113x contains 18 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows.

The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 11, 12 and 13 show typical waveforms. Unused outputs should be left unconnected.

Fig.3 DDRAM-to-display mapping: no shift.

handbook, full pagewidth

00 01 02 03 04 15 16 17 18 19 4C 4D 4E 4F

non-displayed DDRAM addresses

64 65 66 6740 41 42 43 44 49 4A 4B 4C 4D

00 01 02 03 04 09 0A 0B 0C 0D 24 25 26 27

non-displayed DDRAM address

line 1

line 2

MGE991

DDRAM address

2-line display

12345 222324

12345 101112

display position

DDRAM address

1-line display

Fig.4 DDRAM-to-display mapping: right shift.

handbook, halfpage

MGE992

27 00 01 02 03

67 40 41 42 43

08 09 0A

48 49 4A

DDRAM address

line 1

line 2

2-line display

1 2 3 4 5 22 23 24

1 2 3 4 5 10 11 12

4F 00 01 02 03 14 15 16

display position

DDRAM address

1-line display

Page 11

1997 Apr 04 11

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.5 DDRAM-to-display mapping: left shift.

handbook, halfpage

01 04 05

41 42 43 44 45

0A 0B 0C

4A 4B 4C

DDRAM address

line 1

line 2

2-line display

1 2 3 4 5 22 23 24

1 2 3 4 5 10 11 12

01 04 05

02 03

02 03 16 17 18

display position

DDRAM address

1-line display

MGE993

Fig.6 Cursor and blink display examples.

MGA801

cursor

5 x 7 dot character font alternating display

cursor display example blink display example

Page 12

1997 Apr 04 12

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.7 Character set ‘A’ in CGROM: PCF2113A.

handbook, full pagewidth

MGE994

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

upper

4 bits

lower 4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111 16

Page 13

1997 Apr 04 13

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.8 Character set ‘D’ in CGROM: PCF2113D.

handbook, full pagewidth

MGD688

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

upper

4 bits

lower 4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111 16

Page 14

1997 Apr 04 14

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.9 Character set ‘E’ in CGROM: PCF2113E.

handbook, full pagewidth

MGD689

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

upper

4 bits

lower 4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111 16

Page 15

1997 Apr 04 15

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.10 Relationship between CGRAM addresses and data and display patterns.

Character code bits 0to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with

the cursor. Data in the 8

position will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in this figure. CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ instruction. Bit 6 can be set using the ‘set DDRAM address’ instruction in

the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘Read busy flag and address’ instruction.

handbook, full pagewidth

MGE995

76543210 6543210 43210

higher

order

bits

lower order

bits

lower order

bits

higher

order

bits

lower order

bits

higher

order

bits

00000000 0000000 0

001 000 010 000 011 0 100 0 00 101 00 0 110 000 111 00000

000 000 001 0 0 0 010

00 00011 100 101 00 00 110 00 00 111 00000

001

00000001 0001

00000010

00001111 00001111 00001111 00001111

010 0000

100 101 110 1

1 1 1 1

1 1 1 111

character codes

(DDRAM data)

CGRAM address

character patterns

(CGRAM data)

43210

000

111 000

0 0010 00 01 000

1 1

1111

1 1 1

000

1 101

000 111

0 1111 01 00 010

1 1

0100

1 0 0

000

character code (CGRAM data)

character

pattern

example 1

cursor

position

character

pattern

example 2

Page 16

1997 Apr 04 16

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.11 Typical LCD waveforms; character mode.

handbook, full pagewidth

MGE996

state 1 (ON) state 2 (OFF)

frame n + 1 frame n

123 18123 18

ROW 1

LCD

V3/V

ROW 9

LCD

V3/V

ROW 2

LCD

V3/V

COL1

LCD

V3/V

COL2

LCD

V3/V

0 V

state 1

0.5V

0.25V

−0.25V

−0.5V

−V

0 V

state 2

0.5V

0.25V

−0.25V

−0.5V

−V

R1 R2 R3 R4 R5 R6 R7 R8

Page 17

1997 Apr 04 17

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.12 MUX 1 : 2 LCD waveforms; icon-mode.

handbook, full pagewidth

MGE997

frame n + 1 frame n

LCD

2/3 1/3

LCD

2/3 1/3

LCD

2/3 1/3

LCD

2/3 1/3

LCD

2/3 1/3

LCD

2/3 1/3

LCD

2/3 1/3

COL 4

OFF/OFF

COL 3

ON/ON

COL 2

OFF

/ON

COL 1

ON/OFF

ROW 1 to 16

ROW 18

ROW 17

only icons are driven (MUX 1 : 2)

Page 18

1997 Apr 04 18

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.13 MUX 1 : 2 LCD waveforms; icon-mode.

ON(rms)

= 0.745VOP.

OFF(rms)

= 0.333VOP.

OFF

-------------

2.23==

handbook, full pagewidth

MGE998

frame n + 1 frame n

2/3 V

1/3 V

−1/3 V

−2/3 V

−V

2/3 V

1/3 V

−1/3 V

−2/3 V

−V

2/3 V

1/3 V

−1/3 V

−2/3 V

−V

state 3

COL 1 -

ROW 1 to 16

state 2

COL 2 -

ROW 17

state 1

COL 1 -

ROW 17

state 3 (OFF)

R17 R18 R1-16

PIXEL

state 1 (ON) state 2 (OFF)

Page 19

1997 Apr 04 19

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

8.17 Reset function

The PCF2113x automatically initializes (resets) when power is turned on. The chip executes a reset sequence, requiring 165 OSC cycles. After the reset the chip’s functions are in the states shown in Table 4.

Table 4 State after reset

STEP FUNCTION RESET STATE (BIT/REGISTER) RESET STATE (DESCRIPTION)

1 clear display 2 entry mode set I/D = 1 +1 (increment)

S = 0 no shift

3 display control D = 0 display off

C = 0 cursor off B = 0 cursor character blink off

4 function set DL = 1 8-bit interface

M = 0 1-line display H = 0 normal instruction set

5 default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = logic 1) until initialization

ends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 17 and 18 6 icon control IM, IB = 00 icons/icon blink disabled 7 display/screen conﬁguration L, P, Q= 000 default conﬁgurations 8V

LCD

temperature coefﬁcient TC1, TC2 = 00 default temperature coefﬁcient

9 set V

LCD

VA, VB=0 V

LCD

generator off

10 I

C-bus interface reset

Page 20

1997 Apr 04 20

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

9 INSTRUCTIONS

Only two PCF2113x registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers, to allow interface to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ICs. The format for instructions when I2C-bus control is used is shown in Table 5. The PCF2113x operation is controlled by the instructions shown in Table 6, which also gives execution times in clock cycles. Details are explained in subsequent sections.

Instructions are of 4 types, those that:

1. Designate PCF2113x functions such as display format, data length, etc.

2. Set internal RAM addresses

3. Perform data transfer with internal RAM

4. Others.

In normal use, category 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency.

During internal operation, no instruction other than the ‘Read busy flag and address’ instruction will be executed. Because the Busy Flag is set to logic 1 while an instruction is being executed, check to make sure it is on logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 6. An instruction sent while the Busy Flag is logic 1 will not be executed.

Table 5 Instruction format for I

C-bus instructions

Note

1. R/

W is set together with the slave address.

CONTROL BYTE

(1)

COMMAND BYTE

CoRS000000DB7DB6DB5DB4DB3DB2DB1DB0

Page 21

1997 Apr 04 21

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Table 6 Instructions

INSTRUCTION RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DESCRIPTION

REQUIRED

CLOCK

CYCLES

H=0or1

NOP 0000000000no operation 3 Function set 00001DL0M0Hsets interface Data Length (DL) and number of

display lines (M); extended instruction set control (H)

Read busy ﬂag and address

0 1 BF A

reads the Busy Flag (BF) indicating internal operating is being performed and reads Address Counter contents

Read data 1 1 read data reads data from CGRAM or DDRAM 3 Write data 1 0 write data writes data from CGRAM or DDRAM 3

H=0

Clear display 0000000001clears entire display and sets DDRAM address 0 in

Address Counter

165

Return home 0000000010sets DDRAM address 0 in Address Counter; also

returns shifted display to original position; DDRAM contents remain unchanged

Entry mode set 00000001I/DSsets cursor move direction and speciﬁes shift of

display; these operations are performed during data write and read

Display control 0000001DCBsets entire display on/off (D), cursor on/off (C) and

blink of cursor position character (B); D = 0 (display off) puts chip into power-down mode

Cursor/display shift

000001S/CR/L00moves cursor and shifts display without changing

DDRAM contents

Set CGRAM address

0001 A

sets CGRAM address; bit 6 is to be set by the instruction ‘Set DDRAM address’; look at the description of the instructions

Set DDRAM address

001 A

sets DDRAM address 3

Page 22

1997 Apr 04 22

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Note

1. X=don’t care.

H=1

Reserved 0000000001do not use − Screen

conﬁguration

000000001Lset screen conﬁguration 3

Display conﬁguration

00000001PQset display conﬁguration 3

Icon control 0000001IMIB0set icon mode (IM), icon blink (IB) 3 Temperature

control

00000100TC1TC2set temperature coefﬁcient (TCx) 3

Reserved 0001X

(1)X(1)X(1)X(1)X(1)X(1)

do not use −

Set V

LCD

0 0 1 V voltage store V

LCD

in register VAor VB (V) 3

INSTRUCTION RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DESCRIPTION

REQUIRED

CLOCK

CYCLES

Page 23

1997 Apr 04 23

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Table 7 Explanations of symbols used in Table 6

Table 8 Explanation of TC1 and TC2 used in Table 6

BIT 0 1

I/D decrement increment S display freeze display shift D display off display on C cursor off cursor on B cursor character blink off: character at cursor

position does not blink

cursor character blink on: character at cursor

position blinks S/C cursor move display shift R/L left shift right shift DL 4 bits 8 bits H use basic instruction set use extended instruction set L (no impact, if

M=1)

left/right screen: standard connection (as in PCF2114); 1st 12 characters of 24: columns are from 1 to 60 2nd 12 characters of 24: columns are from 1 to 60

left/right screen: mirrored connection

(as in PCF2116);

1st 12 characters of 24: columns are from

1to60

2nd 12 characters of 24: columns are from

60 to 1 P column data: left to right (as in PCF2116);

column data is displayed from 1 to 60

column data: right to left;

column data is displayed from 60 to 1 Q row data: top to bottom (as in PCF2116);

row data is displayed from 1 to 16 and icon row data is in 17 and 18

row data: bottom to top;

row data is displayed from 16 to 1 and icon

row data is in 18 and 17 IM character mode; full display icon mode; only icons displayed IB icon blink disabled icon blink enabled V set V

set V

M 1-line by 24 display 2-line by 12 display C

last control byte; see Table 5 another control byte follows after data/instruction

TC1 TC2 DESCRIPTION

00V

LCD

temperature coefﬁcient 0

10V

LCD

temperature coefﬁcient 1

01V

LCD

temperature coefﬁcient 2

11V

LCD

temperature coefﬁcient 3; for ranges for TC see Chapter 15

Page 24

1997 Apr 04 24

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.14 4-bit transfer example.

MGA804

DB7

R/W

DB6

DB5

DB4

instruction

write

busy flag and

address counter read

data register

read

IR7 IR3 BF AC3 DR7 DR3

IR6 IR2 AC6 AC2 DR6 DR2

IR5 IR1 AC5 AC1 DR5 DR1

IR4 IR0 AC4 AC0 DR4 DR0

Fig.15 An example of 4-bit data transfer timing sequence.

IR7, IR3: instruction 7th, 3rd bit. AC3: Address Counter 3rd bit. D7, D3: data 7th, 3rd bit.

MGA805

internal

DB7

R/W

internal operation

IR7 IR3 AC3 D7 D3

not

busy

AC3

busy

instruction

write

busy flag

check

busy flag

check

instruction

write

Page 25

1997 Apr 04 25

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.16 Example of Busy Flag checking timing sequence.

MGA806

instruction

write

busy flag

check

busy flag

check

busy flag

check

instruction

write

internal operation

internal

DB7

R/W

data busy busy

not

busy

data

9.1 Clear display

‘Clear display’ writes character code 20 (hexadecimal) into all DDRAM addresses (the character pattern for character code 20 must be blank pattern), sets the DDRAM Address Counter to logic 0 and returns display to its original position if it was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the display. Sets entry mode I/D = logic 1 (increment mode). S of entry mode does not change.

The instruction ‘Clear display’ requires extra execution time. This may be allowed by checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed. The latter must be applied where no read-back options are foreseen, as in some Chip-On-Glass (COG) applications.

9.2 Return home

‘Return home’ sets the DDRAM Address Counter to logic 0 and returns display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the first display line. I/D and S of entry mode do not change.

9.3 Entry mode set

9.3.1 I/D When I/D = logic 1 (0) the DDRAM or CGRAM address

increments (decrements) by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor underline and cursor character blink are inhibited when the CGRAM is accessed.

9.3.2 S When S = logic 1, the entire display shifts either to the right

(I/D = logic 0) or to the left (I/D = logic 1) during a DDRAM write. Thus it looks as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing into or reading out of the CGRAM. When S = logic 0 the display does not shift.

Page 26

1997 Apr 04 26

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

9.4 Display control (and partial power-down mode)

9.4.1 D The display is on when D = logic 1 and off when

D = logic 0. Display data in the DDRAM are not affected and can be displayed immediately by setting D to logic 1.

When the display is off (D = logic 0) the chip is in partial power-down mode:

• The LCD-outputs are connected to V

• The LCD generator and bias generator are turned off. 3 OSC cycles are required after sending the ‘Display off’

instruction to ensure all outputs are at VSS, afterwards OSC can be stopped. If the oscillator is running during partial power-down mode (‘Display off’) the chip can still execute instructions. Even lower current consumption is obtained by inhibiting the oscillator (OSC = VSS).

To ensure IDD<1µA the parallel bus pins DB7 to DB0 should be connected to VDD; RS, R/W, to VDD or left open and PD to VDD. Recovery from power-down mode: PD back to logic 0, if necessary OSC back to VDD, send a ‘Display control’ instruction with D = logic 1.

9.4.2 C The cursor is displayed when C = logic 1 and inhibited

when C = logic 0. Even if the cursor disappears, the display functions I/D, etc. remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.6).

9.4.3 B The character indicated by the cursor blinks when

B = logic 1. The cursor character blink is displayed by switching between display characters and all dots on with

a period of approximately 1 s, with The cursor underline and the cursor character blink can be

set to display simultaneously.

9.5 Cursor/display shift

‘Cursor/display shift’ moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line.

BLINK

OSC

52224

---------------- -

The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the ‘cursor shift’.

9.6 Function set

9.6.1 DL (

PARALLEL MODE ONLY)

Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = logic 1 or in two nibbles (DB7 to DB4) when DL = logic 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 should be left open (internal pull-ups). Hence in the first ‘Function set’ instruction after power-on N and H are set to logic 1. A second ‘Function set’ must then be sent (2 nibbles) to set N and H to their required values.

‘Function set’ from I2C-interface sets the DL bit to logic 1.

9.6.2 M Chooses either 1-line by 24 display (M = 0) or 2-line by

12 display (M = 1).

9.6.3 H When H = logic 0 the chip can be programmed via the

standard 11 instruction codes used in the PCF2116 and other LCD controllers.

When H = logic 1 the extended range of instructions will be used. These are mainly for controlling the display configuration and the icons.

9.7 Set CGRAM address

‘Set CGRAM address’ sets bits 5 to 0 of the CGRAM address (A

in Table 6) into the Address Counter (binary A[5] to A[0]). Data can then be written to or read from the CGRAM.

Attention: the CGRAM address uses the same address register as the DDRAM address and consists of 7 bits (binary A[6] to A[0]). With the ‘Set CGRAM address’ instruction, only bits 5 down to 0 are set. Bit 6 can be set using the ‘Set DDRAM address’ instruction first, or by using the auto-increment feature during CGRAM write. All of bits 6 to 0 can be read using the ‘Read busy flag and address’ instruction.

When writing to the lower part of the CGRAM, make sure that bit 6 of the address is not set (e.g. by an earlier DDRAM write or read action).

Page 27

1997 Apr 04 27

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

9.8 Set DDRAM address

‘Set DDRAM address’ sets the DDRAM address (ADD in Table 6) into the Address Counter (binary A[6] to A[0]). Data can then be written to or read from the DDRAM.

9.9 Read busy ﬂag and address

‘Read busy flag and address’ reads the Busy Flag (BF) and Address Counter (AC). BF = logic 1 indicates that an internal operation is in progress. The next instruction will not be executed until BF = logic 0, so BF should be checked before sending another instruction.

At the same time, the value of the Address Counter expressed in binary A[6] to A[0] is read out. The Address Counter is used by both CGRAM and DDRAM, and its value is determined by the previous instruction.

9.10 Write data to CGRAM or DDRAM

‘Write data’ writes binary 8-bit data D[7] to D[0] to the CGRAM or the DDRAM.

Whether the CGRAM or DDRAM is to be written into is determined by the previous ‘Set CGRAM address’ or ‘Set DDRAM address’ instruction. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits D[4] to D[0] of CGRAM data are valid, bits D[7] to D[5] are ‘don’t care’.

9.11 Read data from CGRAM or DDRAM

‘Read data’ reads binary 8-bit data D[7] to D[0] from the CGRAM or DDRAM.

The most recent ‘Set address’ instruction determines whether the CGRAM or DDRAM is to be read.

The ‘Read data’ instruction gates the content of the Data Register (DR) to the bus while E is high. After E goes low again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR.

Note: the only three instructions that update the Data Register (DR) are:

• ‘Set CGRAM address’

• ‘Set DDRAM address’

• ‘Read data’ from CGRAM or DDRAM.

Other instructions (e.g. ‘Write data’, ‘Cursor/display shift’, ‘Clear display’, ‘Return home’) do not modify the data register content.

10 EXTENDED FUNCTION SET INSTRUCTIONS AND

FEATURES

10.1 New instructions

H = logic 1 sets the chip into alternate instruction set mode.

10.2 Icon control

The PCF2113x can drive up to 120 icons. See Fig.17 for CGRAM to icon mapping.

10.3 IM

When IM = logic 0 the chip is in character mode. In character mode characters and icons are driven (MUX 1 : 18). The V

LCD

generator, if used, produces the

LCD

voltage programmed in register VA.

When IM = logic 1 the chip is in icon mode. In icon mode only the icons are driven (MUX 1 : 2) and the V

LCD

voltage

generator, if used, produces the V

LCD

voltage

programmed in register VB.

Remark: If internally generated V

LCD

must not be lower

than VDD(VDD≤ 4V)

10.4 IB

Icon blink control is independent of the cursor/character blink function.

When IB = logic 0 icon blink is disabled. Icon data is stored in CGRAM character 0 to 2 (3 × 8 × 5 = 120 bits for 120 icons).

When IB = logic 1 icon blink is enabled. In this case each icon is controlled by two bits. Blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter).

Icon states for the even phase are stored in CGRAM characters 0 to 2 (3 × 8 × 5 = 120 bits for 120 icons). These bits also define icon state when icon blink is not used.

Icon states for the odd phase are stored in CGRAM character 4 to 6 (another 120 bits for the 120 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as normal CGRAM characters.

Page 28

1997 Apr 04 28

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Table 9 Blink effect for icons and cursor character blink

PARAMETER EVEN PHASE ODD PHASE

Cursor underline on off Cursor character blink block (all on) normal (display character) Icons state 1: CGRAM character 0 to 2 state 2: CGRAM character 4 to 6

Fig.17 CGRAM to icon mapping.

CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off. Data in character codes 0 to 2 define the icon-states when icon blink is disabled or during the even phase when icon blink is enabled. Data in character codes 4 to 6 define the icon-state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).

handbook, full pagewidth

COL 1 to 5

12345

61 62 63 64 65

display:

ROW 17 –

ROW 18 –

block of 5 columns

COL 6 to 10

678910

66 67 68 69 70

COL 56 to 60

56 57 58 59 60

116 117 118 119 120

MGE999

handbook, full pagewidth

MGG001

116-120 odd (blink) 18/56-60 0 0 0 0 0 1 1 0

icon view

0 1 1 0 0 1 1 0 0 1 1 0

1-5 odd (blink) 17/1-5 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0

116-120 even 18/56-60 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1

61-65 even 18/1-5 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0

56-60 even 17/56-60 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1

11-15 even 17/11-15 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0

6-10 even 17/6-10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0

1-5 even 17/1-5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1

7 6 5 4 3 2 1 0

MSB LSB LSB

MSB MSBLSB

6 5 4 3 2 1 0 4 3 2 1 0

icon no. phase ROW/COL character codes CGRAM address CGRAM data

Page 29

1997 Apr 04 29

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

10.5 Normal/Icon mode operation

10.6 Screen conﬁguration

L: default is L = logic 0. L = logic 0: the two halves of a split screen are connected

in a standard way i.e. column 1/61, 2/62 to 60/120. L = logic 1: the two halves of a split screen are connected

in a mirrored way i.e. column 1/120, 2/119 to 60/61. This allows single layer PCB or glass layout.

10.7 Display conﬁguration

P, Q: default is P, Q = logic 0. P = logic 1 mirrors the column data. Q = logic 1 mirrors the row data.

10.8 TC1, TC2

Default is TC1, TC2 = logic 0. This selects the default temperature coefficient for the internally generated V

LCD

. TC1,TC2 = 10,01 and 11 selects alternative temperature coefficients 1, 2 and 3 respectively.

10.9 Set V

LCD

value is programmed by instruction. Two on-chip

registers hold V

LCD

values for character mode and icon

mode respectively (VAand VB). The generated V

LCD

value is independent of VDD, allowing battery operation of the chip. VB must be programmed to FF in character mode (i.e. using VA) and VA must be programmed to 00 in icon mode.

Note: If internally generated V

LCD

must not be lower

than VDD.

Note:

IM CONDITION V

LCD

0 character mode generates V

1 icon mode generates V

4V≤

LCD

programming:

1. send ‘Function set’ instruction with H = 1

2. send ‘Set V

LCD

’ instruction to write to voltage register:

a) DB7, DB6 = 10: DB5 to DB0 are V

LCD

of character

mode (VA)

b) DB7, DB6 = 11: DB5 to DB0 are V

LCD

of icon mode

(VB)

c) DB5 to DB0 = 000000 switches V

LCD

generator off

(when selected)

d) During ‘display off’ and power-down V

LCD

generator is also disabled

3. send ‘Function set’ instruction with H = 0 to resume normal programming.

10.10 Reducing current consumption

Reducing current consumption can be achieved by one of the options mentioned in Table 10.

Table 10 Reducing current consumption

When V

LCD

lies outside the VDD range and must be generated, it is usually more efficient to use the on-chip generator than an external regulator.

Table 11 Use of the V

and VB registers

ORIGINAL

MODE

ALTERNATIVE MODE

Character mode icon mode (control bit IM) Display on display off (control bit D)

MODE V

Normal operation V

LCD

character

mode

LCD

icon mode

Page 30

1997 Apr 04 30

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

11 INTERFACE TO MICROCONTROLLER

(PARALLEL INTERFACE)

The PCF2113x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers.

In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three further control lines E, RS, and R/

W are required. See Chapter 7.

In 4-bit mode data is transferred in two cycles of 4 bits each using pins DB7 to DB4 for transaction. The higher order bits (corresponding to DB7 to DB4 in 8-bit mode) are sent in the first cycle and the lower order bits (DB3 to DB0 in 8-bit mode) in the second. Data transfer is complete after two 4-bit data transfers. Note that two cycles are also required for the Busy Flag check. 4-bit operation is selected by instruction. See Figs 14 to 17 for examples of bus protocol.

In 4-bit mode pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally.

12 INTERFACE TO MICROCONTROLLER

C-BUS INTERFACE)

12.1 Characteristics of the I

C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.

Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.

12.2 I

C-bus protocol

Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The I2C-bus configuration for the different PCF2113x read and write cycles is shown in Figs 23 and 24. The slow down feature of the I2C-bus protocol (receiver holds SCL low during internal operations) is not used in the PCF2113x.

12.3 Deﬁnitions

• Transmitter: the device which sends the data to the bus

• Receiver: the device which receives the data from the

bus

• Master: the device which initiates a transfer, generates

clock signals and terminates a transfer

• Slave: the device addressed by a master

• Multi-Master: more than one master can attempt to

control the bus at the same time without corrupting the message

• Arbitration: procedure to ensure that, if more than one

master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clock

signals of two or more devices.

Page 31

1997 Apr 04 31

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

MGA807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

Fig.18 System configuration.

MBC621

data line

stable;

data valid

change of data

allowed

SDA

SCL

Fig.19 Bit transfer.

MBC622

SDA

SCL

STOP condition

SDA

SCL

START condition

Fig.20 Definition of START and STOP conditions.

MBC602

START

CONDITION

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

Fig.21 Acknowledgement on the I2C-bus.

Page 32

1997 Apr 04 32

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.22 Master transmits to slave receiver; write mode.

ok, full pagewidth

MGG002

S A

S P

011101

slave address

CONTROL BYTE

DATA BYTE

CONTROL BYTE

R/W

update

data pointer

1 byte n ≥ 0 bytes2n ≥ 0 bytes

DATA BYTE

acknowledgement

from PCF2113x

RS RS

S A

011101

PCF2113x

slave address

R/W

Page 33

1997 Apr 04 33

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

gewidth

MGG003

S A 0

011101

slave address

CONTROL BYTE

DATA BYTE

CONTROL BYTE

R/W

Co update

data pointer

update

data pointer

1 byte n ≥ 0 bytes

n bytes last byte

2n 0 bytes

DATA BYTE

(1)

acknowledgement

S A 0

1A DATA BYTE A 1

SLAVE

ADDRESS

DATA BYTE

acknowledgement acknowledgement no acknowledgement

R/W

RS RS

Fig.23 Master reads after setting word address; write word address, set RS; ‘read data’.

(1) Last data byte is a dummy byte (may be omitted).

Page 34

1997 Apr 04 34

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.25 I2C-bus timing diagram.

ook, full pagewidth

SDA

MGA728

SDA

SCL

SU;STA

SU;STO

HD;STA

BUF

LOW

HD;DAT

HIGH

SU;DAT

Fig.24 Master reads slave immediately after first byte; read mode (RS previously defined).

handbook, full pagewidth

MGG004

Co update

data pointer

update

data pointer

n bytes last byte

S A 0

1A DATA BYTE A 1

SLAVE

ADDRESS

DATA BYTE

acknowledgement

from PCF2113x

acknowledgement

from master

no acknowledgement

from master

R/W

Page 35

1997 Apr 04 35

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

13 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

14 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see

“Handling MOS Devices”

SYMBOL PARAMETER MIN. MAX. UNIT

supply voltage −0.5 +6.5 V

LCD

LCD supply voltage −0.5 +7.5 V

input voltage OSC, RS, R/W, E and DB7 to DB0 −0.5 VDD+ 0.5 V

output voltage R1 to R18, C1 to C60 and V

LCD

−0.5 V

LCD

+ 0.5 V

DC input current −10 +10 mA

DC output current −10 +10 mA

, ISS, I

LCDVDD

, VSS or V

LCD

current −50 +50 mA

tot

total power dissipation − 400 mW

power dissipation per output − 100 mW

stg

storage temperature −65 +150 °C

Page 36

1997 Apr 04 36

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

15 DC CHARACTERISTICS

= 1.8 to 4.0 V (external V

LCD

: VDD= 1.8 to 5.5 V); VSS=0V; V

LCD

= 2.2 to 6.5 V; T

amb

= −40 to +85 °C;

unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

supply voltage internal V

LCD

generation 1.8 − 4.0 V

supply voltage external V

LCD

1.8 − 5.5 V

LCD

LCD supply voltage 2.2 − 6.5 V

supply current, external V

LCD

note 1

SS1

supply current 1 − 60 120 µA

SS3

supply current 3 VDD=3V; V

LCD

=5V;

note 2

− 45 80 µA

SS4

supply current 4 (icon mode) VDD=3V; V

LCD

= 2.5 V;

note 2

− 25 45 µA

SS5

supply current 5 (power-down mode)

VDD=3V; V

LCD

= 2.5 V; DB7 to DB0, RS, R/W=1; OSC = 0; PD = 1

− 0.5 5 µA

supply current, internal V

LCD

notes 1, 3

SS6

supply current 6 − 200 400 µA

SS8

supply current 8 VDD=3V; V

LCD

=5V; note 2

− 200 400 µA

SS9

supply current 9 (icon mode) VDD=3V; V

LCD

= 2.5 V; note 2

− 100 −µA

POR

Power-on reset voltage level note 4 − 1.3 1.6 V

Logic

IL1

LOW level input voltage T1, E, RS, R/W, DB[7..0] and SA0

0 − 0.3V

IH1

HIGH level input voltage T1, E, RS, R/W, DB[7..0] and SA0

0.7V

− V

IL(PD)

LOW level input voltage PD 0 − 0.2V

IH(PD)

HIGH level input voltage PD 0.8V

− V

IL(osc)

LOW level input voltage OSC 0 − VDD− 1.5 V

IH(osc)

HIGH input voltage OSC VDD− 0.1 − V

OL(DB)

LOW level output current DB[7..0] VOL= 0.4 V; VDD= 5 V 1.6 4 − mA

OH(DB)

HIGH level output current DB[7..0] VOH=4V; VDD=5V −1.0 −− mA

pull-up current DB[7..0] VI=V

0.04 0.15 1 µA

leakage current OSC, E, RS, R/W, DB[7..0] and SA0

VI=VDDor V

−1.0 − +1.0 µA

Page 37

1997 Apr 04 37

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Notes

1. LCD outputs are open-circuit; inputs at VDDor VSS; bus inactive.

2. T

amb

=25°C; f

OSC

= 200 kHz.

3. LCD outputs are open-circuit; HV generator is on; load current I

VLCD

(at V

LCD

)=5µA.

4. Resets all logic when VDD<V

POR

; 3 OSC clock cycles required.

5. Tested on sample basis.

6. Resistance of output terminals (R1 to R18 and C1 to C60) with a load current of 20 µA; outputs measured one at a time; external V

LCD

7. LCD outputs open-circuit; external V

LCD

8. Temperature coefficient at VOP= 5.0 V. Typical range ±2 mV/K.

C-bus

SDA AND SCL V

IL2

LOW level input voltage 0 − 0.3V

IH2

HIGH level input voltage 0.7V

− 5.5 V

input leakage current VI=VDDor V

−1 − +1 µA

input capacitance note 5 −−10 pF

OL(SDA)

LOW level output current (SDA) VOL= 0.4 V; VDD=5V 3 −− mA

LCD outputs

ROW

row output resistance R1 to R18 note 6 − 10 30 kΩ

COL

column output resistance C1 to C60 note 6 − 15 40 kΩ

tol1

bias voltage tolerance R1 to R18 and C1 to C60

note 7 − 20 130 mV

tol2a

LCD

tolerance T

amb

=25°C;V

LCD

<3V;

note 3

−−200 mV

tol2b

LCD

tolerance T

amb

=25°C; V

LCD

<4V;

note 3

−−350 mV

tol2c

LCD

tolerance T

amb

=25°C; V

LCD

<5V;

note 3

−−400 mV

TC0 V

LCD

temperature coefﬁcient 0 note 8 −−7.6 − mV/K

TC1 V

LCD

temperature coefﬁcient 1 note 8 −−8.4 − mV/K

TC2 V

LCD

temperature coefﬁcient 2 note 8 −−10.4 − mV/K

TC3 V

LCD

temperature coefﬁcient 3 note 8 −−12.4 − mV/K

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Page 38

1997 Apr 04 38

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

16 AC CHARACTERISTICS

= 1.8 to 5.5 V; VSS=0V; V

LCD

= 2.2 − 6.5 V; T

amb

= −40 to +85 °C; unless otherwise speciﬁed.

Note

1. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V

and VIH with an input voltage swing of VSSto VDD.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

LCD frame frequency (internal clock) VDD= 5.0 V 45 81 147 Hz

OSC

oscillator frequency (not available at any pin) 140 250 450 kHz

OSC

external clock frequency 140 − 450 kHz

OSCST

oscillator start-up time after power-down − 200 300 µs Bus timing characteristics: parallel interface; note 1 WRITE OPERATION (

WRITING DATA FROM MICROCONTROLLER TO PCF2113X)

enable cycle time 500 −−ns PW

enable pulse width 220 −−ns t

ASU

address set-up time 50 −−ns t

AHD

address hold time 25 −−ns t

DSW

data set-up time 60 −−ns t

data hold time 25 −−ns READ OPERATION (READING DATA FROM PCF2113X TO MICROCONTROLLER) T

enable cycle time 500 −−ns PW

enable pulse width 220 −−ns t

ASU

address set-up time 50 −−ns t

address hold time 25 −−ns t

DHD

data delay time −−150 ns t

data hold time 20 − 100 ns

Timing characteristics: I

C-bus interface; note 1

SCL

SCL clock frequency −−400 kHz t

LOW

SCL clock low period 1.3 −−µs t

HIGH

SCL clock high period 0.6 −−µs t

SU;DAT

data set-up time 100 −−ns t

HD;DAT

data hold time 0 −−ns t

SCL, SDA rise time −−300 ns t

SCL, SDA fall time −−300 ns C

capacitive bus line load −−400 pF t

SU;STA

set-up time for a repeated START condition 0.6 −−µs t

HD;STA

START condition hold time 0.6 −−µs t

SU;STO

set-up time for STOP condition 0.6 −−µs t

tolerable spike width on bus −−50 ns

Page 39

1997 Apr 04 39

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

17 TIMING CHARACTERISTICS

Fig.26 Parallel bus write operation sequence; writing data from microcontroller to PCF2113x.

dbook, full pagewidth

DB0 to DB7

V V

IH1 IL1

IH1

IL1

IH1

IL1

IH1 IL1

IL1

IH1

IL1

DSW

Valid Data

MLA798 - 1

R/W

Fig.27 Parallel bus read operation sequence; reading data from PCF2113x to microcontroller.

dbook, full pagewidth

R/W

DB0 to DB7

V V

IH1 IL1

IH1

IL1

IH1

IL1

OL1

OH1

IL1

DHR

IH1

OL1

OH1

DDR

IH1

MLA799 - 1

Page 40

1997 Apr 04 40

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

18 APPLICATION INFORMATION

Fig.28 Direct connection to 8-bit microcontroller; 8-bit bus.

handbook, full pagewidth

PCF2113x

MGG005

P80CL51

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

C1 to C60

RSP20

P21

EP22

DB7 to DB0P17 to P10

R17, R18

R1 to R16

R/W

Fig.29 Direct connection to 8-bit microcontroller; 4-bit bus.

handbook, full pagewidth

PCF2113x

MGG006

P80CL51

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

C1 to C60

RSP10

P11

EP12

DB7 to DB4P17 to P14

R17, R18

R1 to R16

R/W

Fig.30 Typical application using parallel interface.

handbook, full pagewidth

MGG007

PCF2113x

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

C1 to C60

OSC

RSDB7 to DB0 E

100

R17, R18

R1 to R16

LCD

R/W

Page 41

1997 Apr 04 41

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.31 Application using I2C-bus interface.

handbook, full pagewidth

SCL SDA

MASTER TRANSMITTER

PCF84C81A; P80CL410

PCF2113x

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

C1 to C60

OSC

SCL SDA

DB3/SAO

100

R17, R18

R1 to R16

LCD

PCF2113x

1 × 24 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

C1 to C60

OSC

SCL SDA

DB3/SAO

100

R17, R18

R1 to R16

LCD

MGG008

Page 42

1997 Apr 04 42

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

18.1 8-bit operation, 1-line display using internal reset

Table 13 shows an example of a 1-line display in 8-bit operation. The PCF2113x functions must be set by the ‘function set’ instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes display position only and DDRAM contents remain unchanged, display data entered first can be displayed when the ‘return home’ operation is performed.

18.2 4-bit operation, 1-line display using internal reset

The program must set functions prior to 4-bit operation. Table 12 shows an example. When power is turned on, 8-bit operation is automatically selected and the PCF2113x attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required.

However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 12 step 3).

Thus, DB4 to DB7 of the ‘function set’ are written twice.

18.3 8-bit operation, 2-line display

For a 2-line display, the cursor automatically moves from the first to the second line after the 40

digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the eighth character is completed (see Table 5). Note that both lines of the display are always shifted together; data does not shift from one line to the other.

18.4 I

C operation, 1-line display

A control byte is required with most instructions (see Table 16).

Table 12 4-bit operation, 1-line display example; using internal reset

STEP INSTRUCTION DISPLAY OPERATION

1 power supply on (PCF2113x is initialized by

the internal reset circuit)

initialized; no display appears

2 function set

RS R/

W DB7 DB6 DB5 DB4 sets to 4-bit operation; in this instance operation

is handled as 8-bits by initialization and only this instruction completes with one write

000010

3 function set

000010 sets to 4-bit operation, selects 1-line display and

LCD=V0

; 4-bit operation starts from this point

and resetting is needed

000000

4 display on/off control

000000_ turns on display and cursor; entire display is

blank after initialization

001110

5 entry mode set

000000_ sets mode to increment the address by 1 and to

shift the cursor to the right at the time of write to the DD/CGRAM; display is not shifted

000110

6 ‘write data’ to CGRAM/DDRAM

100101P_ writes ‘P’; the DDRAM has already been

selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right

100000

Page 43

1997 Apr 04 43

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Table 13 8-bit operation, 1-line display example; using internal reset (character set ‘A’)

STEP INSTRUCTION DISPLAY OPERATION

1 power supply on (PCF2113x is initialized by the internal reset

function)

initialized; no display appears

2 function set

RS R/

W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 sets to 8-bit operation, selects 1-line display and

LCD=V0

0000110000

3 display mode on/off control

0000001110_ turns on display and cursor; entire display is blank after

initialization

4 entry mode set

0000000110_ sets mode to increment the address by 1 and to shift the

cursor to the right at the time of the write to the DD/CGRAM; display is not shifted

5 ‘write data’ to CGRAM/DDRAM

1001010000P_ writes ‘P’; the DDRAM has already been selected by

initialization at power-on; the cursor is incremented by 1 and shifted to the right

6 ‘write data’ to CGRAM/DDRAM

1001001000PH_ writes ‘H’

7to11 |

12 ‘write data’ to CGRAM/DDRAM

1001010011PHILIPS_ writes ‘S’

13 entry mode set

0000000111PHILIPS_ sets mode for display shift at the time of write

14 ‘write data’ to CGRAM/DDRAM

1000100000HILIPS _ writes space

15 ‘write data’ to CGRAM/DDRAM

1001001101ILIPS M_ writes ‘M’

16 |

| |

Page 44

1997 Apr 04 44

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

17 ‘write data’ to CGRAM/DDRAM

1001001111MICROKO

writes ‘O’

18 cursor/display shift

0000010000MICROK

O shifts only the cursor position to the left

19 cursor/display shift

0000010000MICROKO shifts only the cursor position to the left

20 ‘write data’ to CGRAM/DDRAM

1001000011ICROC

O writes ‘C’ correction; the display moves to the left

21 cursor/display shift

0000011100MICROCO shifts the display and cursor to the right

22 cursor/display shift

0000010100MICROCO_ shifts only the cursor to theright

23 ‘write data’ to CGRAM/DDRAM

1001001101ICROCOM_ writes ‘M’

24 |

| |

25 return home

0000000010

PHILIPS M returns both display and cursor to the original position

(address 0)

STEP INSTRUCTION DISPLAY OPERATION

Page 45

1997 Apr 04 45

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Table 14 8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’)

STEP INSTRUCTION DISPLAY OPERATION

1 power supply on (PCF2113x is initialized by the internal reset

function)

initialized; no display appears

2 function set

RS R/

W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 sets to 8-bit operation, selects 1-line display and

LCD=V0

0000110000

3 display mode on/off control

0000001110_ turns on display and cursor; entire display is blank after

initialization

4 entry mode set

0000000110_ sets mode to increment the address by 1 and to shift the

cursor to the right at the time of the write to the DD/CGRAM; display is not shifted

5 set CGRAM address

0001000000_ sets the CGRAM address to position of character 0; the

CGRAM is selected

6 ‘write data’ to CGRAM/DDRAM

1000001010_ writes data to CGRAM for icon even phase; icons appears

7 |

8 set CGRAM address

0001110000_ sets the CGRAM address to position of character 4; the

CGRAM is selected

9 ‘write data’ to CGRAM/DDRAM

1000001010_ writes data to CGRAM for icon odd phase

10 |

11 function set

0000110001 _ sets H = 1

12 icon control

0 0 0 0 0 0 1 0 1 0 _ icons blink

13 function set

0000110001 _ sets H = 0

Page 46

1997 Apr 04 46

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

14 set DDRAM address

0 0 1 0 0 0 0 0 0 0 sets the DDRAM address to the ﬁrst position; DDRAM is

selected

15 ‘write data’ to CGRAM/DDRAM

1001010000P_ writes ‘P’; the cursor is incremented by 1 and shifted to the

right

16 ‘write data’ to CGRAM/DDRAM

1001001000PH_ writes ‘H’

17 to 20 |

21 return home

0000000010

PHILIPS returns both display and cursor to the original position

(address 0)

STEP INSTRUCTION DISPLAY OPERATION

Page 47

1997 Apr 04 47

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Table 15 8-bit operation, 2-line display example; using internal reset

STEP INSTRUCTION DISPLAY OPERATION

1 power supply on (PCF2113x is initialized by the internal reset

function)

initialized; no display appears

2 function set sets to 8-bit operation; selects 2-line display and voltage

generator off

RS R/

W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0000111000

3 display on/off control turns on display and cursor; entire display is blank after

initialization

0000001110

4 entry mode set sets mode to increment the address by 1 and to shift the

cursor to the right at the time of write to the CG/DDRAM; display is not shifted

0000000110

5 ‘write data’ to CGRAM/DDRAM writes ‘P’; the DDRAM has already been selected by

initialization at power-on; the cursor is incremented by 1 and shifted to the right

1001010000

6to10 |

| |

11 ‘write data’ to CGRAM/DDRAM writes ‘S’

PHILIPS_

1001010011

12 set DDRAM address sets DDRAM address to position the cursor at the head of

the 2nd line

PHILIPS

0011000000_

13 ‘write data’ to CGRAM/ DDRAM writes ‘M’

PHILIPS

1001001101M_

14 to 19 |

| |

Page 48

1997 Apr 04 48

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

20 ‘write data’ to CGRAM/DDRAM writes ‘O’

PHILIPS

1001001111MICROCO_

21 ‘write data’ to CGRAM/DDRAM sets mode for display shift at the time of write

PHILIPS

0000000111MICROCO_

22 ‘write data’ to CGRAM/DDRAM writes ‘M’; display is shifted to the left; the ﬁrst and second

lines shift together

HILIPS

1001001101ICROCOM_

23 |

| |

24 return home returns both display and cursor to the original position

(address 0)

PHILIPS

0000000010MICROCOM

STEP INSTRUCTION DISPLAY OPERATION

Page 49

1997 Apr 04 49

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Table 16 Example of I2C operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1)

STEP I

C BYTE DISPLAY OPERATION

C start initialized; no display appears

2 slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack during the acknowledge cycle SDA will be pulled-down by the

PCF2113x

011101001

3 send a control byte for ‘function set’

Co RS 0 0 0 0 0 0 Ack control byte sets RS for following data bytes 000000001

4 function set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack selects 1-line display and V

LCD=V0

; SCL pulse during

acknowledge cycle starts execution of instruction

001X00001

5 display on/off control _

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack turns on display and cursor; entire display shows character 20H

(blank in ASCII-like character sets)

000011101

6 entry mode set _

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack sets mode to increment the address by 1 and to shift the cursor

to the right at the time of write to the DDRAM or CGRAM; display is not shifted

000001101

C start _

for writing data to DDRAM, RS must be set to 1; therefore a control byte is needed

8 slave address for write _

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/

W Ack

011101001

9 send a control byte for ‘write data’ _

Co RS 0 0 0 0 0 0 Ack 010000001

10 ‘write data’ to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack writes ‘P’; the DDRAM has been selected at power-up; the

cursor is incremented by 1 and shifted to the right

010100001P_

Page 50

1997 Apr 04 50

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

11 ‘write data’ to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack writes ‘H’ 010010001PH_

12 to 15 |

| | |

16 ‘write data’ to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack writes ‘S’ 010100111PHILIPS_

17 (optional I

C stop) I2C start + slave address for write

(as step 8) PHILIPS_

18 control byte

Co RS 0 0 0 0 0 0 Ack 100000001PHILIPS_

19 return home

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack sets DDRAM address 0 in Address Counter (also returns shifted

display to original position; DDRAM contents unchanged); this instruction does not update the Data Register (DR)

000000101

PHILIPS

20 I2C start PHILIPS 21 slave address for read

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/

W Ack during the acknowledge cycle the content of the DR is loaded

into the internal I2C interface to be shifted out; in the previous instruction neither a ‘set address’ nor a ‘read data’ has been performed; therefore the content of the DR was unknown. The R/W has to be set to 1 while still in I2C-write mode.

011101011P

HILIPS

22 control byte for read

Co RS 0 0 0 0 0 0 Ack DDRAM content will be read from following instructions 011000001

PHILIPS

STEP I

C BYTE DISPLAY OPERATION

Page 51

1997 Apr 04 51

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Notes

1. X = don’t care.

2. SDA is left at high-impedance by the microcontroller during the read acknowledge.

23 ‘read data’: 8 × SCL + master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 8 × SCL; content loaded into interface during previous

acknowledge cycle is shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I2C interface

XXXXXXXX0PH

ILIPS

24 ‘read data’: 8 × SCL + master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 8 × SCL; code of letter ‘H’ is read ﬁrst; during master

acknowledge code of ‘I’ is loaded into the I

C interface

010010000PHI

LIPS

25 ‘read data’: 8 × SCL + no master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack no master acknowledge; after the content of the I2C interface

register is shifted out no internal action is performed; no new data is loaded to the interface register, Data Register (DR) is not updated, Address Counter (AC) is not incremented and cursor is not shifted

010010011PHI

LIPS

26 I2C stop PHILIPS

STEP I2C BYTE DISPLAY OPERATION

Page 52

1997 Apr 04 52

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Table 17 Initialization by instruction, 8-bit interface (note 1)

Note

1. X = don’t care.

STEP DESCRIPTION

power-on or unknown state

wait 2 ms after V

rises above V

POR

RS R/

W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction

0 0 0 0 1 1 X X X X function set (interface is 8 bits long)

wait 2 ms

RS R/

W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction

0 0 0 0 1 1 X X X X function set (interface is 8 bits long)

wait more than 40 µs

RS R/

W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction

0 0 0 0 1 1 X X X X function set (interface is 8 bits long)

| |

BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the speciﬁed instruction time (see Table 3)

RS R/

W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 function set (interface is 8 bits long); specify the number of display lines. 0000110M0H 0 0 0 0 0 0 1 0 0 0 display off 0 0 0 0 0 0 0 0 0 1 clear display 0 0 0 0 0 0 0 1 I/D S entry mode set

Initialization ends

Page 53

1997 Apr 04 53

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Table 18 Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation

STEP DESCRIPTION

Power-on or unknown state

Wait 2 ms after V

rises above V

POR

RS R/

W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction

000011function set (interface is 8 bits long)

Wait 2 ms

RS R/

W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction

000011function set (interface is 8 bits long)

Wait 40 µs

RS R/

W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction

000011function set (interface is 8 bits long)

| BF can be checked after the following instructions; when BF is not checked, the waiting time

between instructions is the speciﬁed instruction time (see Table 3)

RS R/

W DB7 DB6 DB5 DB4 function set (set interface to 4 bits long) 000010interface is 8 bits long 000010function set (interface is 4 bits long) 0 0 0 M 0 H specify number of display lines 000000 001000display off 000000clear display 000001 000000entry mode set 0001I/DS

Initialization ends

Page 54

1997 Apr 04 54

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

19 BONDING PAD LOCATIONS

Fig.32 Bonding pad locations.

handbook, full pagewidth

MGG009

C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16

C15 C14 C13 C12 C11

C10

C9 C8 C7 C6 C5 C4 C3 C2

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

C41

C42

C43

C44

C45

C46

C47

C48

C49

C50

C51

C52

C53

C54 C55 C56 C57 C58 C59 C60

R18 R16 R15 R14 R13 R12 R11 R10 R9

LCD1

LCD2

SS2

SS1

T1 PD OSC V

DD1

C1R8R7R6R5R4R3R2R1

R17

SCL

SDA

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DD2

R/W

PCF2113x

≈ 3.94 mm

≈ 4.08

Page 55

1997 Apr 04 55

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Table 19 Bonding pad locations (dimensions in µm)

All x/y coordinates are referenced to centre of chip (see Fig.32).

SYMBOL PAD X Y

DD1

1 1811.3 −1547.1 OSC 2 1811.3 −1416.5 PD 3 1811.3 −1285.9 T1 4 1811.3 −1155.3 V

SS1

5 1811.3 −1024.7 V

SS2

6 1811.3 −822.1 V

LCD2

7 1811.3 −633.9 V

LCD1

8 1811.3 −446.3 R9 9 1811.3 −264.0 R10 10 1811.3 −144.0 R11 11 1811.3 −24.0 R12 12 1811.3 96.0 R13 13 1811.3 216.0 R14 14 1811.3 336.0 R15 15 1811.3 456.0 R16 16 1811.3 576.0 R18 17 1811.3 696.0 C60 18 1811.3 889.4 C59 19 1811.3 1009.4 C58 20 1811.3 1129.4 C57 21 1811.3 1249.4 C56 22 1811.3 1369.4 C55 23 1811.3 1489.4 C54 24 1811.3 1609.4 C53 25 1536.5 1877.7 C52 26 1416.5 1877.7 C51 27 1296.5 1877.7 C50 28 1176.5 1877.7 C49 29 983.9 1877.7 C48 30 863.9 1877.7 C47 31 743.9 1877.7 C46 32 623.9 1877.7 C45 33 503.9 1877.7 C44 34 383.9 1877.7 C43 35 263.9 1877.7 C42 36 143.9 1877.7 C41 37 23.9 1877.7 C40 38 −96.1 1877.7L

C39 39 −216.1 1877.7 C38 40 −336.1 1877.7 C37 41 −456.1 1877.7 C36 42 −576.1 1877.7 C35 43 −696.1 1877.7 C34 44 −816.1 1877.7 C33 45 −936.1 1877.7 C32 46 −1056.1 1877.7 C31 47 −1176.1 1877.7 C30 48 −1296.1 1877.7 C29 49 −1488.7 1877.7 C28 50 −1811.3 1609.4 C27 51 −1811.3 1489.4 C26 52 −1811.3 1369.4 C25 53 −1811.3 1249.4 C24 54 −1811.3 1129.4 C23 55 −1811.3 1009.4 C22 56 −1811.3 889.4 C21 57 −1811.3 769.4 C20 58 −1811.3 649.4 C19 59 −1811.3 529.4 C18 60 −1811.3 409.4 C17 61 −1811.3 289.4 C16 62 −1811.3 169.4 C15 63 −1811.3 23.2 C14 64 −1811.3 −96.8 C13 65 −1811.3 −216.8 C12 66 −1811.3 −336.8 C11 67 −1811.3 −456.8 C10 68 −1811.3 −649.4 C9 69 −1811.3 −769.4 C8 70 −1811.3 −889.4 C7 71 −1811.3 −1009.4 C6 72 −1811.3 −1129.4 C5 73 −1811.3 −1249.4 C4 74 −1811.3 −1369.4 C3 75 −1811.3 −1489.4 C2 76 −1811.3 −1609.4

SYMBOL PAD X Y

Page 56

1997 Apr 04 56

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

C1 77 −1542.7 −1877.7 R8 78 −1422.4 −1877.7 R7 79 −1302.4 −1877.7 R6 80 −1182.4 −1877.7 R5 81 −1062.4 −1877.7 R4 82 −942.4 −1877.7 R3 83 −822.4 −1877.7 R2 84 −702.4 −1877.7 R1 85 −582.4 −1877.7 R17 86 −462.4 −1877.7 SCL 87 −271.2 −1877.7 SDA 88 −130.2 −1877.7 E 89 74.4 −1877.7 RS 90 205.1 −1877.7 RW 91 335.7 −1877.7 DB7 92 468.8 −1877.7 DB6 93 603.8 −1877.7 DB5 94 738.8 −1877.7 DB4 95 873.8 −1877.7 DB3 96 1008.8 −1877.7 DB2 97 1143.8 −1877.7 DB1 98 1278.8 −1877.7 DB0 99 1413.8 −1877.7 V

DD2

100 1546.0 −1877.7 Sign C1 −1518.0 −1387.7 Sign C2 1405.0 1671.3 Sign f −1491.0 1602.3

SYMBOL PAD X Y

Page 57

1997 Apr 04 57

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

20 PACKAGE OUTLINE

UNIT

max.

A1A2A3bpcE

(1)

Zywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

1.6

0.20

0.05

1.5

1.3

0.25

0.28

0.16

0.18

0.12

14.1

13.9

0.5

16.25

15.75

1.15

0.85

7 0

o o

0.12 0.10.21.0

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT407-1

95-12-19 97-08-04

(1) (1)(1)

14.1

13.9

16.25

15.75

1.15

0.85

detail X

(A )

v M

100

pin 1 index

w M

0 5 10 mm

scale

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm

SOT407-1

Page 58

1997 Apr 04 58

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

21 SOLDERING

21.1 Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

“IC Package Databook”

(order code 9398 652 90011).

21.2 Reﬂow soldering

Reflow soldering techniques are suitable for all LQFP packages.

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.

21.3 Wave soldering

Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave) soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves downstream and at the side corners.

Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

21.4 Repairing soldered joints

Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

Page 59

1997 Apr 04 59

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

22 DEFINITIONS

23 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

24 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

Purchase of Philips I

C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

Page 60

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

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Tel. +9-5 800 234 7381 Middle East: see Italy

Printed in The Netherlands 417067/00/02/pp60 Date of release: 1997 Apr 04 Document order number: 9397 750 01753

Datasheet PCF2113DU-10-F3, PCF2113DU-F2, PCF2113DU-F3, PCF2113EU-10-F2, PCF2113EU-10-F3 Datasheet (Philips)

Specifications and Main Features

Frequently Asked Questions

User Manual