• Low output distortion with on-chip filtering conforming to
CEPT recommendations
• Latched inputs for data bus applications
• I2C-bus compatible
• Selection of parallel or serial (I2C-bus) data input
(PCD3311C).
used, and a separate microcontroller is required to control
the devices.
Both the devices can interface to I
2
C-bus compatible
microcontrollers for serial input. The PCD3311C can also
interface directly to all standard microcontrollers,
accepting a binary coded parallel input.
With their on-chip voltage reference the PCD3311C and
PCD3312C provide constant output amplitudes which are
independent of the operating supply voltage and ambient
temperature.
An on-chip filtering system assures a very low total
2GENERAL DESCRIPTION
The PCD3311C and PCD3312C are single-chip silicon
gate CMOS integrated circuits. They are intended
principally for use in telephone sets to provide the
dual-tone multi-frequency (DTMF) combinations required
for tone dialling systems. The various audio output
frequencies are generated from an on-chip 3.58 MHz
quartz crystal-controlled oscillator. A separate crystal is
harmonic distortion in accordance with CEPT
recommendations.
In addition to the standard DTMF frequencies the devices
can also provide:
• Twelve standard frequencies used in simplex modem
applications for data rates from 300 to 1200 bits per
second
• Two octaves of musical scales in steps of semitones.
3QUICK REFERENCE DATA
SYMBOLPARAMETERMIN.TYP.MAX.UNIT
V
DD
I
DD
I
stb
V
HG(RMS)
V
LG(RMS)
G
v
operating supply voltage2.5−6.0V
operating supply current−−0.9mA
standby current−−3µA
DTMF HIGH group output voltage level (RMS value)158192205mV
DTMF LOW group output voltage level (RMS value)125150160mV
pre-emphasis (voltage gain) of group1.852.102.35dB
THDtotal harmonic distortion−−25−dB
T
amb
operating ambient temperature−25−+70°C
4ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAMEDESCRIPTIONVERSION
PCD3311CPDIP14plastic dual in-line package; 14 leads (300 mil)SOT27-1
PCD3311CTSO16plastic small outline package; 16 leads; body width 7.5 mmSOT162-1
PCD3312CPDIP8plastic dual in-line package; 8 leads (300 mil)SOT97-1
PCD3312CTSO8plastic small outline package; 8 leads; body width 7.5 mmSOT176-1
The Input Control Logic decodes the input data to
determine whether DTMF, modem or musical tones are
selected; and which particular tone or combination of
tones is required.
A code representing the required tones is sent to the
Divider Selection ROM which selects the correct division
ratio in both of the Frequency Dividers (or in one divider, if
only a single tone is required).
The Oscillator circuit provides a square wave of frequency
3.58 MHz. Each Frequency Divider divides the frequency
of the Oscillator to give a serial digital square wave with a
frequency simply related to that of the required tone.
The output from each Frequency Divider goes to a DAC,
which is also fed by a clock derived from the oscillator.
Using these two signals, the DAC produces an
approximate sine wave of the required frequency, with an
amplitude derived from the Voltage Reference.
The output from the DAC goes to an Adder where, for
DTMF, it is combined with the output from the other DAC.
The output from the Adder goes through two stages of Low
Pass Filters to give a smoothed tone (single or dual), and
finally to the TONE output.
7.4Data inputs (PCD3311C)
Inputs D0, D1, D2, D3, D4 and D5 are used in the parallel
data input mode of the PCD3311C. Inputs D0 and D1 are
also used in serial input mode when they act as the SCL
and SDA inputs respectively. Inputs D0 and D1 have no
internal pull-down or pull-up resistors and must not be left
open in any application. Inputs D2, D3, D4 and D5 have
internal pull-down.
D4 and D5 are used to select between DTMF dual, DTMF
single, modem and musical tones (see Table 1). D0, D1,
D2 and D3 select the tone combination or single tone
within the selected application. They also, in combination
with D4, select the standby mode. See Tables 2, 3, 4
and 5.
PCD 3312C has no parallel data pins as data input is via
2
C-bus.
the I
Table 1 Use of D5 and D4 to select application
D5D4APPLICATION
LOW LOW DTMF single tones; musical tones;
standby
LOW HIGH DTMF dual tones (all 16 combinations)
HIGH LOW modem tones
HIGH HIGH musical tones
7.2Clock/oscillator connection
The timebase for the PCD3311C and PCD3312C is a
crystal-controlled oscillator, requiring a 3.58 MHz quartz
crystal to be connected between OSCI and OSCO.
Alternatively, the OSCI input can be driven from an
external clock of 3.58 MHz.
7.3Mode selection (PCD3311C)
The MODE input selects the data input mode for the
PCD3311C. When MODE is connected to V
(HIGH),
DD
data can be received in the parallel mode. When
connected to VSS (LOW) or left open, data can be received
via the serial I2C-bus.
PCD 3312C has no MODE input as data input is via the
I2C-bus only.
7.5Strobe input (PCD3311C )
The STROBE input (with internal pull-down) allows the
loading of parallel data into D0 to D5 when MODE is HIGH.
The data inputs must be stable preceding the
positive-going edge of the strobe pulse (active HIGH).
Input data are loaded at the negative-going edge of the
strobe pulse and then the corresponding tone (or standby
mode) is provided at the TONE output. The output remains
unchanged until the negative-going edge of the next
STROBE pulse (for new data) is received. Figure 5 is an
example of the timing relationship between STROBE and
the data inputs.
When MODE is LOW, data is received serially via the
Fig.5Timing of STROBE, parallel data inputs and TONE output (770 Hz + 1477 Hz in example) in the parallel
mode (MODE = HIGH).
7.6I2C-bus clock and data inputs
SCL and SDA are the serial clock and serial data inputs
according to the I2C-bus specification, see Chapter 8.
SCL and SDA must be pulled up externally to VDD.
For the PCD3311C, SCL and SDA are combined with
parallel inputs D0 and D1 respectively - D0/SCL and
D1/SDA operate serially only when MODE is LOW.
7.7Address input
Address input A0 defines the least significant bit of the
2
C-bus address of the device (see Fig.6). The first 6 bits
I
of the address are fixed internally. By tying the A0 of each
device to VDD (HIGH) and VSS(LOW) respectively, two
different PCD3311C or PCD3312C devices can be
individually addressed on the bus.
Whether one or two devices are used, A0 must be
connected to VDD or VSS.
1996 Nov 217
7.8I
2
C-bus data configuration (see Fig.6)
The PCD3311C and PCD3312C are always slave
receivers in the I2C-bus configuration. The R/W bit in is
thus always LOW, indicating that the master
(microcontroller) is writing.
The slave address in the serial mode consists of 7 bits: 6
bits internally fixed, 1 externally set via A0. in the serial
mode, the same input data codes are used as in the
parallel mode. See Tables 2, 3, 4 and 5.
7.9Tone output
The single and dual tones provided at the TONE output are
first filtered by an on-chip switched-capacitor filter,
followed by an active RC low-pass filter. The filtered tones
fulfil the CEPT recommendations for total harmonic
distortion of DTMF tones. An on-chip reference voltage
provides output tone levels independent of the supply
voltage. Tables 3, 4 and 5 give the frequency deviation of
the output tones with respect to the standard DTMF,
modem and music frequencies.
In order to avoid an undefined state when the power is switched ON, the devices have an internal reset circuit which sets
the standby mode (oscillator OFF).
7.11TABLES OF INPUT AND OUTPUT
The specified output tones are obtained when a 3.579545 MHz crystal is used.
In each table, the logical states for the input data lines are related to voltage levels as follows:
1 = HIGH = V
0 = LOW = V
DD
SS
X = don’t care
Table 2 Input data for no output tone, TONE in 3-state
D5D4D3D2D1D0HEX
(1)
X0000000 or 20ON
X0000101 or 21OFF
X0001002 or 22OFF
X0001103 or 23OFF
Note
1. The alternative HEX values depend on the value of D5.
The I2C-bus is for two-way communication between different ICs or modules. It uses only two lines, a serial data line
(SDA) and a serial clock line (SCL), both of which are bi-directional. Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus
is not busy.
8.1Bit transfer (see Fig.7)
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as control signals.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.7 Bit transfer.
8.2Start and stop conditions (see Fig.8)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
8.3System configuration (see Fig.9)
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
message transfer is the ‘master’ and the devices that are controlled by the master are the ‘slaves’.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
MBA605
Fig.9 System configuration.
8.4Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited.
Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the
transmitter whereas the master generates an extra acknowledge after the reception of each byte. Also a master must
generate an acknowledge after reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the acknowledge-related clock pulse. Set-up and hold times must
be taken into account to ensure that the SDA line is stable LOW during the whole HIGH period of the
acknowledge-related clock pulse. A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate the stop condition.
The PCD3311C and PCD3312C accept data input from a microcontroller and are ‘slave receivers’ when operating via
the I2C-bus. They support the ‘standard’ and ‘low-speed’ modes of the I2C-bus, but not the ‘fast’ mode detailed in
I2C-bus and how to use it”
document order no. 9398 393 40011. The timing requirements for the devices are described
in Sections 8.5.1 and 8.5.2.
“The
8.5.1S
TANDARD MODE
Masters generate a bus clock with a maximum frequency of 100 kHz. Detailed timing is shown in Fig.11, where the two
signal levels are LOW = VIL and HIGH = VIH, see Chapter 11. Figure 12 shows a complete data transfer in standard
mode. The time symbols are explained in Table 6.
Clock LOW minimum = 4.7 µs; clock HIGH minimum = 4 µs.
The dashed line is the acknowledgment of the receiver.
Mark-to-space ratio = 1 : 1 (LOW-to-HIGH).
Maximum number of bytes is unrestricted.
Premature termination of transfer is allowed by generation of STOP condition.
Acknowledge clock bit must be provided by master.
SDA
SCL
CONDITION
981 - 7981 - 7981 - 7
ACKADDRESS R/W
DATASTART
ACK
CONDITION
START
STOPACKADDRESS R/W
MBC765
Fig.12 Complete data transfer in standard mode.
Table 6 Explanation of time symbols used in Fig.11
SYMBOLPARAMETERREMARKSMIN.MAX.UNIT
f
t
t
SCL
SW
BUF
SCL clock frequency0100kHz
tolerable pulse spike width−100ns
bus free timeThe time that the bus is free (SDA is HIGH)
4.7−µs
before a new transmission is initiated by SDA
going LOW.
t
SU;STA
t
HD;STA
set-up time repeated STARTOnly valid for repeated start code.4.7−µs
hold time ST ART conditionThe time between SDA going LOW and the first
4.0−µs
valid negative-going transition of SCL.
t
LOW
t
HIGH
t
r
t
f
t
SU;DAT
t
HD;DAT
t
SU;STO
SCL LOW timeThe LOW period of the SCL clock.4.7−µs
SCL HIGH timeThe HIGH period of the SCL clock.4.0−µs
rise time SDA and SCL−1.0µs
fall time SDA and SCL−0.3µs
data set-up time250−ns
data hold time0−ns
set-up time STOP condition4.0−µs
8.5.2L
OW-SPEED MODE
Masters generate a bus clock with a maximum frequency of 2 kHz; a minimum LOW period of 105 µs and a minimum
HIGH period of 365 µs. The mark-to-space ratio is 1 : 3 LOW-to-HIGH. Detailed timing is shown in Fig.13, where the two
signal levels are LOW = VIL and HIGH = VIH, see Chapter 11. Figure 14 shows a complete data transfer in low-speed
mode.The time symbols are explained in Table 7.
Clock LOW minimum = 130 µs ±25 µs; clock HIGH minimum 390 µs ±25 µs.
Mark-to-space ratio = 1 : 3 (LOW-to-HIGH).
Start byte 0000 0001.
Maximum number of bytes = 6.
Premature termination of transfer not allowed.
Acknowledge clock bit must be provided by master.
Table 7 Explanation of time symbols used in Fig.13
SYMBOLPARAMETERREMARKSMIN.MAX.UNIT
f
SCL
t
SW
t
BUF
t
SU;STA
t
HD;STA
t
LOW
t
HIGH
t
r
t
f
t
SU;DAT
t
HD;DAT
t
SU;STO
SCL clock frequency02kHz
tolerable pulse spike width−100ns
bus free timeThe time that the bus is free (SDA is
105−µs
HIGH) before a new transmission is
initiated by SDA going LOW.
set-up time repeated STARTOnly valid for repeated start code.105155µs
hold time START conditionThe time between SDA going LOW and
365415µs
the first valid negative-going transition of
SCL.
SCL LOW timeThe LOW period of the SCL clock.105155µs
SCL HIGH timeThe HIGH period of the SCL clock.365−µs
rise time SDA and SCL−1.0µs
fall time SDA and SCL−0.3µs
data set-up time250−ns
data hold time0−ns
set-up time STOP condition105155µs
9HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take
normal precautions appropriate to handling MOS devices (see
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOLPARAMETERMIN.MAX.UNIT
V
V
I
I
P
P
I
I
T
T
DD
I
I
O
tot
O
DD
SS
stg
amb
supply voltage−0.8+8.0V
all input voltages−0.8VDD+ 0.8 V
DC input current−10+10mA
DC output current−10+10mA
total power dissipation−300mW
power dissipation per output−50mW
supply current through pin V
supply current through pin V
1. Oscillator ON; VDD= 3 V; crystal connected between OSCI and OSCO; D0/SCL and D1/SDA connected via
resistance of 5.6 kΩ to VDD; all other pins left open.
2. As note 1, but with oscillator OFF.
3. Related to the level of the LOW group frequency component, according to CEPT recommendations.
4. Related to the level of the fundamental frequency.
5. Oscillator must be running.
6. Values are referenced to the 10% and 90% levels of the relevant pulse amplitudes, with a total voltage swing from
VSSto VDD.
DTMF output voltage (RMS), HIGH group158192205mV
DTMF output voltage (RMS), LOW group125150160mV
DC voltage level−
1
⁄2V
DD
−V
voltage gain (pre-emphasis) of group1.852.102.35dB
=25°C
amb
dual tone (note 3)−−25−dB
modem tone (note 4)−−29−dB
maximum allowable amplitude at OSCI−−V
=3V)
DD
− VSSV
DD
oscillator start-up time−3−ms
TONE start-up time (note 5)−0.5−ms
STROBE pulse width (note 6)400−−ns
data set-up time (note 6)150−−ns
data hold time (note 6)100−−ns
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
(order code 9398 652 90011).
14.2DIP
14.2.1S
OLDERING BY DIPPING OR BY WA VE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
14.2.2R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
14.3SO
14.3.1REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
14.3.2W
AVE SOLDERING
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
14.3.3R
EPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
16 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
17 PURCHASE OF PHILIPS I
Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2
C COMPONENTS
2
C components conveys a license under the Philips’ I2C patent to use the
1996 Nov 2127
Page 28
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands417021/1200/02/pp28 Date of release: 1996 Nov 21Document order number: 9397 750 01155
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