Datasheet PCB80C552-5-16WP, S87C552-5BA Datasheet (Philips)

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80C552/83C552

Single-chip 8-bit microcontroller

Product specification 1996 Aug 06

INTEGRATED CIRCUITS

IC20 Data Handbook

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2

1996 Aug 06

DESCRIPTION

The 80C552/83C552 (hereafter generically
referred to as 8XC552) Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
8XC552 has the same instruction set as the
80C51. Three versions of the derivative exist:

• 83C552—8k bytes mask programmable

ROM

• 80C552—ROMless version of the 83C552

• 87C552—8k bytes EPROM (described in a

separate chapter)

The 8XC552 contains a non-volatile 8k × 8
read-only program memory (83C552), a
volatile 256 × 8 read/write data memory, five
8-bit I/O ports, one 8-bit input port, two 16-bit
timer/event counters (identical to the timers of
the 80C51), an additional 16-bit timer coupled
to capture and compare latches, a 15-source,
two-priority-level, nested interrupt structure,
an 8-input ADC, a dual DAC pulse width
modulated interface, two serial interfaces
(UART and I

2

C-bus), a “watchdog” timer and
on-chip oscillator and timing circuits. For
systems that require extra capability, the
8XC552 can be expanded using standard
TTL compatible memories and logic.

In addition, the 8XC552 has two software
selectable modes of power reduction—idle
mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM,
timers, serial ports, and interrupt system to
continue functioning. The power-down mode
saves the RAM contents but freezes the
oscillator, causing all other chip functions to
be inoperative.

The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte, and
17 three-byte. With a 16MHz (24MHz)
crystal, 58% of the instructions are executed
in 0.75µs (0.5µs) and 40% in 1.5µs (1µs).
Multiply and divide instructions require 3µs
(2µs).

FEA TURES

•

80C51 central processing unit

• 8k × 8 ROM expandable externally to 64k

bytes

• An additional 16-bit timer/counter coupled

to four capture registers and three compare
registers

• Two standard 16-bit timer/counters

• 256 × 8 RAM, expandable externally to 64k

bytes

• Capable of producing eight synchronized,

timed outputs

• A 10-bit ADC with eight multiplexed analog

inputs

• Two 8-bit resolution, pulse width

modulation outputs

• Five 8-bit I/O ports plus one 8-bit input port

shared with analog inputs

• I

2

C-bus serial I/O port with byte oriented

master and slave functions

• Full-duplex UART compatible with the

standard 80C51

• On-chip watchdog timer

• Three speed ranges:

– 1.2 to 16MHz
– 1.2 to 24MHz (ROM, ROMless only)
– 1.2 to 30MHz (ROM, ROMless only)

• Three operating ambient temperature

ranges:

– PCB83C552–5: 0°C to +70°C
– PCF83C552–5: –40°C to +85°C

(XTAL frequency max. 24 MHz)

– PCA83C552–5: –40°C to +125°C

(XTAL frequency max. 16 MHz)

PIN CONFIGURA TIONS

9161

60

44

4327

26

10

CERAMIC

AND

PLASTIC

LEADED CHIP

CARRIER

Pin Function Pin Function

1 P5.0/ADC0 35 XTAL1
2 V

DD

36 V

SS

3 STADC 37 V

SS

4 PWM0 38 NC*
5 PWM1 39 P2.0/A08
6 EW 40 P2.1/A09
7 P4.0/CMSR0 41 P2.2/A10
8 P4.1/CMSR1 42 P2.3/A11

9 P4.2/CMSR2 43 P2.4/A12
10 P4.3/CMSR3 44 P2.5/A13
11 P4.4/CMSR4 45 P2.6/A14
12 P4.5/CMSR5 46 P2.7/A15
13 P4.6/CMT0 47 PSEN
14 P4.7/CMT1 48 ALE
15 RST 49 EA
16 P1.0/CT0I 50 P0.7/AD7
17 P1.1/CT1I 51 P0.6/AD6
18 P1.2/CT2I 52 P0.5/AD5
19 P1.3/CT3I 53 P0.4/AD4
20 P1.4/T2 54 P0.3/AD3
21 P1.5/RT2 55 P0.2/AD2
22 P1.6/SCL 56 P0.1/AD1
23 P1.7/SDA 57 P0.0/AD0
24 P3.0/RxD 58 AVref–
25 P3.1/TxD 59 AVref+
26 P3.2/INT0 60 AV

SS

27 P3.3/INT1 61 AV

DD

28 P3.4/T0 62 P5.7/ADC7
29 P3.5/T1 63 P5.6/ADC6
30 P3.6/WR 64 P5.5/ADC5
31 P3.7/RD 65 P5.4/ADC4
32 NC* 66 P5.3/ADC3
33 NC* 67 P5.2/ADC2
34 XTAL2 68 P5.1/ADC1

*DO NOT CONNECT

80 65

64

41

4025

24

1

PLASTIC

QUAD FLAT

PACK

PORT 5

PORT 4

ADC0-7

CMT0
CMT1

CMSR0-5

RST

EW

XTAL1
XTAL2

EA

ALE

PSEN

AVref+
AVref–

STADC

PWM0
PWM1

PORT 0

LOW ORDER

ADDRESS AND

DATA BUS

PORT 1PORT 2PORT 3

CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA

RxD/DATA
TxD/CLOCK

INT0
INT1
T0
T1
WR
RD

V

SS

V

DD

AV

SS

AV

DD

HIGH ORDER

ADDRESS AND

DATA BUS

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

3

PLASTIC QUAD FLAT PACK
PIN FUNCTIONS

80 65

64

41

4025

24

1

PQFP

Pin Function Pin Function

1 P4.1/CMSR1 41 P2.3/A11
2 P4.2/CMSR2 42 P2.4/A12
3 NC* 43 NC*
4 P4.3/CMSR3 44 NC*
5 P4.4/CMSR4 45 P2.5/A13
6 P4.5/CMSR5 46 P2.6/A14
7 P4.6/CMT0 47 P2.7/A15
8 P4.7/CMT1 48 PSEN

9 RST 49 ALE
10 P1.0/CT0I 50 EA
11 P1.1/CT1I 51 P0.7/AD7
12 P1.2/CT2I 52 P0.6/AD6
13 P1.3/CT3I 53 P0.5/AD5
14 P1.4/T2 54 P0.4/AD4
15 P1.5/RT2 55 P0.3/AD3
16 P1.6/SCL 56 P0.2/AD2
17 P1.7/SDA 57 P0.1/AD1
18 P3.0/RxD 58 P0.0/AD0
19 P3.1/TxD 59 AVref–
20 P3.2/INT0 60 AVref+
21 NC* 61 AV

SS

22 NC* 62 NC*
23 P3.3/INT1 63

AV

DD

24 P3.4/T0 64 P5.7/ADC7
25 P3.5/T1 65 P5.6/ADC6
26 P3.6/WR 66 P5.5/ADC5
27 P3.7/RD 67 P5.4/ADC4
28 NC* 68 P5.3/ADC3
29 NC* 69 P5.2/ADC2
30 NC* 70 P5.1/ADC1
31 XTAL2 71 P5.0/ADC0
32 XTAL1 72 V

DD

33 IC 73 IC
34 V

SS

74 STADC

35 V

SS

75 PWM0

36 V

SS

76 PWM1
37 NC* 77 EW
38 P2.0/A08 78 NC*
39 P2.1/A09 79 NC*
40 P2.2/A10 80 P4.0/CMSR0

* DO NOT CONNECT
IC = internally connected (do not use)

LOGIC SYMBOL

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

4

ORDERING INFORMATION

PHILIPS

PART ORDER NUMBER

PART MARKING

NORTH AMERICA PHILIPS

PART ORDER NUMBER

DRAWING

TEMPERATURE °C

FREQ

ROMless ROM ROMless ROM NUMBER AND PACKAGE MHz

PCB80C552-5-16WP PCB83C552-5WP/xxx S80C552-4A68 S83C552-4A68 SOT188-3

0 to +70, Plastic Leaded Chip

Carrier

16

PCB80C552-5-16H PCB83C552-5H/xxx S80C552-4B S83C552-4B SOT318-2 0 to +70, Plastic Quad Flat Pack 16
PCF80C552-5-16WP PCF83C552-5WP/xxx S80C552-5A68 S83C552-5A68 SOT188-3

–40 to +85, Plastic Leaded Chip

Carrier

16

PCF80C552-5-16H PCF83C552-5H/xxx S80C552-5B S83C552-5B SOT318-2

–40 to +85, Plastic Quad Flat

Pack

16

PCA80C552-5-16WP PCA83C552-5WP/xxx S80C552-6A68 S83C552-6A68 SOT188-3

–40 to +125, Plastic Leaded Chip

Carrier

16

PCA80C552-5-16H PCA83C552-5H/xxx S80C552-6B S83C552-6B SOT318-2

–40 to +125, Plastic Quad Flat

Pack

16

PCB80C552-5-24WP PCB83C552-5WP/xxx S80C552-AA68 S83C552-AA68 SOT188-3

0 to +70, Plastic Leaded Chip

Carrier

24

PCB80C552-5-24H PCB83C552-5H/xxx S80C552-AB S83C552-AB SOT318-2 0 to +70, Plastic Quad Flat Pack 24
PCF80C552-5-24WP PCF83C552-5WP/xxx S80C552-BA68 S83C552-BA68 SOT188-3

–40 to +85, Plastic Leaded Chip

Carrier

24

PCF80C552-5-24H PCF83C552-5H/xxx S80C552-BB S83C552-BB SOT318-2

–40 to +85, Plastic Quad Flat

Pack

24

PCB80C552-5-30WP PCB83C552-5WP/xxx S80C552-CA68 S83C552-CA68 SOT188-3

0 to +70, Plastic Leaded Chip

Carrier

30

PCB80C552-5-30H PCB83C552-5H/xxx S80C552-CB S83C552-CB SOT318-2 0 to +70, Plastic Quad Flat Pack 30

NOTE:

1. xxx denotes the ROM code number.

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

5

DRAWING

TEMPERATURE °C

FREQ

EPROM NUMBER AND PACKAGE MHz

S87C552-4A68 SOT188-3

0 to +70, Plastic Leaded Chip

Carrier

16

S87C552-4K68 1473A

0 to +70, Ceramic Leaded Chip

Carrier w/Window

16
S87C552-4BA SOT318-2 0 to +70, Plastic Quad Flat Pack 16
S87C552-5A68 SOT188-3

–40 to +85, Plastic Leaded Chip

Carrier

16

S87C552-5K68 1473A

–40 to +85, Ceramic Leaded

Chip Carrier w/Window

16

S87C552-5BA SOT318-2

–40 to +85, Plastic Quad Flat

Pack

16

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

6

BLOCK DIAGRAM

CPU

ADC

8-BIT INTERNAL BUS

16

P0 P1 P2 P3 TxD RxD P5 P4 CT0I-CT3I T2 RT2 CMSR0-CMSR5

CMT0, CMT1

RST EW

XTAL1

XTAL2

EA

ALE

PSEN

WR

RD

T0 T1 INT0 INT1

V

DD

V

SS

PWM0 PWM1

AV

SS

AV

DD

AV

REF

–+

STADC

ADC0-7 SDA SCL

3 3 3 3

3 3

0

2

1 1 1 4

115

0
1
2

ALTERNATE FUNCTION OF PORT 0

3
4
5

AD0-7

A8-15

3

3

16

T0, T1

TWO 16-BIT

TIMER/EVENT

COUNTERS

PROGRAM

MEMORY

8k x 8 ROM

DATA

MEMORY

256 x 8 RAM

DUAL
PWM

SERIAL

I

2

C PORT

80C51 CORE

EXCLUDING

ROM/RAM

PARALLEL I/O

PORTS AND

EXTERNAL BUS

SERIAL

UART
PORT

8-BIT

PORT

FOUR
16-BIT

CAPTURE

LATCHES

T2

16-BIT
TIMER/
EVENT

COUNTERS

T2

16-BIT

COMPARA-

TORS

wITH

REGISTERS

COMPARA-

TOR

OUTPUT

SELECTION

T3

WATCHDOG

TIMER

ALTERNATE FUNCTION OF PORT 1
ALTERNATE FUNCTION OF PORT 2

ALTERNATE FUNCTION OF PORT 3
ALTERNATE FUNCTION OF PORT 4
ALTERNATE FUNCTION OF PORT 5

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

7

PIN DESCRIPTION

PIN NO.

MNEMONIC PLCC QFP TYPE NAME AND FUNCTION

V

DD

2 72 I Digital Power Supply: +5V power supply pin during normal operation, idle and

power-down mode.

STADC 3 74 I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also

be started by software). This pin must not float.
PWM0 4 75 O Pulse Width Modulation: Output 0.
PWM1 5 76 O Pulse Width Modulation: Output 1.
EW 6 77 I Enable W atchdog T imer: Enable for T3 watchdog timer and disable power-down mode.

This pin must not float.
P0.0-P0.7 57-50 58-51 I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written

to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external program and data memory. In

this application it uses strong internal pull-ups when emitting 1s.
P1.0-P1.7 16-23 10-17 I/O Port 1: 8-bit I/O port. Alternate functions include:

16-21 10-15 I/O (P1.0-P1.5): Quasi-bidirectional port pins.
22-23 16-17 I/O (P1.6, P1.7): Open drain port pins.
16-19 10-13 I CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.

20 14 I T2 (P1.4): T2 event input.
21 15 I RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
22 16 I/O SCL (P1.6): Serial port clock line I2C-bus.
23 17 I/O SDA (P1.7): Serial port data line I2C-bus.

Port 1 is also used to input the lower order address byte during EPROM programming and

verification. A0 is on P1.0, etc.
P2.0-P2.7 39-46 38-42,

45-47

I/O Port 2: 8-bit quasi-bidirectional I/O port.

Alternate function: High-order address byte for external memory (A08-A15).
P3.0-P3.7 24-31 18-20,

23-27

I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:

24 18 RxD(P3.0): Serial input port.
25 19 TxD (P3.1): Serial output port.
26 20 INT0 (P3.2): External interrupt.
27 23 INT1 (P3.3): External interrupt.
28 24 T0 (P3.4): Timer 0 external input.
29 25 T1 (P3.5): Timer 1 external input.
30 26 WR (P3.6): External data memory write strobe.
31 27 RD (P3.7): External data memory read strobe.

P4.0-P4.7 7-14 80, 1-2

4-8

I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:

7-12 80, 1-2

4-6

O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with

timer T2.

13, 14 7, 8 O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.

P5.0-P5.7 68-62, 71-64, I Port 5: 8-bit input port.

1 ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.

RST 15 9 I/O Reset: Input to reset the 8XC552. It also provides a reset pulse as output when timer T3

overflows.
XTAL1 35 32 I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the

internal clock generator. Receives the external clock signal when an external oscillator is

used.
XTAL2 34 31 O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit

when an external clock is used.

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

8

PIN DESCRIPTION (Continued)

PIN NO.

MNEMONIC PLCC QFP TYPE NAME AND FUNCTION

V

SS

36, 37 34-36 I Two Digital ground pins.
PSEN 47 48 O Program Store Enable: Active-low read strobe to external program memory.
ALE 48 49 O Address Latch Enable: Latches the low byte of the address during accesses to external

memory. It is activated every six oscillator periods. During an external data memory
access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles
CMOS inputs without an external pull-up.

EA 49 50 I External Access: When EA is held at TTL level high, the CPU executes out of the internal

program ROM provided the program counter is less than 8192. When EA

is held at TTL

low level, the CPU executes out of external program memory. EA

is not allowed to float.

AV

REF–

58 59 I Analog to Digital Conversion Reference Resistor: Low-end.

AV

REF+

59 60 I Analog to Digital Conversion Reference Resistor: High-end.

AV

SS

60 61 I Analog Ground

AV

DD

61 63 I Analog Power Supply

NOTE:

1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V

DD

+ 0.5V or VSS – 0.5V ,

respectively.

OSCILLATOR
CHARACTERISTICS

XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol,
page 3.

To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.

RESET

A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
power-on, the voltage on V

DD

and RST must
come up at the same time for a proper
start-up.

IDLE MODE

In the idle mode, the CPU puts itself to sleep
while some of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers

remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.

POWER-DOWN MODE

In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 1
shows the state of the I/O ports during low
current operating modes.

Table 1. External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM

MEMORY

ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4

PWM0/

PWM1

Idle Internal 1 1 Data Data Data Data Data 1
Idle External 1 1 Float Data Address Data Data 1
Power-down Internal 0 0 Data Data Data Data Data 1
Power-down External 0 0 Float Data Data Data Data 1

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

9

Serial Control Register (S1CON) – See Table 2

CR2 ENS1 STA STO SI AA CR1 CR0

S1CON (D8H)

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

Table 2. Serial Clock Rates

BIT FREQUENCY (kHz) AT f

OSC

CR2 CR1 CR0 6MHz 12MHz 16MHz 24MHz

2

30MHz

2

f

OSC

DIVIDED BY

0 0 0 23 47 62.5 94 117 1 256
0 0 1 27 54 71 107

1

134

1

224

0 1 0 31 63 83.3 125

1

156

1

192

0 1 1 37 75 100 150

1

188

1

160
1 0 0 6.25 12.5 17 25 31 960
1 0 1 50 100 133

1

200

1

250

1

120
1 1 0 100 200 267

1

400

1

500

1

60

1 1 1 0.24 < 62.5 0.49 < 62.5 0.65 < 55.6 0.98 < 50.0 1.22 < 52.1 96 × (256 – (reload value Timer 1))

0 < 255 0 < 254 0 < 253 0 <251 0 < 250 reload value Timer 1 in Mode 2.

NOTES:

1. These frequencies exceed the upper limit of 100kHz of the I

2

C-bus specification and cannot be used in an I2C-bus application.

2. At f

OSC

= 24MHz/ 30MHz the maximum I2C bus rate of 100kHz cannot be realized due to the fixed divider rates.

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER RATING UNIT

Storage temperature range –65 to +150 °C
Voltage on any other pin to V

SS

–0.5 to +6.5 V
Input, output DC current on any single I/O pin 5.0 mA
Power dissipation

(based on package heat transfer limitations, not device power consumption)

1.0 W

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

SS

unless otherwise

noted.

DEVICE SPECIFICATIONS

SUPPLY VOLTAGE (V) FREQUENCY (MHz)

TYPE MIN MAX MIN MAX TEMPERATURE RANGE (°C)

PCB83(0)C552-5-16 4.0 6.0 1.2 16 0 to +70
PCF83(0)C552-5-16 4.0 6.0 1.2 16 –40 to +85
PCA83(0)C552-5-16 4.5 5.5 1.2 16 –40 to +125
PCB83(0)C552-5-24 4.5 5.5 1.2 24 0 to +70
PCF83(0)C552-5-24 4.5 5.5 1.2 24 –40 to +85
PCB83(0)C552-5-30 4.5 5.5 1.2 30 0 to +70

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

10

DC ELECTRICAL CHARACTERISTICS

VSS, AVSS = 0V

TEST LIMITS

SYMBOL PARAMETER CONDITIONS MIN MAX UNIT

I

DD

Supply current operating: See notes 1 and 2

PCB8XC552-5-16 f

OSC

= 16MHz 45 mA

PCF8XC552-5-16 f

OSC

= 16MHz 45 mA

PCA8XC552-5-16 f

OSC

= 16MHz 40 mA

PCB8XC552-5-24 f

OSC

= 24MHz 55 mA

PCF8XC552-5-24 f

OSC

= 24MHz 55 mA

PCB8XC552-5-30 f

OSC

= 30MHz 68 mA

I

ID

Idle mode: See notes 1 and 3

PCB8XC552-5-16 f

OSC

= 16MHz 10 mA

PCF8XC552-5-16 f

OSC

= 16MHz 10 mA

PCA8XC552-5-16 f

OSC

= 16MHz 9 mA

PCB8XC552-5-24 f

OSC

= 24MHz 12.5 mA

PCF8XC552-5-24 f

OSC

= 24MHz 12.5 mA

PCB8XC552-5-30 f

OSC

= 30MHz 15 mA

I

PD

Power-down current: See notes 1 and 4;

2V < V

PD

< VDD max
PCB8XC552 50 µA
PCF8XC552 50 µA
PCA8XC552 150 µA

Inputs

V

IL

Input low voltage, except EA, P1.6, P1.7 –0.5 0.2VDD–0.1 V

V

IL1

Input low voltage to EA –0.5 0.2VDD–0.3 V

V

IL2

Input low voltage to P1.6/SCL, P1.7/SDA

5

–0.5 0.3V

DD

V

V

IH

Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA 0.2VDD+0.9 VDD+0.5 V

V

IH1

Input high voltage, XTAL1, RST 0.7V

DD

VDD+0.5 V

V

IH2

Input high voltage, P1.6/SCL, P1.7/SDA

5

0.7V

DD

6.0 V

I

IL

Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7 VIN = 0.45V –50 µA

I

TL

Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7 See note 6 –650 µA

±I

IL1

Input leakage current, port 0, EA, STADC, EW 0.45V < V

I

< V

DD

10 µA

±I

IL2

Input leakage current, P1.6/SCL, P1.7/SDA

0V < V

I

< 6V

0V < V

DD

< 5.5V

10 µA

±I

IL3

Input leakage current, port 5 0.45V < V

I

< V

DD

1 µA

Outputs

V

OL

Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7 IOL = 1.6mA

7

0.45 V

V

OL1

Output low voltage, port 0, ALE, PSEN, PWM0, PWM1 IOL = 3.2mA

7

0.45 V

V

OL2

Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA

7

0.4 V

V

OH

Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA VDD = 5V +10%

–IOH = 60µA 2.4 V
–IOH = 25µA 0.75V

DD

V

–IOH = 10µA 0.9V

DD

V

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

11

DC ELECTRICAL CHARACTERISTICS (Continued)

TEST LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
Outputs (Continued)

V

OH1

Output high voltage (port 0 in external bus mode, ALE,
PSEN

, PWM0, PWM1)

8

VDD = 5V +10%

–I

OH

= 400µA

2.4 V

–IOH = 150µA 0.75V

DD

V

–IOH = 40µA 0.9V

DD

V

V

OH2

Output high voltage (RST) –IOH = 400µA 2.4 V

–IOH = 120µA 0.8V

DD

V

R

RST

Internal reset pull-down resistor 50 150 kΩ

C

IO

Pin capacitance Test freq = 1MHz,

T

amb

= 25°C

10 pF

Analog Inputs

AV

DD

Analog supply voltage:

PCB8XC552-5-16 AVDD = VDD±0.2V 4.0 6.0 V
PCF8XC552-5-16 AVDD = VDD±0.2V 4.0 6.0 V
PCA8XC552-5-16 AVDD = VDD±0.2V 4.5 5.5 V
PCB8XC552-5-24 AVDD = VDD±0.2V 4.5 5.5 V
PCF8XC552-5-24 AVDD = VDD±0.2V 4.5 5.5 V
PCB8XC552-5-30 AVDD = VDD±0.2V 4.5 5.5 V

AI

DD

Analog supply current: operating: (16MHz) Port 5 = 0 to AV

DD

1.2 mA

Analog supply current: operating: (24MHz, 30MHz) Port 5 = 0 to AV

DD

1.0 mA

AI

ID

Idle mode:

PCB8XC552-5-16 50 µA
PCF8XC552-5-16 50 µA
PCA8XC552-5-16 100 µA
PCB8XC552-5-24 50 µA
PCF8XC552-5-24 50 µA
PCB8XC552-5-30 50 µA

AI

PD

Power-down mode: 2V < AVPD < AVDD max

PCB8XC552 50 µA
PCF8XC552 50 µA
PCA8XC552 100 µA

AV

IN

Analog input voltage AVSS–0.2 AVDD+0.2 V

AV

REF

Reference voltage:

AV

REF–

AVSS–0.2 V

AV

REF+

AVDD+0.2 V

R

REF

Resistance between AV

REF+

and AV

REF–

10 50 kΩ

C

IA

Analog input capacitance 15 pF

t

ADS

Sampling time 8t

CY

µs

t

ADC

Conversion time (including sampling time) 50t

CY

µs

DL

e

Differential non-linearity

10, 11, 12

±1 LSB

IL

e

Integral non-linearity

10, 13

±2 LSB

OS

e

Offset error

10, 14

±2 LSB

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

12

DC ELECTRICAL CHARACTERISTICS (Continued)

TEST LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
Analog Inputs (continued)

G

e

Gain error

10, 15

±0.4 %

A

e

Absolute voltage error

10, 16

±3 LSB

M

CTC

Channel to channel matching ±1 LSB

C

t

Crosstalk between inputs of port 5

17

0–100kHz –60 dB

NOTES FOR DC ELECTRICAL CHARACTERISTICS:

1. See Figures 10 through 15 for I

DD

test conditions.

2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t

r

= tf = 10ns; VIL = VSS + 0.5V;

V

IH

= VDD – 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS.

3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

r

= tf = 10ns; VIL = VSS + 0.5V;

V

IH

= VDD – 0.5V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS.

4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW

= VDD;

EA

= RST = STADC = XTAL1 = VSS.

5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I

2

C specification, so an input voltage below 1.5V will be recognized as a logic

0 while an input voltage above 3.0V will be recognized as a logic 1.

6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V

IN

is approximately 2V .

7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

OL

s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V . In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I

OL

can exceed these conditions provided that no

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

8. Capacitive loading on ports 0 and 2 may cause the V

OH

on ALE and PSEN to momentarily fall below the 0.9VDD specification when the

address bits are stabilizing.

9. The following condition must not be exceeded: V

DD

– 0.2V < AVDD < VDD + 0.2V .

10.Conditions: AV

REF–

= 0V; AVDD = 5.0V , AV

REF+

(80C552, 83C552) = 5.12V . ADC is monotonic with no missing codes. Measurement by

continuous conversion of AV

IN

= –20mV to 5.12V in steps of 0.5mV .

11.The differential non-linearity (DL

e

) is the difference between the actual step width and the ideal step width. (See Figure 1.)

12.The ADC is monotonic; there are no missing codes.

13.The integral non-linearity (IL

e

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset error. (See Figure 1.)

14.The offset error (OS

e

) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and

a straight line which fits the ideal transfer curve. (See Figure 1.)

15.The gain error (G

e

) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),

and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)

16.The absolute voltage error (A

e

) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve.

17.This should be considered when both analog and digital signals are simultaneously input to port 5.

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

13

Figure 1. ADC Conversion Characteristic

1

0

2

3

4

5

6

7

1018

1019

1020

1021

1022

1023

1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024

Code

Out

(2)

(1)

(5)

(4)

(3)

1 LSB
(ideal)

Offset

error
OS

e

Offset

error
OS

e

Gain
error

G

e

AVIN (LSB

ideal

)

1 LSB =

AV

REF+

– AV

REF–

1024

(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DL

e

).

(4) Integral non-linearity (IL

e

).

(5) Center of a step of the actual transfer curve.

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

14

AC ELECTRICAL CHARACTERISTICS

1, 2

16 MHz version

16MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT

1/t

CLCL

2 Oscillator frequency 1.2 16 MHz

t

LHLL

2 ALE pulse width 85 2t

CLCL

–40 ns

t

AVLL

2 Address valid to ALE low 8 t

CLCL

–55 ns

t

LLAX

2 Address hold after ALE low 28 t

CLCL

–35 ns

t

LLIV

2 ALE low to valid instruction in 150 4t

CLCL

–100 ns

t

LLPL

2 ALE low to PSEN low 23 t

CLCL

–40 ns

t

PLPH

2 PSEN pulse width 143 3t

CLCL

–45 ns

t

PLIV

2 PSEN low to valid instruction in 83 3t

CLCL

–105 ns

t

PXIX

2 Input instruction hold after PSEN 0 0 ns

t

PXIZ

2 Input instruction float after PSEN 38 t

CLCL

–25 ns

t

AVIV

2 Address to valid instruction in 208 5t

CLCL

–105 ns

t

PLAZ

2 PSEN low to address float 10 10 ns

Data Memory

t

RLRH

3 RD pulse width 275 6t

CLCL

–100 ns

t

WLWH

4 WR pulse width 275 6t

CLCL

–100 ns

t

RLDV

3 RD low to valid data in 148 5t

CLCL

–165 ns

t

RHDX

3 Data hold after RD 0 0 ns

t

RHDZ

3 Data float after RD 55 2t

CLCL

–70 ns

t

LLDV

3 ALE low to valid data in 350 8t

CLCL

–150 ns

t

AVDV

3 Address to valid data in 398 9t

CLCL

–165 ns

t

LLWL

3, 4 ALE low to RD or WR low 138 238 3t

CLCL

–50 3t

CLCL

+50 ns

t

AVWL

3, 4 Address valid to WR low or RD low 120 4t

CLCL

–130 ns

t

QVWX

4 Data valid to WR transition 3 t

CLCL

–60 ns

t

DW

4 Data before WR 288 7t

CLCL

–150 ns

t

WHQX

4 Data hold after WR 13 t

CLCL

–50 ns

t

RLAZ

3 RD low to address float 0 0 ns

t

WHLH

3, 4 RD or WR high to ALE high 23 103 t

CLCL

–40 t

CLCL

+40 ns

External Clock

t

CHCX

5 High time

4

20 20 ns

t

CLCX

5 Low time

4

20 20 ns

t

CLCH

5 Rise time

4

20 20 ns

t

CHCL

5 Fall time

4

20 20 ns

Serial Timing – Shift Register Mode4 (Test Conditions: T

amb

= 0°C to +70°C; VSS = 0V; Load Capacitance = 80pF)

t

XLXL

6 Serial port clock cycle time 0.75 12t

CLCL

µs

t

QVXH

6 Output data setup to clock rising edge 492 10t

CLCL

–133 ns

t

XHQX

6 Output data hold after clock rising edge 8 2t

CLCL

–117 ns

t

XHDX

6 Input data hold after clock rising edge 0 0 ns

t

XHDV

6 Clock rising edge to input data valid 492 10t

CLCL

–133 ns

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100pF, load capacitance for all other outputs = 80pF .

3. t

CLCL

= 1/f

OSC

= one oscillator clock period.

t

CLCL

= 83.3ns at f

OSC

= 12MHz.

t

CLCL

= 62.5ns at f

OSC

= 16MHz.

4. These values are characterized but not 100% production tested.

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

15

AC ELECTRICAL CHARACTERISTICS (Continued)

1, 2

24/30 MHz version

24MHz CLOCK 30MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT

1/t

CLCL

2 Oscillator frequency 1.2 24 MHz

t

LHLL

2 ALE pulse width 43 27 2t

CLCL

–40 ns

t

AVLL

2 Address valid to ALE low 17 8 t

CLCL

–25 ns

t

LLAX

2 Address hold after ALE low 17 8 t

CLCL

–25 ns

t

LLIV

2 ALE low to valid instruction in 102 68 4t

CLCL

–65 ns

t

LLPL

2 ALE low to PSEN low 17 8 t

CLCL

–25 ns

t

PLPH

2 PSEN pulse width 80 55 3t

CLCL

–45 ns

t

PLIV

2 PSEN low to valid instruction in 65 40 3t

CLCL

–60 ns

t

PXIX

2 Input instruction hold after PSEN 0 0 0 ns

t

PXIZ

2 Input instruction float after PSEN 17 8 t

CLCL

–25 ns

t

AVIV

2 Address to valid instruction in 128 87 5t

CLCL

–80 ns

t

PLAZ

2 PSEN low to address float 10 10 10 ns

Data Memory

t

RLRH

3 RD pulse width 150 100 6t

CLCL

–100 ns

t

WLWH

4 WR pulse width 150 100 6t

CLCL

–100 ns

t

RLDV

3 RD low to valid data in 118 77 5t

CLCL

–90 ns

t

RHDX

3 Data hold after RD 0 0 0 ns

t

RHDZ

3 Data float after RD 55 39 2t

CLCL

–28 ns

t

LLDV

3 ALE low to valid data in 183 117 8t

CLCL

–150 ns

t

AVDV

3 Address to valid data in 210 135 9t

CLCL

–165 ns

t

LLWL

3, 4 ALE low to RD or WR low 75 175 50 150 3t

CLCL

–50 3t

CLCL

+50 ns

t

AVWL

3, 4 Address valid to WR low or RD low 92 58 4t

CLCL

–75 ns

t

QVWX

4 Data valid to WR transition 12 3 t

CLCL

–30 ns

t

DW

4 Data before WR 162 103 7t

CLCL

–130 ns

t

WHQX

4 Data hold after WR 17 8 t

CLCL

–25 ns

t

RLAZ

3 RD low to address float 0 0 0 ns

t

WHLH

3, 4 RD or WR high to ALE high 17 67 8 58 t

CLCL

–25 t

CLCL

+25 ns

External Clock

t

CHCX

5 High time

3

17 15 17 ns

t

CLCX

5 Low time

3

17 15 17 ns

t

CLCH

5 Rise time

3

5 3 20 ns

t

CHCL

5 Fall time

3

5 3 20 ns

Serial Timing – Shift Register Mode3 (Test Conditions: T

amb

= 0°C to +70°C; VSS = 0V; Load Capacitance = 80pF)

t

XLXL

6 Serial port clock cycle time 0.5 0.4 12t

CLCL

µs

t

QVXH

6 Output data setup to clock rising edge 283 200 10t

CLCL

–133 ns

t

XHQX

6 Output data hold after clock rising edge 23 6.6 2t

CLCL

–60 ns

t

XHDX

6 Input data hold after clock rising edge 0 0 0 ns

t

XHDV

6 Clock rising edge to input data valid 283 200 10t

CLCL

–133 ns

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100pF, load capacitance for all other outputs = 80pF .

3. These values are characterized but not 100% production tested.

4. t

CLCL

= 1/f

OSC

= one oscillator clock period.

t

CLCL

= 41.7ns at f

OSC

= 24MHz.

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

16

AC ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER INPUT OUTPUT

I2C Interface (Refer to Figure 9)

t

HD;STA

STAR T condition hold time ≥ 14 t

CLCL

> 4.0µs

1

t

LOW

SCL low time ≥ 16 t

CLCL

> 4.7µs

1

t

HIGH

SCL high time ≥ 14 t

CLCL

> 4.0µs

1

t

RC

SCL rise time ≤ 1µs –

2

t

FC

SCL fall time ≤ 0.3µs < 0.3µs

3

t

SU;DAT1

Data set-up time ≥ 250ns > 20 t

CLCL

– t

RD

t

SU;DAT2

SDA set-up time (before rep. STAR T cond.) ≥ 250ns > 1µs

1

t

SU;DAT3

SDA set-up time (before STOP cond.) ≥ 250ns > 8 t

CLCL

t

HD;DAT

Data hold time ≥ 0ns > 8 t

CLCL

– t

FC

t

SU;STA

Repeated START set-up time ≥ 14 t

CLCL

> 4.7µs

1

t

SU;STO

STOP condition set-up time ≥ 14 t

CLCL

> 4.0µs

1

t

BUF

Bus free time ≥ 14 t

CLCL

> 4.7µs

1

t

RD

SDA rise time ≤ 1µs –

2

t

FD

SDA fall time ≤ 0.3µs < 0.3µs

3

NOTES:

1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs.

3. Spikes on the SDA and SCL lines with a duration of less than 3 t

CLCL

will be filtered out. Maximum capacitance on bus-lines SDA and

SCL = 400pF.

4. t

CLCL

= 1/f

OSC

= one oscillator clock period at pin XTAL1. For 62ns, 42ns, 33.3ns < t

CLCL

< 285ns (16MHz, 24MHz, 30MHz > f

OSC

>

1.2MHz) the SI01 interface meets the I

2

C-bus specification for bit-rates up to 100 kbit/s.

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

17

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The
first character is always ‘t’ (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN

Q – Output data
R–RD

signal
t – Time
V – Valid
W– WR

signal
X – No longer a valid logic level
Z – Float
Examples: t

AVLL

= Time for address valid to

ALE low.

t

LLPL

= Time for ALE low to

PSEN

low.

t

PXIZ

Figure 2. External Program Memory Read Cycle

ALE

PSEN

PORT 0

PORT 2

A8–A15 A8–A15

A0–A7 A0–A7

t

AVLL

t

PXIX

t

LLAX

INSTR IN

t

PLIV

t

LHLL

t

PLPH

t

LLIV

t

PLAZ

t

LLPL

t

AVIV

ALE

PSEN

PORT 0

PORT 2

Figure 3. External Data Memory Read Cycle

RD

A0–A7

FROM RI OR DPL

DATA IN A0–A7 FROM PCL INSTR IN

P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH

t

WHLH

t

LLDV

t

LLWL

t

RLRH

t

LLAX

t

RLAZ

t

AVLL

t

RHDX

t

RHDZ

t

AVWL

t

AVDV

t

RLDV

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

18

t

LLAX

ALE

PSEN

PORT 0

PORT 2

Figure 4. External Data Memory Write Cycle

WR

A0–A7

FROM RI OR DPL

DATA OUT A0–A7 FROM PCL INSTR IN

P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH

t

WHLH

t

LLWL

t

WLWH

t

AVLL

t

AVWL

t

QVWX

t

WHQX

t

DW

0.8V

t

LOW

t

HIGH

Figure 5. External Clock Drive XTAL1

V

IH1

V

IH1

0.8V

t

CLCL

t

r

t

f

V

IH1

V

IH1

0.8V 0.8V

Figure 6. Shift Register Mode Timing

012345678

INSTRUCTION

ALE

CLOCK

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI

VALID VALID VALID VALID VALID VALID VALID VALID

SET TI

SET RI

t

XLXL

t

QVXH

t

XHQX

t

XHDX

t

XHDV

01234567

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

19

VDD–0.5

0.45V

0.2V

DD

+0.9

0.2V

DD

–0.1

NOTE:
AC INPUTS DURING TESTING ARE DRIVEN AT V

DD

–0.5 FOR A LOGIC ‘1’ AND

0.45V FOR A LOGIC ‘0’. TIMING MEASUREMENTS ARE MADE AT V

IH

MIN FOR A

LOGIC ‘1’ AND V

IL

MAX FOR A LOGIC ‘0’.

Figure 7. AC Testing Input/Output

V

LOAD

V

LOAD

+0.1V

V

LOAD

–0.1V

V

OH

–0.1V

V

OL

+0.1V

NOTE:
FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV
CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A
100mV CHANGE FROM THE LOADED V

OH/VOL

LEVEL OCCURS. IOH/IOL > +

20mA.

Figure 8. Float Waveform

TIMING

REFERENCE

POINTS

Figure 9. Timing SIO1 (I2C) Interface

t

RD

t

SU;STA

t

BUF

t

SU; STO

0.7 V

CC

0.3 V

CC

0.7 V

CC

0.3 V

CC

t

FDtRC

t

FC

t

HIGH

t

LOW

t

HD;STA

t

SU;DAT1

t

HD;DAT

t

SU;DAT2

t

SU;DAT3

START condition

repeated START condition

SDA

(INPUT/OUTPUT)

SCL

(INPUT/OUTPUT)

STOP condition

START or repeated START condition

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

20

40

30

20

10

124168

f (MHz)

(1)

Figure 10. 16MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (f

OSC

)

NOTE:
These values are valid only within the frequency specifications of the device under test.

I

DD

, I

D

mA

50

0

0

(2)

(3)

(4)

(1) Maximum operating mode; V

DD

= 6V

(2) Maximum operating mode; V

DD

= 4V

(3) Maximum idle mode; V

DD

= 6V

(4) Maximum idle mode; V

DD

= 4V

40

30

20

10

124168

f (MHz)

(1)

Figure 11. 24MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (f

OSC

)

NOTE:
These values are valid only within the frequency specifications of the device under test.

50

0

0

(2)

(3)
(4)

(1) Maximum operating mode; V

DD

= 5.5V

(2) Maximum operating mode; V

DD

= 4.5V

(3) Maximum idle mode; V

DD

= 5.5V

(4) Maximum idle mode; V

DD

= 4.5V

60

20 24

I

DD

, I

D

mA

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

21

V

DD

P0

EA

RST

XTAL1

XTAL2

V

SS

V

DD

V

DD

V

DD

I

DD

(NC)

CLOCK SIGNAL

Figure 12. IDD Test Condition, Active Mode

All other pins are disconnected

1

V

DD

P0

EA

RST

XTAL1

XTAL2

V

SS

V

DD

V

DD

I

DD

(NC)

CLOCK SIGNAL

Figure 13. IDD Test Condition, Idle Mode

All other pins are disconnected

2

V

DD

P1.6
P1.7

STADC

AV

SS

AV

ref–

EW

V

DD

P1.6
P1.7

STADC

EW

AV

SS

AV

ref–

VDD–0.5

0.5V

0.7V

DD

0.2VDD–0.1

t

CHCL

t

CLCL

t

CLCH

t

CLCX

t

CHCX

Figure 14. Clock Signal Waveform for IDD Tests in Active

and Idle Modes t

CLCH

= t

CHCL

= 5ns

V

DD

P0

RST

XTAL1

XTAL2

V

SS

V

DD

V

DD

I

DD

(NC)

Figure 15. IDD Test Condition, Power Down Mode

All other pins are disconnected. V

DD

= 2V to 5.5V

3

V

DD

P1.6
P1.7

STADC

EA

EW

AV

SS

AV

ref–

NOTES:

1. Active Mode:
a. The following pins must be forced to V

DD

: EA, RST, Port 0, and EW.

b. The following pins must be forced to V

SS

: STADC, AVss, and AV

ref–

.

c. Ports 1.6 and 1.7 should be connected to V

DD

through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the I

OL1

spec of these pins.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

2. Idle Mode:
a. The following pins must be forced to V

DD

: Port 0 and EW.

b. The following pins must be forced to V

SS

: RST, STADC, AVss,, AV

ref–

, and EA.

c. Ports 1.6 and 1.7 should be connected to V

DD

through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the I

OL1

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

3. Power Down Mode:
a. The following pins must be forced to V

DD

: Port 0 and EW.

b. The following pins must be forced to V

SS

: RST, STADC, XTAL1, AVss,, AV

ref–

, and EA.

c. Ports 1.6 and 1.7 should be connected to V

DD

through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the I

OL1

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I

2

C system provided the system conforms to the

I

2

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

22

QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT318-2

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

23

PLCC68: plastic leaded chip carrier; 68 leads; pedestal SOT188-3

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

24

1473A 68-PIN CERQUAD J-BEND (K) PACKAGE

NOTES:

1. All dimensions and tolerances to conform

2. UV window is optional.

3. Dimensions do not include glass protrusion.

Glass protrusion to be 0.005 inches maximum

4. Controlling dimension millimeters.

5. All dimensions and tolerances include

lead trim offset and lead plating finish.

6. Backside solder relief is optional and

dimensions are for reference only.

1.02 (0.040) X 45°

24.51 (0.965)

23.62 (0.930)

25.27 (0.995)

25.02 (0.985)

CHAMFER

45

24.51 (0.965)

23.62 (0.930)

25.27 (0.995)

25.02 (0.985)

on each side.

to ANSI Y14.5–1982.

2

3

3

3 X 0.63 (0.025) R MIN.

3.05 (0.120)

2.29 (0.090)

4.83 (0.190)

3.94 (0.155)

SEATING

PLANE

0.38 (0.015)

0.51 (0.02) X 45°

6

6

25.27 (0.995)

25.02 (0.985)

1.27 (0.050)

20.32 (0.800) NOMINAL

11.94 (0.470)

11.18 (0.440)

11.94 (0.470)

11.18 (0.440)

64X

4.83 (0.190)

3.94 (0.155)

SEATING

PLANE

0.15 (0.006) MIN.

0.25 (0.010) R MIN.

0.508 (0.020) R MIN.

0.25 (0.010)

0.15 (0.006)

90 + 5

–10

°°

°

0.076 (0.003) MIN.

DETAIL B

mm/(inch)

SEE DETAIL B

SEE DETAIL A

DETAIL A

TYP. ALL SIDES

mm/(inch)

1.52 (0.060) REF.

0.482 (0.019 + 0.002)

SEATING

PLANE

1.02 + 0.25 (0.040 + 0.010)

BASE PLANE

45 TYP.

4 PLACES

°

0.73 + 0.08 (0.029 + 0.003)

1.27 (0.050) TYP.

853-1473A 05854

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

25

NOTES

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

26

NOTES

Philips Semiconductors Product specification

80C552/83C552

Single-chip 8-bit microcontroller

1996 Aug 06

27

NOTES

Philips Semiconductors Product specification

80C552/83C552Single-chip 8-bit microcontroller

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.

LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

DEFINITIONS

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation

register eligible circuits under the Semiconductor Chip Protection Act.

 Copyright Philips Electronics North America Corporation 1996

All rights reserved. Printed in U.S.A.