Page 1
INTEGRATED CIRCUITS
PCA9559
5-bit multiplexed/1-bit latched 6-bit I
EEPROM
Product specification
Supersedes data of 1999 Oct 20
2
C
2000 Jan 31
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Philips Semiconductors Product specification
PCA95595-bit multiplexed/1-bit latched 6-bit I2C EEPROM
FEA TURES
PIN CONFIGURATION
•5-bit 2-to-1 multiplexer, 1-bit latch
2
C SCL
•6-bit internal non-volatile register
•Internal non-volatile register programmable and readable via I
•Override input forces all outputs to logic 0
•5 open drain multiplexed outputs
•1 open drain non-multiplexed (latched) output
•5V and 2.5V tolerant inputs
•Useful for ‘jumperless’ configuration of PC motherboards
•2 address pins, allowing up to 4 devices on the I
2
C bus
2
C bus
I
I
MUX_IN A
MUX_IN B
MUX_IN C
MUX_IN D
MUX_IN E
2
C SDA
GND
1
2
A1
3
4
A0
5
6
7
8
9
10
DESCRIPTION
The primary function of the 5-bit multiplexer, 1-bit latch is to enable
system configuration.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
20-Pin Plastic TSSOP 0°C to +70°C PCA9559 PW DH SOT360-1
FUNCTIONAL DESCRIPTION
When the MUX_SELECT signal is logic 0, the multiplexer will select
the data from the non-volatile register to drive on the MUX_OUT
pins. When the MUX_SELECT signal is logic 1, the multiplexer will
select the MUX_IN lines to drive on the MUX_OUT pins. The
MUX_SELECT signal is also used to latch the NON_MUXED_OUT
signal which outputs data from the non-volatile register. The
NON_MUXED_OUT signal latch is transparent when MUX_SELECT
is in a logic 0 state, and will latch data when MUX_SELECT is in a
logic 1 state. When the active-LOW OVERRIDE# signal is set to
logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will
be driven to logic 0. This information is summarized in Table 1.
The Write Protect (WP) input is used to control the ability to write the
contents of the 6-bit non-volatile register. If the WP signal is logic 0,
2
the I
C bus will be able to write the contents of the non-volatile
register. If the WP signal is logic 1, data will not be allowed to be
written into the non-volatile register.
The factory default for the contents of the non-volatile register are all
logic 0. These stored values can be read or written using the I
bus (described in the next section).
The OVERRIDE#, WP, MUX_IN, and MUX_SELECT signals have
internal pullup resistors. See the DC and AC Characteristics for
hysteresis and signal spike suppression figures.
2
C
FUNCTION TABLE
OVERRIDE# MUX_SELECT
0 0 All 0’s All 0’s
0 1
1 0
1 1
NOTE:
1. NON_MUXED_OUT state will be the value present on the output
at the time of the MUX_SELECT input transitioned from a logic 0
to a logic 1 state.
MUX_OUT
OUTPUTS
From non-
20
19
18
17
16
15
14
13
12
11
MUX_IN
inputs
volatile
register
MUX_IN
inputs
V
WP
OVERRIDE #
NON_MUXED_OUT
MUX_OUT A
MUX_OUT B
MUX_OUT C
MUX_OUT D
MUX_OUT E
MUX_SELECT
CC
SW00216
NON_MUXED_OUT
OUTPUT
Latched
NON_MUXED
From non-volatile
register
From non-volatile
register
_OUT
1
2000 Jan 31 853-2181 23063
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Philips Semiconductors Product specification
PCA95595-bit multiplexed/1-bit latched 6-bit I2C EEPROM
PIN DESCRIPTION
PIN
NUMBER
1 I2C SCL Serial I2C bus clock
2 I2C SDA Serial bi-directional I2C bus data
3 A1 Address A1
4 A0 Address A0
5 MUX_IN A
6 MUX_IN B
7 MUX_IN C
8 MUX_IN D
9 MUX_IN E
10 GND Ground
11 MUX_SELECT Selects MUX_IN inputs or register contents for MUX_OUT outputs
12 MUX_OUT E
13 MUX_OUT D
14 MUX_OUT C
15 MUX_OUT B
16 MUX_OUT A
17 NON_MUXED_OUT Open drain outputs from non-volatile memory
18 OVERRIDE# Forces all outputs to logic 0
19 WP Non-volatile register write-protect
20 V
SYMBOL FUNCTION
External inputs to multiplexer
Open drain multiplexed outputs
CC
Positive voltage rail
I2C INTERFACE
Communicating with this device is initiated by sending a valid address on the I2C bus. The address format (see FIgure 1) has 5 fixed bits and
two user-programmable bits followed by a 1-bit read/write value which determines the direction of the data transfer.
MSB LSB
10 0
1 1 A1 A0
Figure 1. I2C Address Byte
Following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write
data to the non-volatile register . Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be read
from the register if the bit is logic 1. The four high-order bits are latched outputs, while the four low order bits are multiplexed outputs (Figure 2).
NOTE:
1. To ensure data integrity, the non-volatile register must be internally write protected when V
component is dropped below normal operating levels.
MSB LSB
00
Non_muxed
Data
Mux
Data E
Mux
Data D
to the I2C bus is powered down or VCC to the
CC
Mux
Data C
Mux
Data B
R/W#
SW00218
Mux
Data A
SW00456
2000 Jan 31
Figure 2. I2C Data Byte
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Philips Semiconductors Product specification
PCA95595-bit multiplexed/1-bit latched 6-bit I2C EEPROM
BLOCK DIAGRAM
10–30k Ω
MUX_SELECT
11
OVERRIDE#
18
A0
4
A1
3
SCL
1
2
I
SDA
2
2
I
VCC = 20
GND = 10
WRITE
19
PROTECT
5
MUX_IN A
6
MUX_IN B
7
MUX_IN C
8
MUX_IN D
C CLOCK
C DATA
100–150k Ω
I C iNTERFACE LOGIC
2
OE#
6-BIT EEPROM
LATCH
NMO
0
5-BIT 2 to 1 MULTIPLEXER
SELECT
NON_MUXED_OUT
MUX_OUT A
MUX_OUT B
MUX_OUT C
MUX_OUT D
MUX_OUT E
17
16
15
14
13
12
2000 Jan 31
9
MUX_IN E
10–30k Ω
1
SW00400
4
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITIONS
UNIT
SCL, SDA
,_,
MUX_OUT, NON_MUXED_OUT
PCA95595-bit multiplexed/1-bit latched 6-bit I2C EEPROM
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
V
CC
V
I
V
OUT
T
stg
DC supply voltage –0.5 to +4.6 V
DC input voltage Note 3 –1.5 to VCC +1.5 V
DC output voltage Note 3 –0.5 to VCC +0.5 V
Storage temperature range –60 to +150 °C
PARAMETER CONDITIONS RATING UNIT
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
V
CC
OVERRIDE#, MUX_IN,
MUX_SELECT
dt/dv Input transition rise or fall time 0 10 ns/V
T
amb
DC supply voltage 3.0 3.6 V
V
IL
V
IH
V
OL
V
OL
V
IL
V
IH
I
OL
I
OH
IOL= 3 mA –0.5 0.9 V
IOL= 3 mA 2.7 4.0 V
IOL= 3 mA 0.4 V
IOL= 6 mA 0.6 V
–0.5 0.8 V
2.0 4.0 V
8 mA
100 µA
Operating temperature 0 70 °C
2000 Jan 31
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITION
UNIT
PCA95595-bit multiplexed/1-bit latched 6-bit I2C EEPROM
DC CHARACTERISTICS
LIMITS
MIN. TYP. MAX.
Supply
V
CC
I
CCL
I
CCH
Input SCL: Input/Output SDA
V
IL
V
IH
I
OL
I
OL
I
IH
I
IL
C
I
Override #, WP, Mux_Select
I
IH
I
IL
C
I
Mux A → E
I
IH
I
IL
C
I
A0, A1 Inputs
I
IH
I
IL
C
I
Mux_Outputs
V
OL
V
OL
Non_Mux_Output
V
OL
V
OL
NOTES:
1. V
is the hysteresis of Schmitt-Trigger inputs
HYS
Supply Voltage 3 3.8 V
Supply Current Operating mode ALL inputs = 0 V 10 mA
Supply Current Operating mode ALL inputs = V
CC
600 µA
Low Level Input Voltage –0.5 0.8 V
High Level Input Voltage 2 VCC + 0.5 V
Low Level Output Current VOL = 0.4 3 mA
Low Level Output Current VOL = 0.6 6 mA
Leakage Current High V
Leakage Current Low V
= V
I
CC
= GND –7 –32 µA
I
–1.5 –12 µA
Input Capacitance 10 pF
Leakage Current High V
Leakage Current Low V
= V
I
CC
= GND –86 –267 µA
I
–20 –100 µA
Input Capacitance 10 pF
Leakage Current High V
Leakage Current Low V
= V
I
CC
= GND –0.72 –2 mA
I
–0.166 –0.75 mA
Input Capacitance 10 pF
Leakage Current High V
Leakage Current Low V
= V
I
CC
= GND –1 1 µA
I
–1 1 µA
Input Capacitance 10 pF
Low Level Output Current (IOL = 100 µA) 0.4 V
Low Level Output Current (IOL = 2 mA) 0.7 V
(IOL = 100 µA) 0.4 V
(IOL = 2 mA) 0.7 V
NON-VOLATILE STORAGE SPECIFICATIONS
PARAMETER SPECIFICATION
Memory cell data retention 10 years min
Number of memory cell write cycles 3,000 cycles min
2000 Jan 31
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
PCA95595-bit multiplexed/1-bit latched 6-bit I2C EEPROM
AC CHARACTERISTICS
LIMITS
MIN. TYP. MAX.
MUX_in ⇒ MUX_out
T
plh
T
phl
Select ⇒ MUX_out
T
plh
T
phl
Override ⇒ Non-MUX_out
T
plh
T
phl
Override ⇒ MUX_out
T
plh
T
phl
T
R
T
F
P
F
C
L
Output rise time 1.0 3 ns/V
Output fall time 1.0 3 ns/V
Pull-up resistor for outputs 1.0 ns/V
Test load capacitance on outputs pF
I2C Bus
t
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SP
t
SU:STO
t
R
t
C
T
W
Bus free time between a STOP and a START condition 1.3 µs
Hold time (repeated) STAR T condition. After this period, the first
Set-up time for a repeated STAR T condition 600 –32 ns
Rise time for both SDA and SCL signals (10 – 400 pF bus) 20 300 ns
I
L
Fall time for both SDA and SCL signals (10 – 400 pF bus) 20 300 ns
SCL clock frequency 10 400 kHz
clock pulse is generated
600 ns
LOW period of SCL clock 1.3 µs
HIGH period of SCL clock 600 –12 ns
Data hold time 0 10 ns
Data set-up time 100 –100 ns
Data spike time 0 50 ns
Set-up time for STOP condition 600 10 ns
Capacitive load for each bus line 400 pF
Write cycle time
1
NOTE:
1. WRITE CYCLE time can only be measured indirectly during the write cycle. During this time, the device will not acknowledge its I
28 37 nS
16 21 nS
30 39 nS
17 22 nS
34 43 nS
19 25 nS
31 41 nS
21 27 nS
15 mS
2
C Address.
2000 Jan 31
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Philips Semiconductors Product specification
PCA95595-bit multiplexed/1-bit latched 6-bit I2C EEPROM
SDA
t
R
t
HD;DAT
V
M
t
PLZ
V
O
VOL + 0.3V
V
OL
SV00500
SCL
MUX INPUT
MUX OUTPUT
t
BUF
V
M
t
PHL
V
t
LOW
t
HD;STA
M
Waveform 1. Open drain output enable and disable times
t
HIGH
V
CC
D.U.T.
t
SP
t
SU;STO
PP S
SU00645
V
O
V
OUT
R
L
C
L
t
F
t
SU;DAT
PULSE
GENERATOR
t
HD;STA
t
SU;STA
Sr
V
IN
R
T
Test Circuit for Open Drain Outputs
DEFINITIONS
RL = Load resistor; 1 kΩ
C
= Load capacitance includes jig and probe capacitance;
L
10 pF
= Termination resistance should be equal to Z
R
T
pulse generators.
OUT
of
SW00510
2000 Jan 31
8
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Philips Semiconductors Product specification
PCA95595-bit multiplexed/1-bit latched 6-bit I2C EEPROM
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
2000 Jan 31
9
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Philips Semiconductors Product specification
PCA95595-bit multiplexed/1-bit latched 6-bit I2C EEPROM
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Date of release: 01-00
Document order number: 9397 750 06833
2000 Jan 31
10
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