Page 1
1
- February 1998
Highlights
www.national.com
©
1998 National Semiconductor Corporation
PRELIMINARY
February 1998
PC87317VUL/PC97317VUL SuperI/O Plug and Play
Compatible with ACPI Compliant Controller/Extender
Highlights
General Description
The PC87317VUL/PC97317VUL are functionally identical
parts that offer a single-chip solution to the most commonly
used ISA, EISA and MicroChannel
®
peripherals. This fully
Plug and Play (PnP) compatible chip conforms to the
Plug
and Play ISA Specification
Version 1.0a, May 5, 1994, and
meets specifications defined in the
PC97 Hardware Design
Guide
. It features a Controller/Extender that is fully compliant with Advanced Configuration and Power Interface (ACPI) Revision 1.0 requirements.
Note: All references to the PC87317VUL in this document
also refer to the PC97317VUL, unless otherwise specified.
References which are applicable to the PC97317VUL only
are italicized.
The PC87317VUL incorporates: an advanced Real-Time
Clock (RTC) device that provides both RTC timekeeping and
Advanced Power Control (APC) functionality, a Floppy Disk
Controller (FDC), a Keyboard and Mouse Controller (KBC),
two enhanced Serial Ports (UARTs) with Infrared (IR) support, a full IEEE 1284 Parallel Port, 24 General-Purpose Input/Output (GPIO) bit ports, three general-purpose chip
select signals that can be programmed for game port control
and a separate configuration register set for each module.
The PC87317VUL provides a LED drive output to comply
with PC97 specifications. The chip also provides support for
Power Management (PM), including a WATCHDOG timer,
and standard PC-AT address decoding for on-chip functions.
The PC87317VUL Infrared (IR) interface complies with the
HP-SIR and SHARP-IR standards, and supports all four basic protocols for Consumer Remote Control circuitry (RC-5,
RC-5 extended, RECS80 and NEC).
Outstanding Features
Among the most advanced members of National Semiconductor’s highly successful SuperI/O family, the PC87317VUL
offers:
●
Full compatibility with ACPI Revision 1.0 requirements
●
Compliancy with
PC97 Hardware Design Guide
speci-
fications, including PC97 LED support
●
Advanced RTC, including timekeeping and APC functionality
●
24 GPIO bit ports
●
FDC, KBC, two enhanced UARTs, IR support, IEEE
1284 parallel port
Block Diagram
Real-Time Clock
Floppy Disk
Controller (FDC)
Keyboard + Mouse
Controller (KBC)
Management (PM
)
µP Address
Floppy Drive
Interface
Data Handshake
Data
X-Bus
Control
Parallel Port
(PnP)
IRQ
Control
DMA
Channels
(RTC and APC)
Plug and Play
Data and
Control
General-Purpose I/O
(GPIO) Registers
I/O Ports
Control
Control
Data and
IEEE 1284
(Logical Device 2)
(Logical Devices 0 & 1)
(Logical Device 8)
(Logical Device 4)
(Logical Device 7)
(Logical Device 3)
Ports
Serial
with IR (UART2)
Interface
Infrared
Interface
(Logical Devices 5)
Power
Serial
(UART1)
Interface
(Logical Devices 6)
Serial Port Serial Port
TRI-STATE® and WATCHDOG are trademarks of National Semiconductor Corporation.
IBM
®
, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.
Microsoft
®
and Windows® are registered trademarks of Microsoft Corporation.
Page 2
2
Highlights
www.national.com
Features
●
100% compatibility with PnP requirements specified in
the “
Plug and Play ISA Specification
”, ISA, EISA, and
MicroChannel architectures
●
A special PnP module that includes:
— Flexible IRQs, DMAs and base addresses that meet
the PnP requirements specified by Microsoft
®
in
their 1995 hardware design guide for Windows
®
and
PnP ISA Revision 1.0A
— PnP ISA mode (with isolation mechanism – Wait for
Key state)
— Motherboard PnP mode
●
An FDC that provides:
— A modifiable address that is referenced by a 16-bit
programmable register
— Software compatibility with the PC8477, which con-
tains a superset of the floppy disk controller functions in the µDP8473, the NEC µPD765A and the
N82077
— 13 IRQ channel options
— Four 8-bit DMA channel options
— 16-byte FIFO
— Burst and non-burst modes
— A new, high-performance, internal, digital data sep-
arator that does not require any external filter components
— Support for standard 5.25" and 3.5" floppy disk
drives
— Automatic media sense support
— Perpendicular recording drive support
— Three-mode Floppy Disk Drive (FDD) support
— Full suppor t for the IBM Tape Dr ive Register (TDR)
implementation of AT and PS/2 drive types
●
A KBC with:
— A modifiable address that is referenced by a 16-bit
programmable register, reported as a fixed address
in resource data
— 13 IRQ options for the Keyboard Controller
— 13 IRQ options for the Mouse Controller
— An 8-bit microcontroller
— Software compatibility with 8042AH and PC87911
microcontrollers
— 2 KB of custom-designed program ROM
— 256 bytes of RAM for data
— Five programmable dedicated open drain I/O lines
for keyboard controller applications
— Asynchronous access to two data registers and one
status register during normal operation
— Support for both interrupt and polling
— 93 instructions
— An 8-bit timer/counter
— Support for binary and BCD arithmetic
— Operation at 8 MHz,12 MHz or 16 MHz (programma-
ble option)
— Customizing by using the PC87323VUL, which in-
cludes a RAM-based KBC, as a development platform for keyboard controller code for the
PC87317VUL
●
An RTC that has:
— A modifiable address that is referenced by a 16-bit
programmable register
— 13 IRQ options, with programmable polarity
— DS1287, MC146818 and PC87911 compatibility
— 242 bytes of battery backed up CMOS RAM in two
banks
— Selective lock mechanisms for the RTC RAM
— Battery backed up century calendar in days, day of
the week, date of month, months, years and century ,
with automatic leap-year adjustment
— Battery backed-up time of day in seconds, minutes
and hours that allows a 12 or 24 hour format and adjustments for daylight savings time
— BCD or binary format for time keeping
— Three different maskable interrupt flags:
• Periodic interrupts - At intervals from 122 msec
to 500 msec
• Time-of-Month alarm - At intervals from once per
second to once per Month
• Updated Ended Interrupt - Once per second
upon completion of update
— Separate battery pin, 2.4 V operation that includes
an internal UL protection resistor
— 2 µA maximum power consumption during power
down
— Double-buffer time registers
●
ACPI Controller/Extender that supports the requirements of the ACPI spec (rev 1.0):
— Power Management Timer
— Power Button
— Real Time Clock Alarm
— Suspend modes via software emulation
— PnP SCI
— Global Lock mechanism
— General Purpose events
— Date of Month Alarm
— Century byte
●
An APC that controls the main power supply to the system, using open-drain output, as follows:
Power turned on when:
— The RTC reaches a pre-determined wake-up centu-
ry, date and time selection
— A high to low transition occurs on the RI input signals
of the UARTs
— A ring pulse or pulse train is detected on the RING
input signal
— A SWITCH input signal indicates a Switch On event
with a debounce-protection
— Any one of seven programmable Power Manage-
ment external trigger events occur
Powered turned off when:
— A SWITCH input signal indicates a Switch Off event
Page 3
3
Highlights
www.national.com
— A Fail-safe ev ent occurs (power-sav e mode detected
but the system is hung up)
— Software turns power off
— Any one of 10 programmable Power Management
trigger events occur
●
Two Serial Ports (UART1 and 2) that provide:
— Fully compatible with the 16550A and the 16450
— Extended UART mode
— 13 IRQ channel options
— Shadow register support for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
●
An enhanced UART with IR interface on the UART2 that
supports:
— IrDA 1.0-SIR
— ASK-IR option of SHARP-IR
— DASK-IR option of SHARP-IR
— Consumer Remote Control circuitry
— DMA handshake signal routing for either 1 or 2 chan-
nels
— A PnP compatible external transceiver
●
A bidirectional parallel port that includes:
— A modifiable address that is referenced by a 16-bit
programmable register
— Software or hardware control
— 13 IRQ channel options
— Four 8-bit DMA channel options
— Demand mode DMA support
— An Enhanced Parallel Port (EPP) that is compatible
with the new version EPP 1.9, and is IEEE 1284
compliant
— An Enhanced Parallel Port (EPP) that also supports
version EPP 1.7 of the Xircom specification
— Support for an Enhanced Parallel Port (EPP) as
mode 4 of the Extended Capabilities Port (ECP)
— An Extended Capabilities Port (ECP) that is IEEE
1284 compliant, including level 2
— Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
— Reduction of PCI bus utilization by supporting a de-
mand DMA mode mechanism and a DMA fairness
mechanism
— A protection circuit that prevents damage to the par-
allel port when a printer connected to it powers up or
is operated at high voltages
— Output buffers that can sink and source14 mA
●
Three general-purpose pins for three separate programmable chip select signals, as follows:
— Can be programmed for game port control
— The Chip Select 0 (
CS0) signal produces open drain
output and is powered by the V
CCH
— The Chip Select 1 (CS1) and 2 (CS2) signals have
push-pull buffers and are pow ered b y the main V
DD
— Decoding of chip select signals depends on the ad-
dress and the Address Enable (AEN) signals, and
can be qualified using the Read (
RD) and Write
(
WR) signals.
●
24 single-bit GPIO ports:
— Modifiable addresses that are referenced by a 16-bit
programmable register
— Programmable direction for each signal (input or out-
put)
— Programmable drive type for each output pin (open-
drain or push-pull)
— Programmable option for internal pull-up resistor on
each input pin
— Configuration-Lock options
— Several signals may be selected as interrupt triggers
— A back-drive protection circuit
●
An X-bus data buffer that connects the 8-bit X data bus
to the ISA data bus
●
Clock source options:
— Source is a 32.768 KHz crystal - an internal frequen-
cy multiplier generates all the required internal fre-
quencies.
— Source may be either a 48 MHz or 24 MHz clock in-
put signal.
●
Enhanced Power Management (PM), including:
— Special configuration registers for power down
— WATCHDOG timer for power-saving strategies
— Reduced current leakage from pins
— Low-power CMOS technology
— Ability to shut off clocks to all modules
— LED control powered by V
CCH
●
General features include:
— All accesses to the SuperI/O chip activate a Zero
Wait State (
ZWS) signal, except for accesses to the
Enhanced Parallel Por t (EPP) and to configuration
registers
— Access to all configuration registers is through an In-
dex and a Data register, which can be relocated
within the ISA I/O address space
— 160-pin Plastic Quad Flatpack (PQFP) package
Page 4
4
Highlights
www.national.com
Basic Configuration
DRATE0
Parallel
Port
Connector
Configuration
Select Logic
Clock
EIA
Drivers
EIA
Drivers
FDC
ONCTL
ISA Bus
X1
MR
AEN
A15-0
D7-0
RD
WR
TC
PD7-0
SLIN/ASTRB
STB/WRITE
AFD/DSTRB
INIT
ACK
ERR
SLCT
PE
BUSY/
WAIT
BADDR1,0
CFG1,0
V
CCH
SWITCH
RING
SIN1
SOUT1
RTS1
DTR1/BOUT1
CTS1
DSR1
DCD1
RI1
SIN2
SOUT2
RTS2
DTR2/BOUT2
CTS2
DSR2
DCD2
RI2
RDATA
WDATA
WGATE
HDSEL
DIR
STEP
TRK0
INDEX
DSKCHG
WP
MTR1,0
DR1,0
DENSEL
IOCHRDY
ZWS
Real-Time Clock (RTC)
Crystal and Power
V
BAT
X1C X2C
DRQ3-0
DACK3-0
P17,16,12
P21,20
KBCLK
KBDAT
MDAT
MCLK
Keyboard I/O
Interface
(GPIO)
CS2,0
MSEN1,0
GPIO27-20
GPIO17-10
IRQ1
Infrared (IR)
Interface
IRRX2,1
IRTX
PC87317VUL
IRQ12-3
IRQ15-14
IRSL2-0
SELCS
X-Bus
XDCS
XD7-0
XDRD
WDO
POR
ID3-0
GPIO37-30
LED
LED
Power
Management
(PM)
Connector
General Purpose I/O
Page 5
5
Table of Contents
www.national.com
Table of Contents
Highlights.......................................................................................................................................................1
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM .........................................................................................................16
1.2 SIGNAL/PIN DESCRIPTIONS ...................................................................................................17
2.0 Configuration
2.1 HARDWARE CONFIGURATION ...............................................................................................27
2.1.1 Wake Up Options ........................................................................................................27
2.1.2 The Index and Data Register Pair ...............................................................................27
2.1.3 The Strap Pins .............................................................................................................28
2.2 SOFTWARE CONFIGURATION ...............................................................................................28
2.2.1 Accessing the Configuration Registers ........................................................................28
2.2.2 Address Decoding .......................................................................................................28
2.3 THE CONFIGURATION REGISTERS .......................................................................................29
2.3.1 Standard Plug and Play (PnP) Register Definitions ....................................................30
2.3.2 Configuration Register Summary ................................................................................33
2.4 CARD CONTROL REGISTERS ................................................................................................37
2.4.1 PC87317 SID Register ................................................................................................37
2.4.2 PC97317 SID Register ................................................................................................37
2.4.3 SuperI/O Configuration 1 Register (SIOC1) ................................................................37
2.4.4 SuperI/O Configuration 2 Register (SIOC2) ................................................................38
2.4.5 Programmable Chip Select Configuration Index Register ...........................................38
2.4.6 Programmable Chip Select Configuration Data Register ............................................39
2.4.7 SuperI/O Configuration 3 Register (SIOC3) ................................................................39
2.4.8 PC97317 SRID Register ..............................................................................................39
2.4.9 SuperI/O Configuration F Register (SIOCF), Index 2Fh ..............................................40
2.5 KBC CONFIGURATION REGISTER (LOGICAL DEVICE 0) ....................................................40
2.5.1 SuperI/O KBC Configuration Register .........................................................................40
2.6 FDC CONFIGURATION REGISTERS (LOGICAL DEVICE 3) ..................................................40
2.6.1 SuperI/O FDC Configuration Register .........................................................................40
2.6.2 Drive ID Register .........................................................................................................41
2.7 PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 4) ...............................41
2.7.1 SuperI/O Parallel Port Configuration Register .............................................................41
2.8 UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 5) ....................42
2.8.1 SuperI/O UART2 Configuration Register .....................................................................42
2.9 UART1 CONFIGURATION REGISTER (LOGICAL DEVICE 6) ................................................42
2.9.1 SuperI/O UART1 Configuration Register .....................................................................42
2.10 PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS ......................................42
2.10.1 CS0 Base Address MSB Register ...............................................................................43
2.10.2 CS0 Base Address LSB Register ................................................................................43
2.10.3 CS0 Configuration Register .........................................................................................43
2.10.4 Reserved .....................................................................................................................43
2.10.5 CS1 Base Address MSB Register ...............................................................................43
Page 6
6
Table of Contents
www.national.com
2.10.6 CS1 Base Address LSB Register ................................................................................43
2.10.7 CS1 Configuration Register .........................................................................................43
2.10.8 Reserved .....................................................................................................................44
2.10.9 CS2 Base Address MSB Register ...............................................................................44
2.10.10 CS2 Base Address LSB Register ................................................................................44
2.10.11 CS2 Configuration Register .........................................................................................44
2.10.12 Reserved, Second Level Indexes 0Bh-0Fh .................................................................44
2.10.13 Not Accessible, Second Level Indexes 10h-FFh .........................................................44
2.11 CONFIGURATION REGISTER BITMAPS ................................................................................44
3.0 Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
3.1 SYSTEM ARCHITECTURE .......................................................................................................47
3.2 FUNCTIONAL OVERVIEW .......................................................................................................48
3.3 DEVICE CONFIGURATION ......................................................................................................48
3.3.1 I/O Address Space ......................................................................................................48
3.3.2 Interrupt Request Signals ............................................................................................48
3.3.3 KBC Clock ...................................................................................................................49
3.3.4 Timer or Event Counter ...............................................................................................50
3.4 EXTERNAL I/O INTERFACES ..................................................................................................50
3.4.1 Keyboard and Mouse Interface ...................................................................................50
3.4.2 General Purpose I/O Signals .......................................................................................50
3.5 INTERNAL KBC - PC87317VUL INTERFACE ..........................................................................51
3.5.1 The KBC DBBOUT Register, Offset 60h, Read Only ..................................................52
3.5.2 The KBC DBBIN Register, Offset 60h (F1 Clear) or 64h (F1 Set), Write Only ............52
3.5.3 The KBC STATUS Register ........................................................................................52
3.6 INSTRUCTION TIMING .............................................................................................................52
4.0 Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
4.1 RTC OVERVIEW .......................................................................................................................53
4.1.1 RTC Hardware and Functional Description .................................................................53
4.1.2 Timekeeping ................................................................................................................54
4.1.3 Power Management ....................................................................................................55
4.1.4 Interrupt Handling ........................................................................................................56
4.2 THE RTC REGISTERS .............................................................................................................56
4.2.1 RTC Control Register A (CRA) ....................................................................................56
4.2.2 RTC Control Register B (CRB) ....................................................................................57
4.2.3 RTC Control Register C (CRC) ...................................................................................58
4.2.4 RTC Control Register D (CRD) ...................................................................................58
4.2.5 Date-of-Month Alarm Register (DMAR ........................................................................59
4.2.6 Month Alarm Register (MAR) ......................................................................................59
4.2.7 Century Register (CR) .................................................................................................59
4.3 APC OVERVIEW .......................................................................................................................59
4.3.1 System Power States ..................................................................................................61
4.3.2 System Power Switching Logic ...................................................................................62
4.4 APC DETAILED DESCRIPTION ...............................................................................................62
Page 7
7
Table of Contents
www.national.com
4.4.1 The ONCTL Flip-Flop and Signal ................................................................................62
4.4.2 Entering Power States .................................................................................................65
4.4.3 System Power-Up and Power-Off Activation Event Description ..................................67
4.5 APC REGISTERS ......................................................................................................................69
4.5.1 APC Control Register 1 (APCR1) ................................................................................70
4.5.2 APC Control Register 2 (APCR2) ................................................................................70
4.5.3 APC Status Register (APSR) ......................................................................................71
4.5.4 Wake up Day of Week Register (WDWR) ...................................................................71
4.5.5 Wake up Date of Month Register (WDMR) .................................................................72
4.5.6 Wake up Month Register (WMR) .................................................................................72
4.5.7 Wake up Year Register (WYR) ....................................................................................72
4.5.8 RAM Lock Register (RLR) ...........................................................................................72
4.5.9 Wake up Century Register (WCR) ..............................................................................73
4.5.10 APC Control Register 3 (APCR3) ................................................................................73
4.5.11 APC Control Register 4 (APCR4), Bank 2, Index 4Ah ................................................74
4.5.12 APC Control Register 5 (APCR5) ................................................................................75
4.5.13 APC Control Register 6 (APCR6) ................................................................................75
4.5.14 APC Control Register 7 (APCR7) ................................................................................76
4.5.15 APC Status Register 1 (APSR1) .................................................................................77
4.5.16 Day-of-Month Alarm Address Register (DADDR) ........................................................77
4.5.17 Month Alarm Address Register (MADDR) ...................................................................77
4.5.18 Century Address Register (CADDR) ...........................................................................77
4.6 ACPI FIXED REGISTERS .........................................................................................................78
4.6.1 Power Management 1 Status Low Byte Register (PM1_STS_LOW) ..........................78
4.6.2 Power Management 1 Status High Byte Register (PM1_STS_HIGH) ........................78
4.6.3 Power Management 1 Enable Low Byte Register (PM1_EN_LOW) ...........................79
4.6.4 Power Management 1 Enable High Byte Register (PM1_EN_HIGH) .........................79
4.6.5 Power Management 1 Control Low Byte Register (PM1_CNT_LOW) ........................80
4.6.6 Power Management 1 Control High Byte Register (PM1_CNT_HIGH) .......................80
4.6.7 Power Management Timer Low Byte Register (PM1_TMR_LOW) .............................80
4.6.8 Power Management Timer Middle Byte Register (PM1_TMR_MID) ...........................81
4.6.9 Power Management Timer High Byte Register (PM1_TMR_HIGH) ............................81
4.6.10 Power Management Timer Extended Byte Register (PM1_TMR_EXT) ......................81
4.7 GENERAL PURPOSE EVENT REGISTERS ............................................................................81
4.7.1 General Purpose 1 Status Register (GP1_STS0) .......................................................81
4.7.2 General Purpose 1 Status 1 Register (GP1_STS1), Offset 01h ..................................82
4.7.3 General Purpose 1 Status 2 Register (GP1_STS2), Offset 02h ..................................82
4.7.4 General Purpose 1 Status 3 Register (GP1_STS3), Offset 03h ..................................82
4.7.5 General Purpose 1 Enable 0 Register (GP1_EN0) .....................................................82
4.7.6 General Purpose 1 Enable 1 Register (GP1_EN1), Offset 05h ...................................83
4.7.7 General Purpose 1 Enable 2 Register (GP1_EN2), Offset 06hr .................................83
4.7.8 General Purpose 1 Enable 3 Register (GP1_EN3), Offset 07h ...................................83
4.7.9 General Purpose 2 Enable 0 Register (GP2_EN0) .....................................................83
4.7.10 Bit 3 - IRRX2 Enable (IRRX2_E) .................................................................................83
4.7.11 SMI Command Register (SMI_CMD), Offset 0Ch .......................................................83
4.8 RTC AND APC REGISTER BITMAPS ......................................................................................84
4.8.1 RTC Register Bitmaps .................................................................................................84
Page 8
8
Table of Contents
www.national.com
4.8.2 APC Register Bitmaps .................................................................................................84
4.9 REGISTER BANK TABLES .......................................................................................................89
5.0 The Digital Floppy Disk Controller (FDC) (Logical Device 3)
5.1 FDC FUNCTIONS .....................................................................................................................92
5.1.1 Microprocessor Interface .............................................................................................92
5.1.2 System Operation Modes ............................................................................................92
5.2 DATA TRANSFER .....................................................................................................................93
5.2.1 Data Rates ...................................................................................................................93
5.2.2 The Data Separator .....................................................................................................93
5.2.3 Perpendicular Recording Mode Support .....................................................................94
5.2.4 Data Rate Selection .....................................................................................................94
5.2.5 Write Precompensation ...............................................................................................95
5.2.6 FDC Low-Power Mode Logic .......................................................................................95
5.2.7 Reset ...........................................................................................................................95
5.3 THE FDC REGISTERS .............................................................................................................96
5.3.1 Status Register A (SRA) ..............................................................................................96
5.3.2 Status Register B (SRB) ..............................................................................................97
5.3.3 Digital Output Register (DOR) .....................................................................................97
5.3.4 Tape Drive Register (TDR) ..........................................................................................99
5.3.5 Main Status Register (MSR) ......................................................................................100
5.3.6 Data Rate Select Register (DSR) ..............................................................................101
5.3.7 Data Register (FIFO) .................................................................................................102
5.3.8 Digital Input Register (DIR) ........................................................................................103
5.3.9 Configuration Control Register (CCR) .......................................................................104
5.4 THE PHASES OF FDC COMMANDS .....................................................................................104
5.4.1 Command Phase .......................................................................................................104
5.4.2 Execution Phase ........................................................................................................104
5.4.3 Result Phase .............................................................................................................106
5.4.4 Idle Phase ..................................................................................................................106
5.4.5 Drive Polling Phase ...................................................................................................106
5.5 THE RESULT PHASE STATUS REGISTERS ........................................................................107
5.5.1 Result Phase Status Register 0 (ST0) .......................................................................107
5.5.2 Result Phase Status Register 1 (ST1) .......................................................................107
5.5.3 Result Phase Status Register 2 (ST2) .......................................................................108
5.5.4 Result Phase Status Register 3 (ST3) .......................................................................109
5.6 FDC REGISTER BITMAPS .....................................................................................................109
5.6.1 Standard ....................................................................................................................109
5.6.2 Result Phase Status ..................................................................................................111
5.7 THE FDC COMMAND SET .....................................................................................................112
5.7.1 Abbreviations Used in FDC Commands ....................................................................113
5.7.2 The CONFIGURE Command ....................................................................................114
5.7.3 The DUMPREG Command .......................................................................................114
5.7.4 The FORMAT TRACK Command .............................................................................115
5.7.5 The INVALID Command ............................................................................................117
5.7.6 The LOCK Command ................................................................................................118
Page 9
9
Table of Contents
www.national.com
5.7.7 The MODE Command ...............................................................................................119
5.7.8 The NSC Command ..................................................................................................121
5.7.9 The PERPENDICULAR MODE Command ...............................................................121
5.7.10 The READ DATA Command .....................................................................................122
5.7.11 The READ DELETED DATA Command ....................................................................124
5.7.12 The READ ID Command ...........................................................................................125
5.7.13 The READ A TRACK Command ...............................................................................126
5.7.14 The RECALIBRATE Command .................................................................................127
5.7.15 The RELATIVE SEEK Command ..............................................................................127
5.7.16 The SCAN EQUAL, the SCAN LOW OR EQUAL and the SCAN HIGH OR EQUAL
Commands ................................................................................................................128
5.7.17 The SEEK Command ................................................................................................129
5.7.18 The SENSE DRIVE STATUS Command ..................................................................129
5.7.19 The SENSE INTERRUPT Command ........................................................................130
5.7.20 The SET TRACK Command ......................................................................................131
5.7.21 The SPECIFY Command ..........................................................................................131
5.7.22 The VERIFY Command .............................................................................................133
5.7.23 The VERSION Command ..........................................................................................134
5.7.24 The WRITE DATA Command ....................................................................................134
5.7.25 The WRITE DELETED DATA Command ..................................................................135
5.8 EXAMPLE OF A FOUR-DRIVE CIRCUIT ...............................................................................136
6.0 Parallel Port (Logical Device 4)
6.1 PARALLEL PORT CONFIGURATION ....................................................................................137
6.1.1 Parallel Port Operation Modes ..................................................................................137
6.1.2 Configuring Operation Modes ....................................................................................137
6.1.3 Output Pin Protection ................................................................................................137
6.2 STANDARD PARALLEL PORT (SPP) MODES ......................................................................137
6.2.1 SPP Modes Register Set ...........................................................................................138
6.2.2 SPP Data Register (DTR) ..........................................................................................138
6.2.3 Status Register (STR) ...............................................................................................139
6.2.4 SPP Control Register (CTR) ......................................................................................140
6.3 ENHANCED PARALLEL PORT (EPP) MODES ......................................................................141
6.3.1 EPP Register Set .......................................................................................................141
6.3.2 SPP or EPP Data Register (DTR) .............................................................................141
6.3.3 SPP or EPP Status Register (STR) ...........................................................................141
6.3.4 SPP or EPP Control Register (CTR) .........................................................................142
6.3.5 EPP Address Register (ADDR) .................................................................................142
6.3.6 EPP Data Register 0 (DATA0) ..................................................................................142
6.3.7 EPP Data Register 1 (DATA1) ..................................................................................142
6.3.8 EPP Data Register 2 (DATA2) ..................................................................................142
6.3.9 EPP Data Register 3 (DATA3) ..................................................................................143
6.3.10 EPP Mode Transfer Operations ................................................................................143
6.3.11 EPP 1.7 and 1.9 Zero Wait State Data Write and Read Operations .........................144
6.4 EXTENDED CAPABILITIES PARALLEL PORT (ECP) ...........................................................145
6.4.1 ECP Modes ...............................................................................................................145
6.4.2 Software Operation ....................................................................................................145
Page 10
10
Table of Contents
www.national.com
6.4.3 Hardware Operation ..................................................................................................145
6.5 ECP MODE REGISTERS ........................................................................................................145
6.5.1 Accessing the ECP Registers ....................................................................................146
6.5.2 Second Level Offsets ................................................................................................146
6.5.3 ECP Data Register (DATAR) .....................................................................................147
6.5.4 ECP Address FIFO (AFIFO) Register .......................................................................147
6.5.5 ECP Status Register (DSR) .......................................................................................147
6.5.6 ECP Control Register (DCR) .....................................................................................148
6.5.7 Parallel Port Data FIFO (CFIFO) Register .................................................................148
6.5.8 ECP Data FIFO (DFIFO) Register .............................................................................148
6.5.9 Test FIFO (TFIFO) Register ......................................................................................149
6.5.10 Configuration Register A (CNFGA) ...........................................................................149
6.5.11 Configuration Register B (CNFGB) ...........................................................................149
6.5.12 Extended Control Register (ECR) .............................................................................150
6.5.13 ECP Extended Index Register (EIR) .........................................................................151
6.5.14 ECP Extended Data Register (EDR) .........................................................................152
6.5.15 ECP Extended Auxiliary Status Register (EAR) ........................................................152
6.5.16 Control0 Register .......................................................................................................152
6.5.17 Control2 Register .......................................................................................................152
6.5.18 Control4 Register .......................................................................................................153
6.5.19 PP Confg0 Register ...................................................................................................153
6.6 DETAILED ECP MODE DESCRIPTIONS ...............................................................................154
6.6.1 Software Controlled Data Transfer
(Modes 000 and 001) ................................................................................................154
6.6.2 Automatic Data Transfer
(Modes 010 and 011) ................................................................................................154
6.6.3 Automatic Address and Data Transfers (Mode 100) .................................................156
6.6.4 FIFO Test Access (Mode 110) ..................................................................................156
6.6.5 Configuration Registers Access
(Mode 111) ................................................................................................................156
6.6.6 Interrupt Generation ..................................................................................................156
6.7 PARALLEL PORT REGISTER BITMAPS ...............................................................................157
6.7.1 EPP Modes ................................................................................................................157
6.7.2 ECP Modes ...............................................................................................................158
6.8 PARALLEL PORT PIN/SIGNAL LIST ......................................................................................160
7.0 Enhanced Serial Port with IR - UART2 (Logical Device 5)
7.1 FEATURES ..............................................................................................................................161
7.2 FUNCTIONAL MODES OVERVIEW .......................................................................................161
7.2.1 UART Modes: 16450 or 16550, and Extended ..........................................................161
7.2.2 Sharp-IR, IrDA SIR Infrared Modes ...........................................................................161
7.2.3 Consumer IR Mode ...................................................................................................161
7.3 REGISTER BANK OVERVIEW ...............................................................................................161
7.4 UART MODES – DETAILED DESCRIPTION ..........................................................................162
7.4.1 16450 or 16550 UART Mode .....................................................................................162
7.4.2 Extended UART Mode ...............................................................................................163
Page 11
11
Table of Contents
www.national.com
7.5 SHARP-IR MODE – DETAILED DESCRIPTION .....................................................................163
7.6 SIR MODE – DETAILED DESCRIPTION ................................................................................163
7.7 CONSUMER-IR MODE – DETAILED DESCRIPTION ............................................................164
7.7.1 Consumer-IR Transmission .......................................................................................164
7.7.2 Consumer-IR Reception ............................................................................................164
7.8 FIFO TIME-OUTS ....................................................................................................................165
7.8.1 UART, SIR or Sharp-IR Mode Time-Out Conditions .................................................165
7.8.2 Consumer-IR Mode Time-Out Conditions .................................................................165
7.8.3 Transmission Deferral ...............................................................................................165
7.9 AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE ..........................................165
7.11 BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS .................................................166
7.11.1 Receiver Data Port (RXD) or the Transmitter Data Port (TXD) .................................166
7.11.2 Interrupt Enable Register (IER) .................................................................................167
7.11.3 Event Identification Register (EIR) ............................................................................168
7.11.4 FIFO Control Register (FCR) .....................................................................................170
7.11.5 Link Control Register (LCR) and Bank Selection Register (BSR) .............................171
7.11.6 Bank Selection Register (BSR) .................................................................................172
7.11.7 Modem/Mode Control Register (MCR) ......................................................................172
7.11.8 Link Status Register (LSR) ........................................................................................174
7.11.9 Modem Status Register (MSR) ..................................................................................175
7.11.10 Scratchpad Register (SPR) .......................................................................................175
7.11.11 Auxiliary Status and Control Register (ASCR) ..........................................................176
7.12 BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS .........................................176
7.12.1 Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)), ..............................177
7.12.2 Link Control Register (LCR) and Bank Select Register (BSR) ..................................177
7.13 BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................177
7.13.1 Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) ...........................178
7.13.2 Extended Control Register 1 (EXCR1) ......................................................................179
7.13.3 Link Control Register (LCR) and Bank Select Register (BSR) ..................................180
7.13.4 Extended Control and Status Register 2 (EXCR2) ....................................................180
7.13.5 Reserved Register .....................................................................................................180
7.13.6 TX_FIFO Current Level Register (TXFLV) ................................................................180
7.13.7 RX_FIFO Current Level Register (RXFLV) ...............................................................181
7.14 BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS ..........................................181
7.14.1 Module Revision ID Register (MRID) ........................................................................181
7.14.2 Shadow of Link Control Register (SH_LCR) .............................................................181
7.14.3 Shadow of FIFO Control Register (SH_FCR) ............................................................182
7.14.4 Link Control Register (LCR) and Bank Select Register (BSR) ..................................182
7.15 BANK 4 – IR MODE SETUP REGISTER ................................................................................182
7.15.1 Reserved Registers ...................................................................................................182
7.15.2 Infrared Control Register 1 (IRCR1) ..........................................................................182
7.15.3 Link Control Register (LCR) and Bank Select Register (BSR) ..................................182
7.15.4 Reserved Registers ...................................................................................................182
7.16 BANK 5 – INFRARED CONTROL REGISTERS .....................................................................183
7.16.1 Reserved Registers ...................................................................................................183
Page 12
12
Table of Contents
www.national.com
7.16.2 (LCR/BSR) Register ..................................................................................................183
7.16.3 Infrared Control Register 2 (IRCR2) ..........................................................................183
7.16.4 Reserved Registers ...................................................................................................183
7.17 BANK 6 – INFRARED PHYSICAL LAYER CONFIGURATION REGISTERS .........................183
7.17.1 Infrared Control Register 3 (IRCR3) ..........................................................................183
7.17.2 Reserved Register .....................................................................................................184
7.17.3 SIR Pulse Width Register (SIR_PW) .........................................................................184
7.17.4 Link Control Register (LCR) and Bank Select Register (BSR) ..................................184
7.17.5 Reserved Registers ...................................................................................................184
7.18 BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS 184
7.18.1 Infrared Receiver Demodulator Control Register (IRRXDC) .....................................184
7.18.2 Infrared Transmitter Modulator Control Register (IRTXMC) ......................................185
7.18.3 Consumer-IR Configuration Register (RCCFG), .......................................................187
7.18.4 Link Control/Bank Select Registers (LCR/BSR) ........................................................188
7.18.5 Infrared Interface Configuration Register 1 (IRCFG1) ...............................................188
7.18.6 Reserved Register .....................................................................................................189
7.18.7 Infrared Interface Configuration 3 Register (IRCFG3) ...............................................189
7.18.8 Infrared Interface Configuration Register 4 (IRCFG4) ...............................................189
7.19 UART2 WITH IR REGISTER BITMAPS ..................................................................................190
8.0 Enhanced Serial Port - UART1 (Logical Device 6)
8.1 REGISTER BANK OVERVIEW ...............................................................................................195
8.2 DETAILED DESCRIPTION ......................................................................................................195
8.2.1 16450 or 16550 UART Mode .....................................................................................196
8.2.2 Extended UART Mode ...............................................................................................196
8.3 FIFO TIME-OUTS ....................................................................................................................196
8.4 AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE ..........................................197
8.4.1 Transmission Deferral ...............................................................................................197
8.5 BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS .................................................197
8.5.1 Receiver Data Port (RXD) or the Transmitter Data Port (TXD) .................................197
8.5.2 Interrupt Enable Register (IER) .................................................................................198
8.5.3 Event Identification Register (EIR) ............................................................................199
8.5.4 FIFO Control Register (FCR) .....................................................................................200
8.5.5 Line Control Register (LCR) and Bank Selection Register (BSR) .............................201
8.5.6 Bank Selection Register (BSR) .................................................................................202
8.5.7 Modem/Mode Control Register (MCR) ......................................................................203
8.5.8 Line Status Register (LSR) ........................................................................................204
8.5.9 Modem Status Register (MSR) ..................................................................................205
8.5.10 Scratchpad Register (SPR) .......................................................................................205
8.5.11 Auxiliary Status and Control Register (ASCR) ..........................................................205
8.6 BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS .........................................206
8.6.1 Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)), ..............................206
8.6.2 Line Control Register (LCR) and Bank Select Register (BSR) ..................................207
8.7 BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................207
8.7.1 Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) ...........................207
Page 13
13
Table of Contents
www.national.com
8.7.2 Extended Control Register 1 (EXCR1) ......................................................................208
8.7.3 Line Control Register (LCR) and Bank Select Register (BSR) ..................................209
8.7.4 Extended Control and Status Register 2 (EXCR2) ....................................................209
8.7.5 Reserved Register .....................................................................................................209
8.7.6 TX_FIFO Current Level Register (TXFLV) ................................................................209
8.7.7 RX_FIFO Current Level Register (RXFLV) ...............................................................210
8.8 BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS ..........................................210
8.8.1 Module Revision ID Register (MRID) ........................................................................210
8.8.2 Shadow of Line Control Register (SH_LCR) .............................................................210
8.8.3 Shadow of FIFO Control Register (SH_FCR) ............................................................211
8.8.4 Line Control Register (LCR) and Bank Select Register (BSR) ..................................211
8.9 UART1 REGISTER BITMAPS .................................................................................................211
9.0 General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip
Select Output Signals
9.1 GPIO PORT ACTIVATION ......................................................................................................215
9.2 GPIO CONTROL REGISTERS ...............................................................................................215
9.2.1 Special GPIO Signal Features ...................................................................................215
9.2.2 Reading and Writing to GPIO Pins ............................................................................215
9.2.3 Multiplexed GPIO Signals ..........................................................................................215
9.2.4 Multiplexed GPIO Signal Selection ............................................................................215
9.3 PROGRAMMABLE CHIP SELECT OUTPUT SIGNALS .........................................................216
10.0 Power Management (Logical Device 8)
10.1 POWER MANAGEMENT OPTIONS .......................................................................................218
10.1.1 Configuration Options ................................................................................................218
10.1.2 WATCHDOG Feature ................................................................................................218
10.2 POWER MANAGEMENT REGISTERS ...................................................................................218
10.2.1 Power Management Index Register ..........................................................................218
10.2.2 Power Management Data Register ...........................................................................219
10.2.3 Function Enable Register 1 (FER1) ...........................................................................219
10.2.4 Function Enable Register 2 (FER2) ...........................................................................219
10.2.5 Power Management Control Register (PMC1) ..........................................................220
10.2.6 Power Management Control 2 Register (PMC2) .......................................................221
10.2.7 Power Management Control 3 Register (PMC3) .......................................................221
10.2.8 WATCHDOG Time-Out Register (WDTO) ................................................................222
10.2.9 WATCHDOG Configuration Register (WDCF) ..........................................................222
10.2.10 WATCHDOG Status Register (WDST) ......................................................................223
10.2.11 PM1 Event Base Address Register (Bits 7-0) ............................................................223
10.2.12 PM1 Event Base Address Register (Bits 15-8) ..........................................................223
10.2.13 PM Timer Base Address (Bits 7-0) ............................................................................223
10.2.14 PM Timer Base Address Register (Bits 15-8) ............................................................224
10.2.15 PM1 Control Base Address Register (Bits 7-0) .........................................................224
10.2.16 PM1 Control Base Address Register (Bits 15-8) .......................................................224
10.2.17 General Purpose Status Base Address Register (Bits 7-0) .......................................224
10.2.18 General Purpose Status Base Address Register (Bits 15-8) .....................................224
Page 14
14
Table of Contents
www.national.com
10.2.19 ACPI Support Register ..............................................................................................225
10.3 POWER MANAGEMENT REGISTER BITMAPS ....................................................................226
11.0 X-Bus Data Buffer
12.0 The Internal Clock
12.1 THE CLOCK SOURCE ............................................................................................................230
12.2 THE INTERNAL ON-CHIP CLOCK MULTIPLIER ...................................................................230
12.3 SPECIFICATIONS ...................................................................................................................230
12.4 POWER-ON PROCEDURE WHEN CFG0 = 0 ........................................................................230
13.0 Interrupt and DMA Mapping
13.1 IRQ MAPPING .........................................................................................................................231
13.2 DMA MAPPING .......................................................................................................................231
14.0 Device Specifications
14.1 GENERAL DC ELECTRICAL CHARACTERISTICS ...............................................................232
14.1.1 Recommended Operating Conditions .......................................................................232
14.1.2 Absolute Maximum Ratings .......................................................................................232
14.1.3 Capacitance ...............................................................................................................232
14.1.4 Power Consumption Under Recommended Operating Conditions ...........................233
14.2 DC CHARACTERISTICS OF PINS, BY GROUP ....................................................................233
14.2.1 Group 1 ......................................................................................................................233
14.2.2 Group 2 ......................................................................................................................234
14.2.3 Group 3 ......................................................................................................................234
14.2.4 Group 4 ......................................................................................................................235
14.2.5 Group 5 ......................................................................................................................235
14.2.6 Group 6 ......................................................................................................................235
14.2.7 Group 7 ......................................................................................................................236
14.2.8 Group 8 ......................................................................................................................236
14.2.9 Group 9 ......................................................................................................................237
14.2.10 Group 10 ....................................................................................................................237
14.2.11 Group 11 ....................................................................................................................238
14.2.12 Group 12 ....................................................................................................................238
14.2.13 Group 13 ....................................................................................................................239
14.2.14 Group 14 ....................................................................................................................239
14.2.15 Group 15 ....................................................................................................................240
14.2.16 Group 16 ....................................................................................................................240
14.2.17 Group 17 ....................................................................................................................240
14.2.18 Group 18 ....................................................................................................................240
14.2.19 Group 19 ....................................................................................................................241
14.2.20 Group 20 ....................................................................................................................241
14.2.21 Group 21 ....................................................................................................................241
14.2.22 Group 22 ....................................................................................................................241
14.2.23 Group 23 ....................................................................................................................241
14.2.24 Group 24 ....................................................................................................................242
Page 15
15
Table of Contents
www.national.com
14.2.25 Group 25 ....................................................................................................................242
14.2.26 Group 26 ....................................................................................................................243
14.2.27 Group 27 ....................................................................................................................243
14.2.28 Group 28 ....................................................................................................................243
14.3 AC ELECTRICAL CHARACTERISTICS ..................................................................................244
14.3.1 AC Test Conditions TA = 0 °C to 70 °C, VDD = 5.0 V ±10% ......................................244
14.3.2 Clock Timing ..............................................................................................................244
14.3.3 Microprocessor Interface Timing ...............................................................................245
14.3.4 Baud Output Timing ...................................................................................................247
14.3.5 Transmitter Timing .....................................................................................................248
14.3.6 Receiver Timing .........................................................................................................249
14.3.7 UART, Sharp-IR, SIR and Consumer Remote Control Timing ..................................251
14.3.8 IRSLn Write Timing ...................................................................................................252
14.3.9 Modem Control Timing ..............................................................................................252
14.3.10 DMA Timing ...............................................................................................................253
14.3.11 Reset Timing .............................................................................................................256
14.3.12 Write Data Timing ......................................................................................................257
14.3.13 Drive Control Timing ..................................................................................................258
14.3.14 Read Data Timing ......................................................................................................258
14.3.15 Parallel Port Timing ...................................................................................................259
14.3.16 Enhanced Parallel Port 1.7 Timing ............................................................................260
14.3.17 Enhanced Parallel Port 1.9 Timing ............................................................................261
14.3.18 Extended Capabilities Port (ECP) Timing ..................................................................262
14.3.19 GPIO Write Timing ....................................................................................................263
14.3.20 RTC Timing ...............................................................................................................263
14.3.21 APC Timing ...............................................................................................................264
14.3.22 Chip Select Timing ....................................................................................................267
14.3.23 LED Timing ................................................................................................................267
Glossary .....................................................................................................................................................268
Page 16
Signal/Pin Connection and Description
16
1.0 Signal/Pin Connection and Description
www.national.com
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM
80
75
70
65
60
55
50
1 5 10 15 20 25 30
859095100
4035
PC87317VUL
105110115120
45
41
81
121
125
130
135
140
145
150
155
160
A1
A2
V
SS
V
DD
A3A4A5A6A7A8A9
A10
A11
A12
A13
IOCHRDY
RD
ZWS
WGATE
TRK0WPRDATA
HDSEL
A0
MTR1
DSKCHG
DIR
STEP
WDATA
MSEN1
DENSEL
INDEX
MTR0
DR1
DR0
XDRD/ID3
MSEN0
V
DD
P21
P20
P17
P16/GPIO25
P12/
CS0
GPIO10
GPIO11
GPIO12
GPIO13
CS2/XD1
STB/WRITE
V
SS
V
DD
SLIN/ASTRB
SLCT
PE
BUSY/
WAIT
ACK
V
DD
INIT
D7
CS1/XD0/CSOUT-NSC-Test
X1
V
SS
D0D1D2D3D4D5D6
MR
X2C
V
CCH
A15
A14
V
BAT
X1C
VSSVDDKBCLK
KBDAT
MDAT
MCLK
IRQ15
IRQ14
IRQ12
IRQ11
DACK3
DRATE0
DTR1/BADDR0/BOUT1
RI1
DCD1
DSR1
SIN1
RTS1/BADDR1
SOUT1/CFG0
CTS1
IRQ10
AEN
WR
TC
IRQ9
IRQ8
IRQ7
IRQ6
IRQ1
IRQ3
IRQ4
IRQ5
GPIO14
GPIO15/PME2
GPIO16/PME1
GPIO17/WDO
GPIO20/IRSL1/ID1
GPIO21/IRSL0/IRSL2/ID2
GPIO22/POR
V
SS
V
DD
DRQ1
DRQ0
DACK2
DACK1
DACK0
DRQ2
DRQ3
ERR
V
SS
V
SS
V
SS
DTR2/CFG1/BOUT2
GPIO33/RI2
GPIO31/DCD2
GPIO32/DSR2
GPIO35/SIN2
GPIO34/RTS2
GPIO36/SOUT2
GPIO30/CTS2
AFD/DSTRB
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
V
SS
IRTX
GPIO24/IRRX1
GPIO37/IRRX2/IRSL0/ID0
IRSL1/ID1/XD7
IRSL2/SELCS/GPIO21/XD6
GPIO27/XD5
GPIO26/XD4
GPIO25/XD3
GPIO24/XD2
LED/
CS0
ONCTL
SWITCH
RING/XDCS
GPIO23/
RING
PlasticQuad Flatpack (PQFP), EIAJ
Order Number PC87317VUL/PC97317VUL
NS Package Number VUL160A
Page 17
Signal/Pin Connection and Description
SIGNAL/PIN DESCRIPTIONS
17
www.national.com
1.2 SIGNAL/PIN DESCRIPTIONS
TABLE 1-1 "Signal/Pin Description Table" lists the signals
of the PC87317VUL in alphabetical order and shows the
pin(s) associated with each. TABLE 1-2 "Multiplexed X-Bus
Data Buffer (XDB) Pins" on page 25 lists the X-Bus Data
Buffer (XDB) signals that are multiplexed and TABLE 1-6
"Pins with a Strap Function During Reset" on page 26 lists
the pins that have strap functions during reset.
The Module column indicates the functional module that is
associated with these pins. In this column, the System label
indicates internal functions that are common to more than
one module. The I/O and Group # column describes whether the pin is an input, output, or bidirectional pin (marked as
Input, Output or I/O, respectively).
TABLE 1-1. Signal/Pin Description Table
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
A15-0 29-26,
23-12
ISA-Bus Input
Group 1
ISA-Bus Address – A15-0 are used for address decoding on any
access except DMA accesses, on condition that the AEN signal is
low.
See Section 2.2.2 on page 28.
ACK 113 Parallel Port Input
Group 3
Acknowledge – This input signal is pulsed low by the printer to
indicate that it has received data from the parallel port. This pin is
internally connected to a weak pull-up.
AFD 119 Parallel Por t I/O
Group 13
Automatic Feed – When this signal is low the printer should
automatically feed a line after printing each line. This pin is in TRISTATE after a 0 is loaded into the corresponding control register bit.
An external 4.7 KΩ pull-up resistor should be attached to this pin.
For Input mode see bit 5 in Section 6.5.16 on page 152.
This signal is multiplexed with
DSTRB. See TABLE 6-12 on page 160
for more information.
AEN 30 ISA-Bus Input
Group 1
DMA Address Enable – This input signal disables function selection
via A15-0 when it is high. Access during DMA transfer is not affected
by this signal.
ASTRB 118 Parallel Port Output
Group 13
Address Strobe (EPP) – This signal is used in EPP mode as an
address strobe. It is active low.
This signal is multiplexed with
SLIN.See TABLE 6-12 on page 160 for
more information.
BADDR1,0 136, 134 Configuration Input
Group 5
Base Address Strap Pins 0 and 1 – These pins determine the base
addresses of the Index and Data registers, the value of the Plug and
Play ISA Serial Identifier and the configuration state immediately after
reset. These pins are pulled down by internal 30 KΩ resistors.
External 10 KΩ pull-up resistors to V
DD
should be employed.
BADDR1 is multiplexed with
RTS1.
BADDR0 is multiplexed with
DTR1 and BOUT1.
See TABLE 2-2 on page 28 and Section 2.1 on page 27.
BOUT2,1 148, 138 UART1,
UART 2
Output
Group 17
Baud Output – This multi-function pin provides the associated serial
channel Baud Rate generator output signal if test mode is selected,
i.e., bit 7 of the EXCR1 register is set. See “Bit 7 - Baud Generator
Test (BTEST)” on page 180.
After Master Reset this pin provides the SOUT function.
BOUT2 is multiplexed with DTR2 and CFG1.
BOUT1 is multiplexed with DTR1 and BADDR0.
BUSY 111 Parallel Port Input
Group 2
Busy – This pin is set to high by the printer when it cannot accept
another character. It is internally connected to a weak pull-down
resistor.
This signal is multiplexed with
WAIT. See TABLE 6-12 on page 160 for
more information.
Page 18
Signal/Pin Connection and Description
18
SIGNAL/PIN DESCRIPTIONS
www.national.com
CFG1-0 144, 138 Configuration Input
Group 5
Configuration Strap Pins 1-0 – These pins determine the default
configuration upon power up. These pins are pulled down by internal
30 KΩ resistors. Use external 10 KΩ pull-up resistors to V
DD
.
CFG1 is multiplexed with DTR2 and BOUT2. CFG0 is multiplexed with
SOUT1. See Table 2-2 on page 28.
CS0
68
106
General
Purpose
Output
Group 21
Group 12
Programmable Chip Select –
CS0, CS1 and CS2 are programmable
chip select and/or latch enable and/or output enable signals that have
many uses, for example, as game ports or for I/O port expansion.
The decoded address and the assertion conditions are configured via
the chip configuration registers. See Section 2.3 on page 29.
CS0 is multiplexed with LED on pin 68 and with P12 on pin 106. On
pin 68 is an open-drain output that is in TRI-STATE unless V
DD
is
applied.
CS1 is multiplexed with CSOUT-NSC-Test/XD0.
CS2 is multiplexed with XD1.
CS2,1 72, 71 General
Purpose
I/O
Group 9
CSOUTNSC-Test
71 NSC-use Output
Group 21
Chip Select Read Output, NSC-Test – National Semiconductor test
output. This is an open-drain output signal.
This signal is multiplexed with
CS1 and XD0.
CTS2,1 141, 131 UART1,
UART 2
Input
Group 1
UART1 and UART2 Clear to Send – When low, these signals indicate
that the modem or other data transfer device is ready to exchange data.
CTS2 is multiplexed with GPIO30.
D7-0 10-3 ISA-Bus I/O
Group 8
ISA-Bus Data – Bidirectional data lines to the microprocessor. D0 is
the LSB and D7 is the MSB. These signals have 24 mA (sink)
buffered outputs.
DACK3-0 59-56 ISA-Bus Input
Group 1
DMA Acknowledge 0,1,2 and 3 – These active low input signals
acknowledge a request for DMA services and enable the
IOWR and
IORD input signals during a DMA transfer. These DMA signals can be
mapped to the following logical devices: FDC, UART1, UART2 or
parallel port.
DCD2,1 142, 132 UART1,
UART 2
Input
Group 1
UART1 and UART2 Data Carrier Detected – When low, this signal
indicates that the modem or other data transfer device has detected
the data carrier.
DCD2 is multiplexed with GPIO31
DENSEL 94 FDC Output
Group 16
Density Select – Indicates that a high FDC density data rate (500
Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is
selected.
DENSELs polarity is controlled by bit 5 of the SuperI/O FDC
Configuration register as described in Section 2.6.1 on page 40.
DIR 90 FDC Output
Group 16
Direction – This output signal determines the direction of the Floppy
Disk Drive (FDD) head movement (active = step in, inactive = step
out) during a seek operation. During reads or writes,
DIR is inactive.
DR1,0 88, 87 FDC Output
Group 16
Drive Select 0 and 1 – These active low output signals are the
decoded drive select output signals.
DR0 and DR1 are controlled by
Digital Output Register (DOR) bits 0 and 1. They are encoded with
information to control four FDDs when bit 7 of the SuperI/O FDC
Configuration register is 1, as described in Section 2.6.1.
See
MTR0,1 for more information.
DRATE0 84 FDC Output
Group 20
Data Rate 0 – This output signal reflects the value of bit 0 of the
Configuration Control Register (CCR) or the Data Rate Select Register
(DSR), whichever was written to last. Output from the pin is totem-pole
buffered (6 mA sink, 6 mA source).
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Page 19
Signal/Pin Connection and Description
SIGNAL/PIN DESCRIPTIONS
19
www.national.com
DRQ3-0 55-52 ISA-Bus Output
Group 18
DMA Request 0, 1, 2 and 3 – These active high output signals inform
the DMA controller that a data transfer is needed. These DMA signals
can be mapped to the following logical devices: Floppy Disk Controller
(FDC), UART1, UART2 or parallel port.
DSKCHG 99 FDC Input
Group 1
Disk Change – This input signal indicates whether or not the drive
door has been opened. The state of this pin is available from the
Digital Input Register (DIR). This pin can also be configured as the
RGATE data separator diagnostic input signal via the MODE
command. See the MODE command in Section 5.7.7.
DSR2,1 143, 133 UART1,
UART 2
Input
Group 1
Data Set Ready – When low, this signal indicates that the data
transfer device, e.g., modem, is ready to establish a communications
link.
DSR2 is multiplexed with GPIO32.
DSTRB 119 Parallel Port Output
Group 13
Data Strobe – This signal is used in EPP mode as a data strobe. It
is active low.
DSTRB is multiplexed with AFD. See TABLE 6-12 for more
information.
DTR2,1 144, 134 UART1,
UART 2
Output
Group 17
Data Terminal Ready – When low, this output signal indicates to the
modem or other data transfer device that the UART1 or UART2 is
ready to establish a communications link.
A Master Reset (MR) deactivates this signal high, and loopback
operation holds this signal inactive.
DTR2 is multiplexed with CFG1 and BOUT2.
DTR1 is multiplexed with BADDR0 and BOUT1.
ERR 116 Parallel Port Input
Group 3
Error – This input signal is set active low by the printer when it has
detected an error. This pin is internally connected to a weak pull-up.
GPIO17-15
GPIO14
GPIO13,12
GPIO11
GPIO10
156-154
153
152,151
150
149
General
Purpose
I/O
Group 10
Group 25
Group 10
Group 24
Group 10
General Purpose I/O Signals 17-10 – General purpose I/O signals of
I/O Port 1.
GPIO17 is multiplexed with
WDO.
GPIO16 is multiplexed with PME1.
GPIO15 is multiplexed with PME2.
GPIO27,26
GPIO25
GPIO24
GPIO23,22
GPIO21
GPIO20
76,75,
74 or 107,
73 or 80,
160-159,
158 or 77
157.
General
Purpose
I/O
Group 10
Group 25
Group 10
Group 10
Group 10
Group 10
General Purpose I/O Signals 27-20 – General purpose I/O por t 2
signals.
GPIO27-26 are multiplexed with XD5-4, respectively.
GPIO25 is multiplexed with XD3 on pin 74 and with P16 on pin107.
GPIO24 is multiplexed with XD2 on pin 73 and with IRRX1 on pin 80.
GPIO23 is multiplexed with
RING.
GPIO22 is multiplexed with
POR.
GPIO21 is multiplexed on pin 158 with IRSL2, IRSL0 and ID2 and on pin
77 with IRSL2, SELCS and XD6. See Bits 4,3 - GPIO21, IRSL2/ID2 or
IRSL0 Pin Select in Section 2.4.4.
GPIO20 is multiplexed with IRSL1 and ID1.
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Page 20
Signal/Pin Connection and Description
20
SIGNAL/PIN DESCRIPTIONS
www.national.com
GPIO37-30 79,
148-145,
143-141
General
Purpose
I/O
Group 10
General Purpose I/O Signals 37-30 – General purpose I/O por t 3
signals.
GPIO37 is multiplexed with IRRX2, IRSL0 and ID0.
GPIO36 is multiplexed with SOUT2.
GPIO35 is multiplexed with SIN2.
GPIO34 is multiplexed with
RTS2.
GPIO33 is multiplexed with
RI2.
GPIO32 is multiplexed with
DSR2.
GPIO31 is multiplexed with
DCD2.
GPIO30 is multiplexed with
CTS2.
HDSEL 92 FDC Output
Group 16
Head Select – This output signal determines which side of the FDD
is accessed. Active low selects side 1, inactive selects side 0.
ID3-0 70, 158,
78 or 157,
79
UART2 Input
Group 1
Identification – These ID signals identify the infrared transceiver for
Plug and Play support. These pins are read after reset.
ID3 is multiplexed with
XDRD.
ID2 is multiplexed with GPIO21, IRSL2 and IRSL0. ID1 is multiplexed
on pin 78 with IRS L1 and XD7 or pin 78, or on pin 157 with GPIO20
and IRSL1.
ID0 is multiplexed with GPIO37,IRRX2 and IRSL0.
See TABLE 1-2 for more information.
INDEX 97 FDC Input
Group 1
Index – This input signal indicates the beginning of an FDD track.
INIT 117 Parallel Port I/O
Group 13
Initialize – When this signal is active low, it causes the printer to be
initialized. This signal is in TRI-STATE after a 1 is loaded into the
corresponding control register bit.
For Input mode see bit 5 in Section 6.5.16.
An external 4.7 KΩ pull-up resistor should be employed.
IOCHRDY 32 ISA-Bus Output
Group 22
I/O Channel Ready – This is the I/O channel ready open drain output
signal. When IOCHRDY is driven low, the EPP extends the host cycle.
IRQ1
IRQ5-3
IRQ12-6
IRQ15,14
36
39-37
47-41
49,48
ISA-Bus I/O
Group 15
Interrupt Requests 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14 and 15 – IRQ
polarity and push-pull or open-drain output selection is software
configurable by the logical device mapped to the IRQ line.
Keyboard Controller (KBC) or Mouse interrupts can be configured by
the Interrupt Request Type Select 0 register (index 71h) as either
edge or level.
The internal SCI
1
signal may be routed to these pins.
IRRX2,1 79, 80 UART2 Input
Group 27
Infrared Reception 1 and 2 – Infrared serial input data. IRRX1
and/or IRRX2 may be routed to POR or ONCTL. The pins are
powered by V
CCH
.
IRRX1 is multiplexed with GPIO24.
IRRX2 is multiplexed with GPIO37,IRSL0 and ID0.
IRSL0
IRSL1
IRSL2
79 or 158
78 or 157
77 or 158
UART2 Output Infrared Control Signals 0, 1 and 2 – These signals control the
Infrared analog front end. The pins on which these signals are driven
is determined by the SuperI/O Configuration 2 register (index 22h).
See TABLE 1-2 for more information.
IRSL0 is multiplexed on pin 79 with GPIO37, IRRX2 and ID0, or on
pin 158 with GPIO21, IRSL2 and ID2.
IRSL1 is multiplexed on pin 78 with XD7 and ID1, or on pin 157 with
GPIO20 and ID1.
IRSL2 is multiplexed on pin 77 with XD6, SELCS and GPIO21, or on
pin 158 with GPIO21, IRSL0 and ID2.
Pins:
77, 78,79
Group 17
Pins:
157, 158
Group 10
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Page 21
Signal/Pin Connection and Description
SIGNAL/PIN DESCRIPTIONS
21
www.national.com
IRTX 81 UART2 Output
Group 19
Infrared Transmit – Infrared serial output data.
KBCLK 102 KBC I/O
Group 11
Keyboard Clock – This I/O pin transfers the keyboard clock between
the SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to the internal TO signal of the KBC.
KBDAT 103 KBC I/O
Group 11
Keyboard Data – This I/O pin transfers the keyboard data between
the SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to KBC’s P10.
LED 68 APC OUTPUT
Group 26
LED Control - Drives an externally connected LED, according to the
user selection (on, off or a 1 Hz blink). This open-drain output is
powered by V
CCH
, it is multiplexed with CSO and can sink 16 mA.
MCLK 104 KBC I/O
Group 11
Mouse Clock – This I/O pin transfers the mouse clock between the
SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to KBC’s T1.
MDAT 105 KBC I/O
Group 11
Mouse Data – This I/O pin transfers the mouse data between the
SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to KBC’s P11.
MR 51 ISA-Bus Input
Group 1
Master Reset – An active high MR input signal resets the controller
to the idle state, and resets all disk interface output signals to their
inactive states. MR also clears the DOR, DSR and CCR registers,
and resets the MODE command, CONFIGURE command, and LOCK
command parameters to their default values. MR does not affect the
SPECIFY command parameters. MR sets the configuration registers
to their selected default values.
MSEN1,0 83, 82 FDC Input
Group 4
Media Sense – These input pins are used for media sensing when bit
6 of the SuperI/O FDC Configuration register (at index F0h) is 1. See
TABLE 1-2 for more information.
Each pin has a 40 KΩ internal pull-up resistor.
MTR1,0 86, 85 FDC Output
Group 16
Motor Select 1,0 – These motor enable lines for drives 0 and 1 are
controlled by bits D7-4 of the Digital Output Register (DOR). They are
output signals that are active when they are low. They are encoded with
information to control four FDDs when bit 7 of the SuperI/O FDC
Configuration register is set See TABLE 1-2 for more information. See
DR1,0.
ONCTL 67 APC Output
Group 23
On/Off Control for the RTC’s Advanced Power Control (APC) –
This signal indicates to the main power supply to turn on power.
ONCTL is an open-drain output signal that is powered by V
CCH
.
P17,16
P12
108, 107
106
KBC I/O
Group 12
I/O Port – KBC quasi-bidirectional port for general purpose input and
output.
P12 may be routed internally (via APC) to
POR and/or SCI1.
P12 is multiplexed with
CS0.
P16 is multiplexed with GPIO25.
P21,20 110, 109 KBC I/O
Group 12
I/O Port – KBC open-drain signals for general purpose input and
output. These signals are controlled by KBC firmware.
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Page 22
Signal/Pin Connection and Description
22
SIGNAL/PIN DESCRIPTIONS
www.national.com
PD7-0 129-122 Parallel Por t I/O
Group 14
Parallel Port Data – These bidirectional signals transfer data to and
from the peripheral data bus and the appropriate parallel port data
register. These signals have a high current dr ive capability. See
Section 14.1 on page 232.
PE 115 Parallel Port Input
Group 2
Group 3
Paper End – This input signal is set high by the printer when it is out
of paper. This pin has an internal weak pull-up or pull-down resistor.
PME2,1 154,155 APC Input
Group 28
Power Management Event 1 and 2 - These signals indicate that a
power Management Event has occurred. They may be routed to
POR,
SCI
1
or ONCTL. Event characteristics (low/high, rise/fall) are software
configurable. The pins are powered by V
CCH
.
PME1 is multiplexed with GPIO16.
PME2 is multiplexed with GPIO15.
POR 159 APC Output
Group 21
Power Off Request – This signal is activated by various events,
including the APC Switch Off event (regardless of the fail-safe delay).
Selection of edge or level for
POR is via the APCR1 register of the
APC. Selection of an output buffer is via GPIO22 output buffer control
bits (in the Port 2 Output Type and Port 2 Pull-up Control registers
described in TABLE 9-2). See Section 4.3.
This signal is multiplexed with GPIO22
RD 33 ISA-Bus Input
Group 1
I/O Read – An active low RD input signal indicates that the
microprocessor has read data.
RDATA 95 FDC Input
Group 1
Read Data – This input signal holds raw serial data read from the
Floppy Disk Drive (FDD).
RI2,1 145, 135 UART1, APC Input
Group 7
Ring Indicators (Modem) – When low, this signal indicates that a
telephone ring signal has been received by the modem.
When enabled, a high to low transition on
RI1 or RI2 activates the
ONCTL pin. The RI1 and RI2 pins have schmitt-trigger input buffers.
RI2 is multiplexed with GPIO33.
RING 69 or 160 APC Input
Group 7
Ring Indicator (APC) – Detection of an active low RING pulse or
pulse train activates the
ONCTL signal. The APC’s APCR2 register
determines which pin the
RING signal uses. The pins have a schmitt-
trigger input buffer.
RING is multiplexed on pin 69 with XDCS and on pin 160 with
GPIO23.
RTS2,1 146, 136 UART1,
UART 2
Output
Group 17
Request to Send – When low, these output signals indicate to the
modem or other data transfer device that the corresponding UART1
or UART2 is ready to exchange data.
A Master Reset (MR) sets
RTS to inactive high. Loopback operation
holds it inactive.
RTS2 is multiplexed with GPIO34. RTS1 is multiplexed with BADDR1.
SELCS 77 Configuration Input
Group 4
Select CSOUT – During reset, this signal is sampled into bit 1 of the
SuperI/O Configuration 1 register (index 21h).
A 40 KΩ internal pull-up resistor (or a 10 KΩ external pull-down
resistor for National Semiconductor testing) controls this pin during
reset. Do not pull this signal low during reset.
This signal is multiplexed with GPIO21, IRSL2 and XD6.
SIN2,1 147, 137 UART1,
UART 2
Input
Group 1
Serial Input – This input signal receives composite serial data from
the communications link (peripheral device, modem or other data
transfer device.)
SIN2 is multiplexed with GPIO35.
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Page 23
Signal/Pin Connection and Description
SIGNAL/PIN DESCRIPTIONS
23
www.national.com
SLCT 114 Parallel Por t Input
Group 2
Select – This input signal is set active high by the printer when the
printer is selected. This pin is internally connected to a nominal 25 KΩ
pull-down resistor.
SLIN 118 Parallel Port I/O
Group 13
Select Input – When this signal is active low it selects the printer.
This signal is in TRI-STATE after a 0 is loaded into the corresponding
control register bit. Use an external 4.7 KΩ pull-up resistor.
For Input mode see bit 5, described in Section 6.5.16.
This signal is multiplexed with
ASTRB.
SOUT2,1 148, 138 UART1,
UART 2
Output
Group 17
Serial Output – This output signal sends composite serial data to the
communications link (peripheral device, modem or other data transfer
device).
The SOUT2,1 signals are set active high after a Master Reset (MR).
SOUT2 is multiplexed with GPIO36.
SOUT1 is multiplexed with CFG0.
STB 112 Parallel Port I/O
Group 13
Data Strobe – This output signal indicates to the printer that valid
data is available at the printer port.
This signal is in TRI-STATE after a 0 is loaded into the corresponding
control register bit.
An external 4.7 KΩ pull-up resistor should be employed.
For Input mode see bit 5, described in Section 6.5.16.
This signal is multiplexed with
WRITE.
STEP 91 FDC Output
Group 16
Step – This output signal issues pulses to the disk drive at a software
programmable rate to move the head during a seek operation.
SWITCH 66 APC Input
Group 7
Switch On/Off – A physical momentary switch attached to this pin
indicates a user request (to the APC) to switch the power on or off.
(See “The SWITCH Input Signal” on page 67).
The pin has an internal pull-up of 1 MΩ (nominal), a schmitt-trigger
input buffer and debounce protection of at least 16 msec.
TC 35 ISA-Bus Input
Group 1
DMA Terminal Count – The DMA controller issues TC to indicate the
termination of a DMA transfer. TC is accepted only when a
DACK
signal is active.
TC is active high in PC-AT mode, and active low in PS/2 mode.
TRK0 96 FDC Input
Group 1
Track 0 – This input signal indicates to the controller that the head of
the selected floppy disk drive is at track 0.
V
BAT
64 RTC and
APC
Input Battery Power Supply – Power signal from the battery to the Real-
Time Clock (RTC) or for Advanced Power Control (APC) when V
CCH
is less than V
BAT
(by at least 0.5V). V
BAT
includes a UL protection
resistor.
V
CCH
65 RTC and
APC
Input VCC Help Power Supply – This signal provides power to the RTC or
APC when V
CCH
is higher than V
BAT
(by at least 0.5V).
V
DD
1, 24, 61,
100, 121,
140
Power
Supply
Input Main 5 V Power Supply – This signal is the 5 V supply voltage for
the digital circuitry.
V
SS
2, 11, 25,
40, 60,
101, 120,
130, 139
Power
Supply
Output Ground – This signal provides the ground for the digital circuitry.
WAIT 111 Parallel Port Input
Group 2
Wait – In EPP mode, the parallel port device uses this signal to
extend its access cycle.
WAIT is active low. This signal is multiplexed
with BUSY. See TABLE 6-12 on page 160 for more information.
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Page 24
Signal/Pin Connection and Description
24
SIGNAL/PIN DESCRIPTIONS
www.national.com
1. SCI is an internal signal used to send ACPI-relevant notifications to the host operating system.
WDATA 89 FDC Output
Group 16
Write Data (FDC) – This output signal holds the write
precompensated serial data that is written to the selected floppy disk
drive. Precompensation is software selectable.
WDO 156 Power Man-
agement
Output
Group 10
WATCHDOG Out – This output pin becomes low when a
WATCHDOG time-out occurs. See Section 10.1.2 on page 218.This
pin is configured by bit 6 of the SuperI/O Configuration Register 2.
This signal is multiplexed with GPIO17.
WGATE 93 FDC Output
Group 16
Write Gate (FDC) – This output signal enables the write circuitry of
the selected disk drive.
WGATE is designed to prevent glitches during
power up and power down. This prevents writing to the disk when
power is cycled.
WP 98 FDC Input
Group 1
Write Protected – This input signal indicates that the disk in the
selected drive is write protected.
WR 34 ISA-Bus Input
Group 1
I/O Write – WR is an active low input signal that indicates a write
operation from the microprocessor to the controller.
WRITE 112 Parallel Por t Output
Group 23
Write Strobe – In EPP mode, this active low signal is a write strobe.
This signal is multiplexed with
STB. See TABLE 6-12 for more
information.
X1 50 Clock Input
Group 6
Clock In – A TTL or CMOS compatible 14.31818MHz, 24 MHz or 48
MHz clock. When this pin is fed by the 14.31818MHz clock, the chip
must be configured to work with the on-chip clock multiplier.See
Chapter 12 on page 230.
X1C 62 RTC Input Crystal 1 Slow – Input signal to the internal Real-Time Clock (RTC)
crystal oscillator amplifier. Clock source is set by CFG0 during reset.
X2C 63 RTC Output Crystal 2 Slow – Output signal from the internal Real-Time Clock
(RTC) crystal oscillator amplifier.
XD7,6,
XD1,0
78, 77
72, 71
X-Bus I/O
Group 9
X-Bus Data – These bidirectional signals hold the data in the X Data
Buffer (XDB).
XD7 is multiplexed with IRSL1 and ID1.
XD6 is multiplexed with IRSL2, SELCS and GPIO21.
XD5-2 are multiplexed with GPIO27-24, respectively.
XD1 is multiplexed with
CS2.
XD0 is multiplexed with
CS1/CSOUT-NSC-Test
See TABLE 1-2 on page 25.
XD5-2 76-73 X-Bus I/O
Group 10
XDCS 69 X-Bus Input
Group 7
X-Bus Data Buffer (XDB) Chip Select – This signal enables and
disables the bidirectional XD7-0 data buffer signals.
This signal is multiplexed with
RING.
XDRD 70 X-Bus Input
Group 1
X-Bus Data Buffer (XDB) Read Command – This signal controls the
direction of the bidirectional XD7-0 data buffer signals.
This signal is multiplexed with ID3.
ZWS 31 ISA-Bus Output
Group 22
Zero Wait State – When this open-drain output signal is activated
(driven low), it indicates that the access time can be shortened, i.e.,
zero wait states.
ZWS is never activated (driven low) on access to SuperI/O chip
configuration registers (including during the Isolation state) or on
access to the parallel port in SPP or EPP 1.9 mode.
ZWS is always activated (driven low) on access to the parallel port in
ECP mode.
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Page 25
Signal/Pin Connection and Description
SIGNAL/PIN DESCRIPTIONS
25
www.national.com
TABLE 1-3. UART2/GPIO Port 3 Pin Designation
TABLE 1-4. APC/Power Management or GPIO/Chip Select Pin Designation
1. Unselected (XDB or alternate function) input signals are internally blocked high.
TABLE 1-2. Multiplexed X-Bus Data Buffer (XDB) Pins
Pin
X-Bus Data Buffer (XDB)
1
Bit 4 of SuperI/O Configuration
Register 1 = 1
I/O
Alternate Function
a
Bit 4 of SuperI/O Configuration 1
Register = 0
I/O
69
XDCS Input RING Input
70
XDRD Input ID3
71 XD0 I/O
CS1/CSOUT-NSC-Test Output
72 XD1 I/O
CS2 Output
73 XD2 I/O GPIO24 I/O
73 XD3 I/O GPIO25 I/O
75 XD4 I/O GPIO26 I/O
76 XD5 I/O GPIO27 I/O
77 XD6/SELCS I/O GPIO21/IRSL2/SELCS I/O
78 XD7 I/O IRSL1/ID1 Output
Pin
UAR T 2
Bit 3 of SuperI/O Configuration
Register 1 = 1
I/O
General Purpose I/O port 3
Bit 3 of SuperI/O Configuration
Register 1 = 0
I/O
141
CTS2 Input GPIO30 I/O
142
DCD2 Input GPIO31 I/O
143
DSR2 Input GPIO32 I/O
146
RTS2 Output GPIO34 I/O
147 SIN2 Input GPIO35 I/O
148 SOUT2 Output GPIO36 I/O
Pin APC, Power Management I/O General Purpose I/O, Chip Select I/O
154 PME2 Input GPIO15 I/O
155 PME1 Input GPIO16 I/O
156
WDO Output GPIO17 I/O
159
POR Output GPIO22 I/O
160
RING Input GPIO23 I/O
68 LED Output
CS0 Output
Page 26
Signal/Pin Connection and Description
26
SIGNAL/PIN DESCRIPTIONS
www.national.com
TABLE 1-5. Infrared/KBC or GPIO/Chip-Select Pin Designation
TABLE 1-6. Pins with a Strap Function During Reset
Pin Infrared, KBC, UART2 I/O General Purpose I/O, Chip Select I/O
157 IRSL1/ID1 I/O GPIO20 I/O
158 IRSL2/IRSL0/ID2 I/O GPIO21 I/O
80 IRRX1 Input GPIO24 I/O
107 P16 I/O GPIO25 I/O
145
RI2 Input GPIO33 I/O
79 IRRX2/IRSL0/ID0 I/O GPIO37 I/O
106 P12 I/O
CS0 Output
Strap Function Pin No. Symbols
BADDR1,0 134
DTR1/BADDR0/BOUT1
136
RTS1/BADDR1
CFG1,0 138 SOUT1/CFG0
144
DTR2/CFG1
SELCS 77 GPIO21/IRSL2/XD6/SELCS
Page 27
Configuration
27
2.0 Configuration
www.national.com
2.0 Configuration
The PC87317VUL is partially configured by hardware, during reset. The configuration can also be changed by software, by changing the values of the configuration registers.
The configuration registers are accessed using an Index
register and a Data register. During reset, hardware strapping options define the addresses of the configuration registers. See Section 2.1.2 "The Index and Data Register
Pair".
After the Index and Data register pair have determined the
addresses of the configuration registers, the addresses of
the Index and Data registers can be changed within the ISA
I/O address space, and a 16-bit programmable register controls references to their addresses and to the addresses of
the other registers.
This chapter describes the hardware and software configuration processes. For each, it describes configuration of the
Index and Data register pair first. See Sections 2.1 "HARDWARE CONFIGURATION" and 2.2 "SOFTWARE CONFIGURATION" on page 28.
Section 2.3 "THE CONFIGURATION REGISTERS" on
page 29 presents an overview of the configuration registers
of the PC87317VUL and describes each in detail.
2.1 HARDWARE CONFIGURATION
The PC87317VUL supports two Plug and Play (PnP) configuration modes that determine the status of register addresses upon wake up from a hardware reset, Full Plug and
Play ISA mode and Plug and Play Motherboard mode.
2.1.1 Wake Up Options
During reset, strapping options on the BADDR0 and
BADDR1 pins determine one of the following modes.
●
Full Plug and Play ISA mode – System wakes up in
Wait for Key state.
Index and Data register addresses are as defined by Microsoft and Intel in the
“Plug and Play ISA Specification,
Version 1.0a, May 5, 1994.”
●
Plug and Play Motherboard mode – system wakes up
in Config state.
The BIOS configures the PC87317VUL. Index and Data
register addresses are different from the addresses of
the Plug and Play (PnP) Index and Data registers. Configuration registers can be accessed as if the serial isolation procedure had already been done, and the
PC87317VUL is selected.
The BIOS may switch the addresses of the Index and
Data registers to the PnP ISA addresses of the Index
and Data registers, by using software to modify the base
address bits, as shown in Section 2.4.4 "SuperI/O Configuration 2 Register (SIOC2)" on page 38.
2.1.2 The Index and Data Register Pair
During reset, a hardware strapping option on the BADDR0
and BADDR1 pins defines an address for the Index and
Data Register pair. This prevents contention between the
registers for I/O address space.
TABLE 2-1 "Base Addresses" shows the base addresses
for the Index and Data registers that hardware sets for each
combination of values of the Base Address strap pins
(BADDR0 and BADDR1). You can access and change the
content of the configuration registers at any time, as long as
the base addresses of the Index and Data registers are defined.
When BADDR1 is low (0), the Plug and Play (PnP) protocol
defines the addresses of the Index and Data register, and
the system wakes up from reset in the Wait for Key state.
When BADDR1 is high (1), the addresses of the Index and
Data register are according to TABLE 2-1 "Base Addresses", and the system wakes up from reset in the Config state.
This configures the PC87317VUL with default values, automatically, without software intervention. After reset, use
software as described in Section 2.2 "SOFTWARE CONFIGURATION" on page 28 to modify the selected base address of the Index and Data register pair, and the defaults
for configuration registers.
The Plug and Play soft reset has no effect on the logical devices, except for the effect of the Activate registers (index
30h) in each logical device.
The PC87317VUL can wake up with the FDC, the KBC and
the RTC either active (enabled) or inactive (disabled). The
other logical devices and the internal on-chip clock multiplier wake up inactive (disabled).
TABLE 2-1. Base Addresses
BADDR1 BADDR0
Address
Configuration Type
Index Register Data Register
0x
0279h
Write Only
Write: 0A79h
Read: RD_DATA Port
Full PnP ISA Mode
Wake up in Wait for Key state
1 0 015Ch Read/Write 015Dh Read/Write
PnP Motherboard Mode
Wake up in Config state
1 1 002Eh Read/Write 002Fh Read/Write
PnP Motherboard Mode
Wake up in Config state
Page 28
Configuration
28
SOFTWARE CONFIGURATION
www.national.com
2.1.3 The Strap Pins
TABLE 2-2. The Strap Pins
1. SELCS = 0 and CFG1 = 1 is an illegal strap option.
2.2 SOFTWARE CONFIGURATION
2.2.1 Accessing the Configuration Registers
Only two system I/O addresses are required to access any
of the configuration registers. The Index and Data register
pair is used to access registers for all read and write operations.
In a write operation, the target configuration register is identified, based on a value that is loaded into the Index register.
Then, the data to be written into the configuration register is
transferred via the Data register.
Similarly, for a read operation, first the source configuration
register is identified, based on a value that is loaded into the
Index register. Then, the data to be read is transferred via
the Data register.
Reading the Index register returns the last value loaded into
the Index register. Reading the Data register returns the
data in the configuration register pointed to by the Index
register.
If, during reset, the Base Address 1 (BADDR1) signal is low
(0), the Index and Data registers are not accessible immediately after reset. As a result, all configuration registers of
the PC87317VUL are also not accessible at this time. To
access these registers, you must apply the Plug and Play
(PnP) ISA protocol.
If during reset, the Base Address 1 (BADDR1) signal is high
(1), all configuration registers are accessible immediately
after reset.
It is up to the configuration software to guarantee no conflicts between the registers of the active (enabled) logical
devices, between IRQ signals and between DMA channels.
If conflicts of this type occur, the results are unpredictable.
To maintain compatibility with other SuperI/O‘s, the value of
reserved bits may not be altered. Use read-modify-write.
2.2.2 Address Decoding
In full Plug and Play mode, the addresses of the Index and
Data registers that access the configuration registers are
decoded using pins A11-0, according to the ISA Plug and
Play specification.
In Plug and Play Motherboard mode, the addresses of the
Index and Data registers that access the configuration registers are decoded using pins A15-1. Pin A0 distinguishes
between these two registers.
KBC and mouse register addresses are decoded using pins
A1,0 and A15-3. Pin A2 distinguishes between the device
registers.
RTC/APC and Power Management (PM) register addresses are decoded using pins A15-1.
FDC, UART, and GPIO register addresses are decoded using pins A15-3.
Parallel Port (PP) modes determine which pins are used for
register addresses. In SPP mode, 14 pins are used to decode Parallel Port (PP) base addresses. In ECP and EPP
modes, 13 address pins are used. TABLE 2-3 "Address
Pins Used for Parallel Port" shows which address pins are
used in each mode.
TABLE 2-3. Address Pins Used for Parallel Port
Pin Reset Configuration Affected
CFG0 0: FDC, KBC and RTC wake up inactiv e , cloc k source is 32.768 KHz
with on-chip clock multiplier disabled.
1: FDC, KBC and RTC wake up active, clock source is 48 MHz fed
via X1 pin.
Bit 0 of Activate registers (index
30h) of logical devices 0, 2 and 3
and bit 0 of PMC2 register of Power
Management (logical device 8).
CFG1
1
0: No X-Bus Data Buffer. (See XDB pins multiplexing in TABLE 1-2.)
1: X-Bus Data Buffer (XDB) enabled.
Bit 4 of SuperI/O Configuration 1
(SIOC1) register (index 21h).
BADDR1,0 00: Full PnP ISA, Wake in Wait For Key state. Index PnP ISA.
01: Full PnP ISA, Wake in Wait For Key state. Index PnP ISA.
10: PnP Motherboard, Wake in Config state. Index 015Ch.
11: PnP Motherboard, Wake in Config state. Index 002Eh.
Bits 1 and 0 of SuperI/O
Configuration 2 (SIOC2) register
(index 22h)
SELCS
a
0: CSOUT-NSC-test on pin 71.
1:
CS1 or XD0 on pin 71 (according to CFG1).
Bit 1 of SuperI/O Configuration 1
(SIOC1) register (index 21h).
PP Mode
Pins Used to
Decode Base
Address
Pins Used to
Distinguish Registers
SPP A15-2 A1,0
ECP A9-2 and A15-11 A1,0 and A10
EPP A15-3 A2-0
Page 29
Configuration
THE CONFIGURATION REGISTERS
29
www.national.com
TABLE 2-4. Parallel Port Address Range Allocation
1. The SuperI/O processor does not decode the Parallel Port outside this range.
2.3 THE CONFIGURATION REGISTERS
The configuration registers control the setup of the
PC87317VUL. Their major functions are to:
●
Identify the chip
●
Enable major functions (such as, the Keyboard Controller (KBC) for the keyboard and the mouse, the RealTime Clock (RTC), including Advanced Power Control
(APC), the Floppy Disc Controller (FDC), UARTs, parallel and general purpose ports, power management and
pin functionality)
●
Define the I/O addresses of these functions
●
Define the status of these functions upon reset
Section 2.3.2 "Configuration Register Summary" on page
33 summarizes information for each register of each function. In addition, the following non-standard, or card control,
registers are described in detail, in Section 2.4 "CARD
CONTROL REGISTERS" on page 37.
●
The Card Control Registers
— SID Register
— SRID Register (only in the PC97317).
— SuperI/O Configuration 1 Register (SIOC1)
— SuperI/O Configuration 2 Register (SIOC2)
— Programmable Chip Select Configuration Index
Register
— Programmable Chip Select Configuration Data Reg-
ister
●
KBC Configuration Register (Logical Device 0)
— SuperI/O KBC Configuration Register
●
FDC Configuration Registers (Logical Device 3)
— SuperI/O FDC Configuration Register
— Drive ID Register
●
Parallel Por t Configuration Register (Logical Device 4)
— SuperI/O Parallel Port Configuration Register
●
UART2 and Infrared Configuration Register (Logical
Device 5)
— SuperI/O UART2 Configuration Register
●
UART1 Configuration Register (Logical Device 6)
— SuperI/O UART1 Configuration Register
●
Programmable Chip Select Configuration Registers
—
CS0 Base Address MSB Register
—
CS0 Base Address LSB Register
—
CS0 Configuration Register
—
CS1 Base Address MSB Register
—
CS1 Base Address LSB Register
—
CS1 Configuration Register
—
CS2 Base Address MSB Register
—
CS2 Base Address LSB Register
—
CS2 Configuration Register
Parallel Port Mode
SuperI/O Parallel Port
Configuration Register Bits
7 6 5 4
Decoded Range
1
SPP 0 0 x x Three registers, from base to base + 02h
EPP (Non ECP Mode 4) 0 1 x x Eight registers, from base to base + 07h
ECP, No Mode 4,
No Inter nal Configuration
1 0 0 0
Six registers, from base to base + 02h and
from base + 400h to base + 402h
ECP with Mode 4,
No Inter nal Configuration
1 1 1 0
11 registers, from base to base + 07h and
from base + 400h to base + 402h
ECP with Mode 4,
Configuration within Parallel Port
1 0 0 1
or
1 1 1 1
16 registers, from base to base + 07h and
from base + 400h to base + 407h
Page 30
Configuration
30
THE CONFIGURATION REGISTERS
www.national.com
2.3.1 Standard Plug and Play (PnP) Register Definitions
TABLES 2-5 through 2-10 describe the standard Plug and
Play registers. For more detailed information on these
registers, refer the
“Plug and Play ISA Specification, Ver-
sion 1.0a, May 5, 1994”.
TABLE 2-5. Plug and Play (PnP) Standard Control Registers
Index Name Definition
00h Set RD_DATA Port Writing to this location modifies the address of the port used for reading from the
Plug and Play ISA cards. Data bits 7-0 are loaded into I/O read port address bits
9-2.
Reads from this register are ignored. Bits1 and 0 are fixed at the value 11.
01h Serial Isolation Reading this register causes a Plug and Play card in the Isolation state to compare
one bit of the ID of the board. This register is read only.
02h Config Control This register is write-only. The values are not sticky, that is, hardware automatically
clears the bits and there is no need for software to do so.
Bit 0 - Reset
Writing this bit resets all logical devices and restores the contents of
configuration registers to their power-up (default) values.
In addition, all the logical devices of the card enter their default state and the
CSN is preserved.
Bit 1 - Return to the Wait for Key state.
Writing this bit puts all cards in the Wait for Key state, with all CSNs preserved
and logical devices not affected.
Bit 2 - Reset CSN to 0.
Writing this bit causes every card to reset its CSN to zero.
03h Wake[CSN] A write to this por t causes all cards that have a CSN that matches the write data
in bits 7-0 to go from the Sleep state to either the Isolation state, if the write data
for this command is zero, or the Config state, if the write data is not zero. It also
resets the pointer to the byte-serial device.
This register is write-only.
04h Resource Data This address holds the next byte of resource information. The Status register must
be polled until bit 0 of this register is set to 1 before this register can be read.
This register is read-only.
005 Status When bit 0 of this register is set to 1, the next data byte is available for reading
from the Resource Data register.
This register is read-only.
06h Card Select
Number (CSN)
Writing to this port assigns a CSN to a card. The CSN is a value uniquely assigned
to each ISA card after the serial identification process so that each card may be
individually selected during a Wake[CSN] command.
This register is read/write.
07h Logical Device
Number
This register selects the current logical device. All reads and writes of memory, I/O,
interrupt and DMA configuration information access the registers of the logical
device written here. In addition, the I/O Range Check and Activate commands
operate only on the selected logical device.
This register is read/write. If a card has only 1 logical device, this location should
be a read-only value of 00h.
20h - 2Fh Card Level,
Vendor Defined
Vendor defined registers.
Page 31
Configuration
THE CONFIGURATION REGISTERS
31
www.national.com
TABLE 2-6. Plug and Play (PnP) Logical Device Control Registers
TABLE 2-7. Plug and Play (PnP) I/O Space Configuration Registers
Index Name Definition
0030h Activate For each logical device there is one Activate register that controls whether or not the
logical device is active on the ISA bus.
This is a read/write register.
Before a logical device is activated, I/O Range Check must be disabled.
Bit 0 - Logical Device Activation Control
0: Do not activate the logical device.
1: Activate the logical device.
Bits 7-1 - Reserved
These bits are reserved and must return 0 on reads.
0031h I/O Range Check This register is used to perform a conflict check on the I/O port range programmed
for use by a logical device.
This register is read/write.
Bit 0 - I/O Range Check control
0: The logical device drives 00AAh.
1: The logical device responds to I/O reads of the logical device's assigned I/O
range with a 0055h when I/O Range Check is enabled.
Bit 1 - Enable I/O Range Check
0: I/O Range Check is disabled.
1: I/O Range Check is enabled. (I/O Range Check is valid only when the logical
device is inactive).
Bits 7-2 - Reserved
These bits are reserved and must return 0 on reads.
Index Name Definition
60h I/O Port Base
Address Bits (15-8)
Descriptor 0
Read/write value indicating the selected I/O lower limit address bits 15-8 for I/O
descriptor 0.
61h I/O Port Base
Address Bits (7-0)
Descriptor 0
Read/write value indicating the selected I/O lower limit address bits 7-0 for I/O
descriptor 0.
62h I/O Port Base
Address Bits (15-8)
Descriptor 1
Read/write value indicating the selected I/O lower limit address bits 15-8 for I/O
descriptor 1.
63h I/O Port Base
Address Bits (7-0)
Descriptor 1
Read/write value indicating the selected I/O lower limit address bits 7-0 for I/O
descriptor 1.
Page 32
Configuration
32
THE CONFIGURATION REGISTERS
www.national.com
TABLE 2-8. Plug and Play (PnP) Interrupt Configuration Registers
TABLE 2-9. Plug and Play (PnP) DMA Configuration Registers
TABLE 2-10. Plug and Play (PnP) Logical Device Configuration Registers
Index Name Definition
70h Interrupt Request
Level Select 0
Read/write value indicating selected interrupt level.
Bits3-0 select the interrupt level used for interrupt 0. A value of 1 selects IRQL 1, a value
of 15 selects IRQL 15. IRQL 0 is not a valid interrupt selection and (represents no
interrupt selection.
71h Interrupt Request
Type Select 0
Read/write value that indicates the type and level of the interrupt request level selected in
the previous register.
If a card supports only one type of interrupt, this register may be read-only.
Bit 0 - Type of the interrupt request selected in the previous register.
0: Edge
1: Level
Bit1 - Level of the interrupt request selected in the previous register. (See also Section
13.1 on page 231).
0: Low polarity. (Implies open-drain output with strong pull-up for a short time, followed
by weak pull-up).
1: High polarity. (Implies push-pull output).
Index Name Definition
74h DMA Channel
Select 0
Read/write value indicating selected DMA channel for DMA 0.
Bits 2-0 select the DMA channel for DMA 0. A value of 0 selects DMA channel 0; a
value of 7 selects DMA channel 7.
Selecting DMA channel 4, the cascade channel, indicates that no DMA channel is
active.
75h DMA Channel
Select 1
Read/write value indicating selected DMA channel for DMA 1
Bits 2-0 select the DMA channel for DMA 1. A value of 0 selects DMA channel 0; a
value of 7 selects DMA channel 7.
Selecting DMA channel 4, the cascade channel, indicates that no DMA channel is
active.
Index Name Definition
F0h-FEh Logical Device
Configuration Vendor
Defined
Vendor defined.
Page 33
Configuration
THE CONFIGURATION REGISTERS
33
www.national.com
2.3.2 Configuration Register Summary
The tables in this section specify the Index, type
(read/write), reset values and configuration register or action that controls each register associated with each function.
When the reset value is not fixed, the table indicates what
controls the value or points to another section that provides
this information.
Soft Reset is related to a Reset executed by utilizing the Reset Bit (Bit 0) of the Config Control Register. (See TABLE
2-5 "Plug and Play (PnP) Standard Control Registers" on
page 30.
TABLE 2-11. Card Control Registers
TABLE 2-12. KBC Configuration Registers for Keyboard - Logical Device 0
Index Type Hard Reset Soft Reset Configuration Register or Action
00h W 00h PnP ISA Set RD_DATA Port.
01h R Serial Isolation.
02h W PnP ISA PnP ISA Configuration Control.
03h W 00h PnP ISA Wake[CSN].
04h R Resource Data.
05h R Status.
06h R/W 00h PnP ISA Card Select Number (CSN).
07h R/W 00h PnP ISA Logical Device Number.
20h R D0h D0h SID Register.
21h R/W See Section 2.4.3 on page 37. No Effect SuperI/O Configuration 1 Register (SIOC1).
22h R/W See Section 2.4.4 on page 38. No Effect SuperI/O Configuration 2 Register (SIOC2).
23h R/W See Section 2.4.5 on page 38. No Effect Programmable Chip Select Configuration Index Register.
24h R/W See Section 2.4.6 on page 39. No Effect Programmable Chip Select Configuration Data Register.
27h R xx xx SRID Register (in PC97317 only).
Index R/W Hard Reset Soft Reset Configuration Register or Action
30h R/W 00h or 01h
See CFG0 in Section.
00h or 01h
See CFG0 in Section
2.1.3.
Activate.
See also FER1 of power management device
(logical device 8).
31h R/W 00h 00h I/O Range Check.
60h R/W 00h 00h Base Address MSB Register.
61h R/W 60h 60h Base Address LSB Register.
Bit 2 (for A2) is read only, 0.
62h R/W 00h 00h Command Base Address MSB Register.
63h R/W 64h 64h Command Base Address LSB.
Bit 2 (for A2) is read only,1.
70h R/W 01h 01h KBC Interr upt (KBC IRQ1 pin) Select.
71h RW 02h 02h KBC Interrupt Type.
Bits 1,0 are read/write; others are read only.
74h R 04h 04h Report no DMA assignment.
75h R 04h 04h Report no DMA assignment.
F0h R/W See Section 2.5.1 on page 40. No Effect SuperI/O KBC Configuration Register.
Page 34
Configuration
34
THE CONFIGURATION REGISTERS
www.national.com
TABLE 2-13. KBC Configuration Registers for Mouse - Logical Device 1
TABLE 2-14. RTC and APC Configuration Registers - Logical Device 2
TABLE 2-15. FDC Configuration Registers - Logical Device 3
Index R/W Hard Reset Soft Reset Configuration Register or Action
30h R/W 00h 00h Activate.
When mouse of the KBC mouse is inactive, the IRQ selected by the Mouse
Interrupt Select register (index 70h) is not asserted.
This register has no effect on host KBC commands handling the PS/2 mouse.
70h R/W 0Ch 0Ch Mouse Interrupt (KBC IRQ12 pin) Select.
71h R/W 02h 02h Mouse Interrupt Type.
Bits 1,0 are read/write; other bits are read only.
74h R 04h 04h Repor t no DMA assignment.
75h R 04h 04h Repor t no DMA assignment.
Index R/W Hard Reset Soft Reset Configuration Register or Action
30h R/W 00h or 01h
See CFG0 in
Section 2.1.3.
00h or 01h
See CFG0 in
Section 2.1.3.
Activate.
The APC of the RTC is not affected by bit 0.
See also FER1 of logical device 8.
31h R/W 00h 00h I/O Range Check.
60h R/W 00h 00h Base Address MSB Register.
61h R/W 70h 70h Base Address LSB Register.
Bit 0 (for A0) is read only, 0.
70h R/W 08h 08h Interrupt Select.
71h R/W 00h 00h Interrupt Type.
Bit 1 is read/write, other bits are read only.
74h R 04h 04h Report no DMA assignment.
75h R 04h 04h Report no DMA assignment.
Index R/W Hard Reset Soft Reset Configuration Register or Action
30h R/W 00h or 01h
See CFG0 in Section 2.1.3.
00h or 01h
See CFG0 in
Section 2.1.3.
Activate.
See also FER1 of logical device 8.
31h R/W 00h 00h I/O Range Check.
60h R/W 03h 03h Base Address MSB Register.
61h R/W F2h F2h Base Address LSB Register.
Bits 2 and 0 (for A2 and A0) are read only, 0,0.
70h R/W 06h 06h Interrupt Select.
71h R/W 03h 03h Interrupt Type.
Bit 1 is read/write; other bits are read only.
74h R/W 02h 02h DMA Channel Select.
75h R 04h 04h Report no DMA assignment.
F0h R/W See Section 2.6.1 on page 40. No Effect SuperI/O FDC Configuration Register.
F1h R/W See Section 2.6.2 on page 41. No Effect Drive ID Register.
Page 35
Configuration
THE CONFIGURATION REGISTERS
35
www.national.com
TABLE 2-16. Parallel Port Configuration Registers - Logical Device 4
TABLE 2-17. UART2 and Infrared Configuration Registers - Logical Device 5
Index R/W Hard Reset Soft Reset Configuration Register or Action
30h R/W 00h 00h Activate.
See also FER1 of the power management device (logical
device 8).
31h R/W 00h 00h I/O Range Check.
60h R/W 02h 02h Base Address MSB register.
Bits 7-2 (for A15-10) are read only, 000000b.
61h R/W 78h 78h Base Address LSB register.
Bits 1,0 (for A1,0) are read only, 00b.
See Section 2.2.2.
70h R/W 07h 07h Interrupt Select.
71h R/W 00h 00h Interrupt Type.
Bit 0 is read only. It reflects the interr upt type dictated by
the Parallel Por t operation mode and configured by the
SuperI/O Parallel Por t Configuration register. This bit is
set to 1 (level interrupt) in Extended Mode and cleared
(edge interrupt) in all other modes.
Bit 1 is a read/write bit.
Bits 7-2 are read only.
74h R/W 04h 04h DMA Channel Select.
75h R 04h 04h Report no DMA assignment.
F0h R/W See Section 2.7 on page 41 No Effect SuperI/O Parallel Port Configuration register.
Index R/W Hard Reset Soft Reset Configuration Register or Action
30h R/W 00h 00 Activate.
See also FER1 of the power management device
(logical device 8).
31h R/W 00h 00h I/O Range Check.
60h R/W 02h 02h Base Address MSB register.
61h R/W F8h F8h Base Address LSB register.
Bit 2-0 (for A2-0) are read only, 000b.
70h R/W 03h 03h Interrupt Select.
71h R/W 03h 03h Interrupt Type.
Bit 1 is R/W; other bits are read only.
74h R/W 04h 04h DMA Channel Select 0 (RX_DMA).
75h R/W 04h 04h DMA Channel Select 1 (TX_DMA).
F0h R/W See Section 2.8 on page 42 No Effect SuperI/O UART2 Configuration register.
Page 36
Configuration
36
THE CONFIGURATION REGISTERS
www.national.com
TABLE 2-18. UART1 Configuration Registers - Logical Device 6
TABLE 2-19. GPIO Ports Configuration Registers - Logical Device 7
TABLE 2-20. Power Management Configuration Registers - Logical Device 8
Index R/W Hard Reset Soft Reset Configuration Register or Action
30h R/W 00h 00h Activate.
See also FER1 of the power management device
(logical device 8).
31h R/W 00h 00h I/O Range Check.
60h R/W 03h 03h Base Address MSB Register.
61h R/W F8h F8h Base Address LSB Register.
Bits 2-0 (for A2-0) are read only as 000b.
70h R/W 04h 04h Interrupt Select.
71h R/W 03h 03h Interrupt Type.
Bit 1 is read/write. Other bits are read only.
74h R 04h 04h Report no DMA Assignment.
75h R 04h 04h Report no DMA Assignment.
F0h R/W See Section 2.9.1 on page 42 No Effect SuperI/O UART 1 Configuration register.
Index R/W Hard Reset Soft Reset Configuration Register or Action
30h R/W 00h 00h Activate.
See also FER2 of the power management device (logical device 8).
31h R/W 00h 00h I/O Range Check.
60h R/W 00h 00h Base Address MSB Register.
61h R/W 00h 00h Base Address LSB Register.
Bit 2-0 (for A2-0) are read only: 000.
74h R 04h 04h Repor t no DMA assignment.
75h R 04h 04h Repor t no DMA assignment.
Index R/W Hard Reset Soft Reset Configuration Register or Action
30h R/W 00 00 Activate.
When bit 0 is cleared, the registers of this logical device are not
accessible. The registers are maintained.
31h R/W 00h 00h I/O Range Check.
60h R/W 00h 00h Base Address Most Significant Byte.
61h R/W 00h 00h Base Address LSB Register.
Bit 0 (for A0) is read only: 0.
74h R 04h 04h Repor t no DMA assignment.
75h R 04h 04h Repor t no DMA assignment.
Page 37
Configuration
CARD CONTROL REGISTERS
37
www.national.com
2.4 CARD CONTROL REGISTERS
This section describes the registers at first level indexes in
the range 20h - 2Fh.
The next section describes the chip select configuration
registers, which are accessed using two index levels. The
first index level accesses the Programmable Chip Select Index register at 23h. The second index level accesses a specific chip select configuration register. See TABLE 2-24
"The Programmable Chip Select Configuration Registers"
on page 43.
2.4.1 PC87317 SID Register
This read-only register holds the revision and chip identity
number of the chip. The PC87317VUL is identified by the
value D0h in this register.
FIGURE 2-1. PC87317 SID Register Bitmap
2.4.2 PC97317 SID Register
This read-only register holds the identity number of the chip.
The PC97317VUL is identified by the value DFh in this register.
FIGURE 2-2.
PC97317 SID Register Bitmap
2.4.3 SuperI/O Configuration 1 Register (SIOC1)
This register can be read or written. It is reset by hardware
to 04h, 06h, 14h or 16h. See SELCS and the CFG1 strap
pin in TABLE 2-2 "The Strap Pins" on page 28.
FIGURE 2-3. SIOC1 Register Bitmap
Bit 0 -
ZWS Enable
This bit controls assertion of
ZWS on any host SuperI/O
chip access, except for configuration registers access
(including Serial Isolation register) and except for Parallel Port access.
For
ZWS assertion on host-EPP access, see Section
6.5.17 "Control2 Register" on page 152.
0:
ZWS is not asserted.
1:
ZWS is asserted.
Bit 1 -
CSOUT-NSC-test or CS1/XD0 on Pin 71 Select
This bit is initialized with SELCS strap value (see TABLE 2-2 "The Strap Pins" on page 28).
0:
CSOUT-NSC-test on pin.
1: CS1 or XD0 on pin (according to bit 4 of SuperI/O
Configuration 1 Register (SIOC1)).
Undefined results, when bit 1 of the SuperI/O Configuration
1 register is cleared to zero and bit 4 of the SuperI/O Configuration 1 register is set to one. (see TABLE 2-21).
TABLE 2-21. Signal Assignment for Pin 71
Bit 2 - PC-AT or PS/2 Drive Mode Select
0: PS/2 drive mode.
1: PC-AT drive mode. (Default)
Bit 3 - UART2 or GPIO30-36 Select
0: GPIO30-32 and GPIO34-36 pins are selected
1: UART2 pins are selected
Upon reset, this bit is initialized to 0.
76543210
Reset
Required
00001011
00001011
PC87317 SID Register
Index 20h
Chip ID
Revision ID
76543210
Reset
Required
11111011
11111011
PC97317 SID Register
Index 20h
Chip ID
SIOC1 Bits
41
Pin 71
0 0 CSOUT-NSC-test
0 1 CS1
1 0 Undefined
1 1 XD0
ZWS Enable
General Purpose Scratch Bits
76543210
Reset
Required
0x10x000
SuperI/O Configuration 1
Index 21h
Register (SIOC1),
PC-AT or PS/2 Drive Mode Select
CSOUT-NSC-test or CS1/XD0
UART2 or GPIO30-36 Select
Lock Scratch Bit
X-Bus Data Buffer (XDB) Select
Page 38
Configuration
38
CARD CONTROL REGISTERS
www.national.com
Bit 4 - X-Bus Data Buffer (XDB) Select
Select X-bus buffer on the XDB pins. This read only bit
is initialized with the CFG1 strap value. See TABLE 2-21
and see also Chapter 11 "X-Bus Data Buffer" on page
229.
0: No XDB buffer. XDB pins have alternate function,
see TABLE 1-2 "Multiplexed X-Bus Data Buffer
(XDB) Pins" on page 25.
1: XDB enabled.
Bit 5 - Lock Scratch Bit
This bit controls bits 7 and 6 of this register. Once this
bit is set to 1 by software, it can be cleared to 0 only by
a hardware reset.
0: Bits 7 and 6 of this register are read/write bits.
1: Bits 7 and 6 of this register are read only bits.
Bits 7,6 - General Purpose Scratch Bits
When bit 5 is set to 1, these bits are read only. After reset they can be read or written. Once changed to readonly, they can be changed back to be read/write bits
only by a hardware reset.
2.4.4 SuperI/O Configuration 2 Register (SIOC2)
This read/write register is reset by hardware to 00h-03h.
See BADDR1,0 strap pins in Section 2.1.3 "The Strap Pins"
on page 28.
FIGURE 2-4. SIOC2 Register Bitmap
Bits 1,0 - BADDR1 and BADDR0
Initialized on reset by BADDR1 and BADDR0 strap pins
(BADDR0 on bit 0). These bits select the addresses of
the configuration Index and Data registers and the Plug
and Play ISA Serial Identifier. See TABLE 2-1 "Base
Addresses" on page 27 and TABLE 2-2 "The Strap
Pins" on page 28.
Bit 2 - GPIO22 or
POR Pin Select
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0: The pin is GPIO22.
1: The pin is
POR.
Bits 4,3 - GPIO21, IRSL2/ID2 or IRSL0 Pin Select
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers as shown in
TABLE 2-22 "Signal Assignment for Pins 158 and 77".
T ABLE 2-22. Signal Assignment for Pins 158 and 77
Bit 5 - GPIO20, IRSL1 or ID1 Pin Select
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0: The pin is GPIO20.
1: The pin is IRSL1/ID1.
Bit 6 - GPIO17 or
WDO Pin Select
This bit determines whether GPIO17 or
WDO is routed
to pin 156 when bit 7 of the Port 1 Direction register at
offset 01h of logical device 7 is set to 1. See Section 9.1
"GPIO PORT ACTIVATION" on page 215.
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0: GPIO17 uses the pin. (Default)
1:
WDO uses the pin.
Bit 7 - GPIO Bank Select
This bit selects the active register bank of GPIO registers.
0: Bank 0 is selected. (Default)
1: Bank 1 is selected.
2.4.5 Programmable Chip Select Configuration Index
Register
This read/write register is reset by hardware to 00h. It indicates the index of one of the Programmable Chip Select
(
CS0, CS1 or CS2) configuration registers described in
Section 2.10 "PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS" on page 42.
The data in the indicated register is in the Programmable
Chip Select Configuration Data register at index 24h.
Bits 7 through 4 are read only and return 0000 when read.
FIGURE 2-5. Programmable Chip Select Configuration
Index Register Bitmap
BADDR1 and BADDR0
GPIO Bank Select
76543210
Reset
Required
xx000000
SuperI/O Configuration 2
Index 22h
Register (SIOC2),
GPIO21, IRSL2/ ID2 or ISL0 Pin Select
GPIO22 or
POR Select
GPIO20 or IRSL1 Pin Select
GPIO17 or WDO Pin Select
Bits
4 3
Pin 158
Pin 77
(When Bit 4 of SuperI/O
Config 1 Register = 0)
0 0 GPIO21 IRSL2/SELCS
0 1 IRSL2/ID2 GPIO21/SELCS
1 0 IRSL0 IRSL2/SELCS
1 1 Reserved IRSL2/SELCS
Index of a Programmable
Read Only
76543210
Reset
Required
00000000
0000
Programmable Chip Select
Index 23h
Configuration Index
Chip Select Configuration
Register
Register,
Page 39
Configuration
CARD CONTROL REGISTERS
39
www.national.com
2.4.6 Programmable Chip Select Configuration Data
Register
This read/write register contains the data in the Programmable Chip Select Configuration register (see Section 2.10
"PROGRAMMABLE CHIP SELECT CONFIGURATION
REGISTERS" on page 42) indicated by the Programmable
Chip Select Configuration Index register at index 23h.
FIGURE 2-6. Programmable Chip Select Configuration
Data Register Bitmap
2.4.7 SuperI/O Configuration 3 Register (SIOC3)
This read/write register enables output-pin designation and
interrupt routing. It is reset by hardware to 00h.
FIGURE 2-7. SIOC3 Register Bitmap
Bit 0 - P16 or GPIO25 Pin Select
0: P16 is routed to I/O pin.
1: GPIO25 is routed to I/O pin. The KBC firmware
may write to P16 and read it back as if the pin exist
and left open. Upon reset, this bit is initialized to 0.
Bit 1 - P12 or
CS0 Pin Select
0: P12 is routed to I/O pin.
1:
CS0 is routed to I/O pin. The KBC firmware may
write to P12 and read it back as if the pin exist and
left open. Upon reset, this bit is initialized to 0.
Bit 2 - Reserved
Reserved.
Bit 3 - SCI Polarity Select
0: SCI interrupt is active low.
1: SCI interrupt is active high.
Bits 7-4 - SCI Plug-and-Play Select
SCI can be routed to one of the following ISA interrupts:
IRQ1, IRQ3-IRQ12, IRQ14-IRQ15.
For details on the SCI signal, refer to Chapter 4 on page 53.
TABLE 2-23. SCI Routing
Upon reset, these bits are initialized to 0000.
Disable means the SCI is not routed to any ISA interrupt.
Unpredictable results when invalid values are written.
2.4.8 PC97317 SRID Register
This read-only register holds the revision number of the
PC97317 chip. SRID is incremented on each tapeout.
FIGURE 2-8.
PC97317 SRID Register Bitmap
Data in a Programmable
76543210
Reset
Required
00000000
Programmable Chip Select
Index 24h
Configuration Data
Chip Select Configuration
Register
Register,
Reserved
76543210
Reset
Required
00000000
SuperI/O Configuration 3
Index 25h
Register (SIOC3),
P16 or GPIO25 Select
P12 or
CS0 Select
SCI Plug-and-Play Select
SCI Polarity Select
Bits
7 6 5 4
Interrupt
0 0 0 0 Disable
0 0 0 1 IRQ1
0 0 1 0 Invalid
0 0 1 1 IRQ3
0 1 0 0 IRQ4
0 1 0 1 IRQ5
0 1 1 0 IRQ6
0 1 1 1 IRQ7
1 0 0 0 IRQ8
1 0 0 1 IRQ9
1 0 1 0 IRQ10
1 0 1 1 IRQ11
1 1 0 0 IRQ12
1 1 0 1 Invalid
1 1 1 0 IRQ14
1 1 1 1 IRQ15
76543210
Reset
Required
xxxxxxxx
PC97317 SRID Register
Index 27h
Chip Revision ID
Page 40
Configuration
40
KBC CONFIGURATION REGISTER (LOGICAL DEVICE 0)
www.national.com
2.4.9 SuperI/O Configuration F Register (SIOCF),
Index 2Fh
This register is reserved. Must be written with ‘0’s.
2.5 KBC CONFIGURATION REGISTER (LOGICAL
DEVICE 0)
2.5.1 SuperI/O KBC Configuration Register
This read/write register is reset by hardware to 40h.
FIGURE 2-9. SuperI/O KBC Configuration Register
Bitmap
Bit 0 - TRI-STATE Control
When set, this bit causes the Keyboard and Mouse pins
to be in TRI-STATE(KBCLK, KBDAT, MCLK, and MDAT
pins), when the KBC is inactive (disabled).
This bit is ORed with a bit of PMC1 register of logical device 8.
0: Keyboard and Mouse pins are not put in TRI-STATE
1: Keyboard and Mouse pins are put in TRI-STATE,
when the KBC is inactive.
Bits 5-1 - Reserved
Reserved.
Bits 7,6 - KBC Clock Source
Bit 6 is the LSB. The clock source can be changed only
when the KBC is inactive (disabled).
00:8 MHz
01:12 MHz
10:16 MHz. Undefined results when these bits are 10
and the clock source for the chip is 24 MHz on X1.
11:Reserved.
2.6 FDC CONFIGURATION REGISTERS (LOGICAL
DEVICE 3)
2.6.1 SuperI/O FDC Configuration Register
This read/write register is reset by hardware to 20h.
FIGURE 2-10. SuperI/O FDC Configuration Register
Bitmap
Bit 0 - TRI-STATE Control
When set, this bit causes the FDC pins to be in TRISTATE(except the IRQ and DMA pins) when the FDC is
inactive (disabled).
This bit is ORed with a bit of PMC1 register of logical device 8.
0: FDC pins are not put in TRI-STATE.
1: FDC pins are put in TRI-STATE.
Bits 4-1 - Reserved
Reserved.
Bit 5 - DENSEL Polarity Control
0: DENSEL is active low for 500 Kbps or 1 Mbps data
rates.
1: DENSEL is active high for 500 Kbps or 1 Mbps
data rates. (Default)
Bit 6 - TDR Register Mode
0: PC-AT Compatible drive mode (bits 7 through 2 of
TDR are not driven).
1: Enhanced dr ive mode (bits 7 through 2 of TDR are
driven on TDR read).
Bit 7 - Four Drive Encode
0: Two floppy drives are directly controlled by
DR1-0,
MTR1-0.
1: Four floppy drives are controlled with the aid of an
external decoder.
Reserved
KBC Clock Source
76543210
Reset
Required
00000010
SuperI/O KBC
Index F0h
Configuration
Register,
TRI-STATE Control
TRI-STATE Control
Four Drive Control
76543210
Reset
Required
00000100
Super I/O FDC
Index F0h
Configuration
Reserved
Register,
DENSEL Polarity Control
TDR Register Mode
Page 41
Configuration
PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 4)
41
www.national.com
2.6.2 Drive ID Register
This read/write register is reset by hardware to 00h. These
bits control bits 5 and 4 of the enhanced TDR register.
FIGURE 2-11. Drive ID Register Bitmap
Bits 1,0 - Drive 0 ID
These bits are reflected on bits 5 and 4, respectively, of
the Tape Drive Register (TDR) of the FDC when drive 0
is accessed. See Section 5.3.4 "Tape Drive Register
(TDR)" on page 99.
Bits 3,2 - Drive 1 ID
These bits are reflected on bits 5 and 4, respectively, of
the TDR register of the FDC when drive 1 is accessed.
See Section 5.3.4 "Tape Drive Register (TDR)" on page
99.
Bits 7-4 - Reserved
2.7 PARALLEL PORT CONFIGURATION REGISTER
(LOGICAL DEVICE 4)
2.7.1 SuperI/O Parallel Port Configuration Register
This read/write register is reset by hardware to F2h. For normal operation and to maintain compatibility with future
chips, do not change bits 7 through 4.
FIGURE 2-12. SuperI/O Parallel Port Configuration
Register Bitmap
Bit 0 - TRI-STATE Control
When set, this bit causes the parallel port pins to be in
TRI-STATE(except IRQ and DMA pins) when the parallel port is inactive (disabled). This bit is ORed with a bit
of the PMC1 register of logical device 8.
Bit 1 - Clock Enable
0: Parallel port clock disabled.
ECP modes and EPP time-out are not functional
when the logical device is active. Registers are
maintained.
1: Parallel port clock enabled.
All operation modes are functional when the logical
device is active. This bit is ANDed with a bit of the
PMC3 register of the power management device
(logical device 8).
Bit 2 - Reserved
Bit 3 - Reported Parallel Port of PnP ISA Resource Data
Report to the ISA PnP Resource Data the device identification.
0: ECP device.
1: SPP device.
Bit 4 - Configuration Bits within the Parallel Port
0: The registers at base (address) + 403h, base +
404h and base + 405h are not accessible (reads
and writes are ignored).
1: When ECP is selected by bits 7 through 5, the reg-
isters at base (address) + 403h, base + 404h and
base + 405h are accessible.
This option supports run-time configuration within
the Parallel Port address space. An 8-byte (and
1024-byte) aligned base address is required to access these registers. See Chapter 6 "Parallel Por t
(Logical Device 4)" on page 137 for details.
Bit 7-5 - Parallel Port Mode Select
Bit 5 is the LSB.
Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled
by bit 4 of the Control2 configuration register of the parallel port at offset 02h. See Section 6.5.17 "Control2
Register" on page 152.
000: SPP Compatible mode. PD7-0 are always output
signals.
001: SPP Extended mode. PD7-0 direction controlled
by software.
010:EPP 1.7 mode.
011:EPP 1.9mode.
100:ECP mode (IEEE1284 register set), with no sup-
port for EPP mode.
101:Reserved.
110:Reserved.
111:ECP mode (IEEE1284 register set), with EPP
mode selectable as mode 4.
Drive 0 ID
Reserved
76543210
Reset
Required
00000000
Index F1h
Drive ID Register,
Drive 1 ID
TRI-STATE Control
Parallel Port Mode Select
76543210
Reset
Required
01001111
Index F0h
Configuration Register,
PP of PnP ISA Resource Data
SuperI/O Parallel Port
Clock Enable
Reserved
Configuration Bits within the Parallel Port
Page 42
Configuration
42
UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 5)
www.national.com
2.8 UART2 AND INFRARED CONFIGURATION
REGISTER (LOGICAL DEVICE 5)
2.8.1 SuperI/O UART2 Configuration Register
This read/write register is reset by hardware to 02h.
FIGURE 2-13. SuperI/O UART2 Configuration Register
Bitmap
Bit 0 - TRI-STATE Control for UART signals
This bit controls the TRI-STATE status of UART signals
(except IRQ and DMA signals) when the UART is inactive (disabled). This bit is ORed with a bit of the PMC1
register of the power management device (logical device 8).
0: Signals not in TRI-STATE.
1: Signals in TRI-STATE.
Bit 1 - Power Mode Control
0: Low power mode.
UART Clock disabled. UART output signals are set
to their default state. The
RI input signal can be
programmed to generate an interrupt. Registers
are maintained.
1: Normal power mode.
UART clock enabled. The UART is functional when
the logical device is active. This bit is ANDed with a
bit of the PMC3 register of the power management
device (logical device 8)
Bit 2 - Busy Indicator
This read-only bit can be used by power management
software to decide when to power down the logical device. This bit is also accessed via the PMC3 register of
the power management device (logical device 8).
0: No transfer in progress.
1: Transfer in progress.
Bit 3 - Ring Detection on
RI Pin
0: The UART
RI input signal uses the RI pin.
1: The UART
RI input signal is the RING detection
signal on the
RING pin. RING pin is selected by the
APCR2 register of the Advanced Power Control
(APC) module.
Bits 6-4 - Reserved
Bit 7 - Bank Select Enable
Enables bank switching. If this bit is cleared, all attempts
to access the extended registers are ignored.
2.9 UART1 CONFIGURATION REGISTER
(LOGICAL DEVICE 6)
2.9.1 SuperI/O UART1 Configuration Register
This read/write register is reset by hardware to 02h. Its bits function like the bits in the SuperI/O UART2 Configuration register
FIGURE 2-14. SuperI/O UART1 Configuration Register
Bitmap
2.10 PROGRAMMABLE CHIP SELECT
CONFIGURATION REGISTERS
The chip select configuration registers are accessed using
two index levels. The first index level accesses the Programmable Chip Select Index register at 23h. See Section 2.4.5
"Programmable Chip Select Configuration Index Register"
on page 38. The second index level accesses a specific chip
select configuration register as shown in TABLE 2-24 "The
Programmable Chip Select Configuration Registers".
See also Section 9.3 "PROGRAMMABLE CHIP SELECT
OUTPUT SIGNALS" on page 216 and the description of
each signal in TABLE 1-1 "Signal/Pin Description Table" on
page 17.
TRI-STATE Control for
Bank Select Enable
76543210
Reset
Required
01000000
Index F0h
Configuration Register,
Ring Detection on RI Pin
SuperI/O UART2
Power Mode Control
Busy Indicator
Reserved
UART2 Signals
TRI-STATE Control for
Bank Select Enable
76543210
Reset
Required
01000000
Index F0h
Configuration Register,
Ring Detection on RI Pin
SuperI/O UART1
Power Mode Control
Busy Indicator
Reserved
UART1 Pins
Page 43
Configuration
PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS
43
www.national.com
TABLE 2-24. The Programmable Chip Select
Configuration Registers
2.10.1
CS0 Base Address MSB Register
This read/write register is reset by hardware to 00h. Same
as Plug and Play ISA base address register at index 60h.
See TABLE 2-7 "Plug and Play (PnP) I/O Space Configuration Registers" on page 31.
2.10.2
CS0 Base Address LSB Register
This read/write register is reset by hardware to 00h. It is the
same as the Plug and Play ISA base address register at index 61h. See TABLE 2-7 "Plug and Play (PnP) I/O Space
Configuration Registers" on page 31.
2.10.3
CS0 Configuration Register
This read/write register is reset by hardware to 00h. It controls activation of the
CS0 signal upon an address match,
when AEN is inactive (low) and the non-masked address
pins match the corresponding base address bits.
FIGURE 2-15. SuperI/O
CS0 Configuration Register
Bitmap
Bit 0 - Mask Address Pin A0
0: A0 is decoded.
1: A0 is not decoded; it is ignored.
Bit 1 - Mask Address Pin A1
0: A1 is decoded.
1: A1 is not decoded (ignored).
Bit 2 - Mask Address Pin A2
0: A2 is decoded.
1: A2 is not decoded; it is ignored.
Bit 3 - Mask Address Pin A3
0: A3 is decoded.
1: A3 is not decoded; it is ignored.
Bit 4 - Assert Chip Select Signal on Write
0: Chip select not asserted on address match and
when
WR is active (low).
1: Chip select asser ted on address match and when
WR is active (low).
Bit 5 - Assert Chip Select Signal on Read
0: Chip select not asserted on address match and
when
RD is active (low).
1: Chip select asser ted on address match and when
RD is active (low).
Bit 6 - Unaffected by
RD/WR
Bits 5 and 4 are ignored when this bit is set.
0: Chip select asserted on address match, qualified
by
RD or WR pin state and contents of bits 5 and 4.
1: Chip select asser ted on address match, regardless
of
RD or WR pin state and regardless of contents
of bits 5 and 4.
Bit 7 - Mask Address Pins A11-A0
0: A11 are decoded.
1: A11 are not decoded; they are ignored.
2.10.4 Reserved
Attempts to access this register produce undefined results.
2.10.5
CS1 Base Address MSB Register
This read/write register is reset by hardware to 00h. Same
as Plug and Play ISA base address register at index 60h.
See TABLE 2-7 "Plug and Play (PnP) I/O Space Configuration Registers" on page 31.
2.10.6
CS1 Base Address LSB Register
This read/write register is reset by hardware to 00h. Same
as Plug and Play ISA base address register at index 61h.
See TABLE 2-7 "Plug and Play (PnP) I/O Space Configuration Registers" on page 31.
2.10.7
CS1 Configuration Register
This read/write register is reset by hardware to 00h. It functions like the
CS0 Configuration Register described in Sec-
tion 2.10.3 "CS0 Configuration Register" on page 43.
Second
Level
Index
Register Name Type Reset
00h
CS0 Base Address MSB Register R/W 00h
01h CS0 Base Address LSB Register R/W 00h
02h CS0 Configuration Register R/W 00h
03h Reserved - 04h CS1 Base Address MSB Register R/W 00h
05h CS1 Base Address LSB Register R/W 00h
06h CS1 Configuration Register R/W 00h
07h Reserved - 08h CS2 Base Address MSB Register R/W 00h
09h CS2 Base Address LSB Register R/W 00h
0Ah CS2 Configuration Register R/W 00h
0Bh-0Fh Reserved - -
10h-FFh Not Accessible - -
Mask Address Pins A11
76543210
Reset
Required
00000000
Second Level
Register,
Mask Address Pin A3
CS0 Configuration
Mask Address Pin A1
Mask Address Pin A2
Assert Chip Select Signal on Read
Mask Address Pin A0
Unaffected by
RD/WR
Assert Chip Select Signal on Write
Index 02h
Page 44
Configuration
44
CONFIGURATION REGISTER BITMAPS
www.national.com
FIGURE 2-16. SuperI/O CS1 Configuration Register
Bitmap
2.10.8 Reserved
Attempts to access this register produce undefined results.
2.10.9
CS2 Base Address MSB Register
This read/write register is reset by hardware to 00h. It functions like the Plug and Play ISA base address register at index 60h. See TABLE 2-7 "Plug and Play (PnP) I/O Space
Configuration Registers" on page 31.
2.10.10
CS2 Base Address LSB Register
This read/write register is reset by hardware to 00h. It functions like the Plug and Play ISA base address register at index 61h. See TABLE 2-7 "Plug and Play (PnP) I/O Space
Configuration Registers" on page 31.
2.10.11
CS2 Configuration Register
This read/write register is reset by hardware to 00h. It functions like the
CS0 Configuration register.
FIGURE 2-17. SuperI/O
CS2 Configuration Register
Bitmap
2.10.12 Reserved, Second Level Indexes 0Bh-0Fh
Attempts to access these registers produce undefined results.
2.10.13 Not Accessible, Second Level Indexes 10h-FFh
Not accessible because bits 7-4 of the Index register are 0.
2.11 CONFIGURATION REGISTER BITMAPS
Mask Address Pins A11
76543210
Reset
Required
00000000
Second Level
Register,
Mask Address Pin A3
CS1 Configuration
Mask Address Pin A1
Mask Address Pin A2
Assert Chip Select Signal on Read
Mask Address Pin A0
Unaffected by
RD/WR
Assert Chip Select Signal on Write
Index 06h
Mask Address Pins A11
76543210
Reset
Required
00000000
Second Level
Register,
Mask Address Pin A3
CS2 Configuration
Mask Address Pin A1
Mask Address Pin A2
Assert Chip Select Signal on Read
Mask Address Pin A0
Unaffected by
RD/WR
Assert Chip Select Signal on Write
Index 0Ah
76543210
Reset
Required
00001011
00001011
SID (In PC87317)
Index 20h
Register,
Chip ID
Revision ID
76543210
Reset
Required
11111011
11111011
SID (In PC97317)
Index 20h
Register,
Chip ID
ZWS Enable
General Purpose Scratch Bits
76543210
Reset
Required
0x10x000
SuperI/O Configuration 1
Index 21h
Register (SIOC1),
PC-AT or PS/2 Drive Mode Select
CSOUT or CS0 Select
Lock Scratch Bit
X-Bus Data Buffer (XDB) Select
UART2 or GPIO30-36 Select
BADDR1 and BADDR0
GPIO Bank Select
76543210
Reset
Required
xx000000
SuperI/O Configuration 2
Index 22h
Register (SIOC2),
GPIO21, IRSL2, ID2 or ISL0 Pin Select
GPIO22 or
POR Select
GPIO20 or IRSL1 Pin Select
GPIO17 or WDO Pin Select
Page 45
Configuration
CONFIGURATION REGISTER BITMAPS
45
www.national.com
Index of a Programmable
Read Only
76543210
Reset
Required
00000000
0000
Programmable Chip Select
Index 23h
Configuration Index
Chip Select Configuration
Register
Register,
Data in a Programmable
76543210
Reset
Required
00000000
Programmable Chip Select
Index 24h
Configuration Data
Chip Select Configuration
Register
Register,
Reserved
76543210
Reset
Required
00000000
SuperI/O Configuration 3
Index 25h
Register (SIOC3),
P16 or GPIO25 Select
P12 or
CS0 Select
SCI Plug-and-Play Select
SCI Polarity Select
76543210
Reset
Required
xxxxxxxx
SRID (In the 97317 only)
Index 27h
Register,
Chip Revision ID
KBC Clock Source
76543210
Reset
Required
00000010
SuperI/O KBC
Index F0h
Configuration
Reserved
Register,
TRI-STATE Control
TRI-STATE Control
Four Drive Control
76543210
Reset
Required
00000100
SuperI/O FDC
Index F0h
Configuration
Reserved
Register,
DENSEL Polarity Control
TDR Register Mode
Drive 0 ID
Reserved
76543210
Reset
Required
00000000
Index F1h
Drive ID Register,
Drive 1 ID
Mask Address Pins A11-4
76543210
Reset
Required
00000000
Second Level
Register,
Mask Address Pin A3
CS0 Configuration
Mask Address Pin A1
Mask Address Pin A2
Assert Chip Select Signal on Read
Mask Address Pin A0
Unaffected by
RD/WR
Assert Chip Select Signal on Write
Index 02h
Page 46
Configuration
46
CONFIGURATION REGISTER BITMAPS
www.national.com
Mask Address Pins A11-4
76543210
Reset
Required
00000000
Second Level
Register,
Mask Address Pin A3
CS1 Configuration
Mask Address Pin A1
Mask Address Pin A2
Assert Chip Select Signal on Read
Mask Address Pin A0
Unaffected by
RD/WR
Assert Chip Select Signal on Write
Index 06h
Mask Address Pins A11-4
76543210
Reset
Required
00000000
Second Level
Register,
Mask Address Pin A3
CS2 Configuration
Mask Address Pin A1
Mask Address Pin A2
Assert Chip Select Signal on Read
Mask Address Pin A0
Unaffected by
RD/WR
Assert Chip Select Signal on Write
Index 0Ah
TRI-STATE Control
Parallel Port Mode Select
76543210
Reset
Required
01001111
Index F0h
Configuration Register,
PP of PnP ISA Resource Data
SuperI/O Parallel Port
Clock Enable
Reserved
Configuration Bits within the Parallel Port
TRI-STATE Control for
Bank Select Enable
76543210
Reset
Required
00000000
Index F0h
Configuration Register,
Ring Detection on RI Pin
SuperI/O UART1,2
Power Mode Control
Busy Indicator
Reserved
UART Pins
Page 47
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
47
3.0 Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
www.national.com
3.0 Keyboard (and Mouse) Controller
(KBC) (Logical Devices 0 and 1)
The Keyboard Controller (KBC) is a functionally independent programmable device controller. It is implemented
physically as a single hardware module on the
PC87317VUL multi-I/O chip and houses two separate logical devices: a keyboard controller and a mouse controller.
The KBC accepts user input from the keyboard or mouse,
and transfers this input to the host PC via the common
PC87317VUL-PC interface.
The KBC is functionally equivalent to the industry standard
8042A keyboard controller, which may serve as a detailed
technical reference for the KBC.
The KBC is delivered preprogrammed with customer-supplied code. KBC firmware code is identical to 8042 code,
and to code of the keyboard controller of the PC87323VUL
chip. The PC87323VUL is recommended as a development
platform for the KBC since it uses identical code and includes internal program RAM that enables software development.
3.1 SYSTEM ARCHITECTURE
The KBC is a general purpose microcontroller, with an 8-bit
internal data bus. See FIGURE 3-1 "KBC System Functional Block Diagram". It includes these functional blocks:
Serial Open-collector Drivers: Four open-collector bi-di-
rectional serial lines enable serial data exchange with
the external devices (keyboard and mouse) using the
PS/2 protocol.
Program ROM: 2 Kbytes of ROM store program machine
code in non-erasable memory. The code is copied to
this ROM during manufacture, from customer-supplied
code.
Data RAM: A 256-byte data RAM enables run-time inter-
nal data storage, and includes an 8-level stack and 16
8-bit registers.
Timer/Counter: An internal 8-bit timer/counter can count
external events or pre-divided system clock pulses. An
internal time-out interrupt may be generated by this device.
I/O Ports: Two 8-bit ports (Port 1 and Port 2) serve various
I/O functions. Some are for general purpose use, others
are utilized by the KBC firmware.
FIGURE 3-1. KBC System Functional Block Diagram
KBDATInterrupt Matrix KBCLK MDAT MCLK
Program
ROM
2 K x 8
Data
RAM
256 x 8
(including
registers
and stack)
I/O Port 2
8-Bit
Serial Open-Collector
Drivers
8-Bit Timer
DBBOUT
DBBINSTATUS
RD WR
P21-20
P27, P26, P23, P22
TEST1
TEST0
D7-0
Timer
8-Bit Internal Bus
Program
Address
IBF
I/O Interface
PC87317VUL Interface
I/O PORT 1
8-Bit
P11,10
P17, P16, P12
P24
P25
8-Bit
CPU
To PnP
A2
or Counter
Overflow
Page 48
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
48
FUNCTIONAL OVERVIEW
www.national.com
FIGURE 3-2. System Interfaces
3.2 FUNCTIONAL OVERVIEW
The KBC supports two external devices — a keyboard and
a mouse. Each device communicates with the KBC via two
bidirectional serial signals. Five additional external generalpurpose I/O signals are provided.
KBC operation involves three signal interfaces:
●
External I/O interface
●
Internal KBC - PC87317VUL interface
●
PC87317VUL - PC chip set interface.
These system interfaces are shown in FIGURE 3-2 "System Interfaces".
The KBC uses two data registers (for input and output) and
a status register to communicate with the PC87317VUL
central system. Data exchange between these units may be
based on programmed I/O or interrupt-driven.
The KBC has two internal interrupts: the Input Buffer Full
(IBF) interrupt and Timer Overflow interrupt (see FIGURE
3-1 "KBC System Functional Block Diagram" on page 47).
These two interrupts can be independently enabled or disabled by KBC firmware. Both are disabled by a hard reset.
These two interrupts only affect the execution flow of the
KBC firmware, and have no connection with the external interrupts requested by this logical device.
The KBC can generate two external interrupt requests.
These request signals are controlled by the KBC firmware
which generates them by manipulating I/O port signals. See
Section 3.3.2 "Interrupt Request Signals".
The PC87317VUL supports the KBC and handles interactions with the PC chip set. In addition to data transfer, these
interactions include KBC configuration, activation and status monitoring. The PC87317VUL interconnects with the
host via one interface that is shared by all chip devices.
The KBC clock is generated from the main clock of the chip,
which may come from an external clock source or from the
internal frequency multiplier. (See Section 3.3 "DEVICE
CONFIGURATION" and FIGURE 3-5 "Timing Generation
and Timer Circuit" on page 50.) The KBC clock rate is configured by the SIO Configuration Registers.
3.3 DEVICE CONFIGURATION
The KBC hardware contains two logical devices—the KBC
(logical device 0) and the mouse (logical device 1).
3.3.1 I/O Address Space
The KBC has two I/O addresses and one IRQ line (KBC
IRQ) and can operate without the companion mouse.
The mouse cannot operate without the KBC device. It has
one IRQ line (mouse IRQ) but has no I/O address. It utilizes
the KBC I/O addresses.
3.3.2 Interrupt Request Signals
The KBC IRQ and Mouse IRQ interrupt request signals are
identical to (or functions of) the P24 and P25 signals of the
8042. These interrupt request signals are routed internally
to the Plug and Play interrupt Matrix and may be routed to
user-programmable IRQ pins. Each logical device is independently controlled.
The Interrupt Select registers (index 70h for each logical device) select the IRQ pin to which the corresponding interrupt
request is routed. The interrupt may also be disabled by not
routing its request signal to any IRQ pin.
Bit 0 of the Interrupt Type registers (index 71h for each logical device) determines whether the interrupts are passed
(bit 0 = 0) or latched (bit 0 = 1). If bit 0 = 0, interrupt request
signals (P24 and P25) are passed directly to the selected
IRQ pin. If bit 0 = 1, interrupt request signals that become
PC
Chip Set
SA15-0
PC87317VUL
XD7-0
MR
A15-0
D7-0
AEN
RD
WR
KBC IRQ
Mouse IRQ
KBC Device
KBCLK
KBDAT
TEST0
P10
Keyboard Clock
Keyboard Data
MCLK
MDAT
TEST1
P11
Mouse Clock
Mouse Data
P26
P27
P23
P22
STATUS
DBBIN
DBBOUT
Plug and
Play
Matrix
P24
P25
P16
P17
P20
P21
P12
Internal Interface Bus
IRQn
Page 49
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
DEVICE CONFIGURATION
49
www.national.com
active are latched on their rising edge, and held until read
from the KBC output buffer (port 60h). FIGURE 3-3 illus-
trates the internal interrupt request logic.
Note:
The EN FLAGS command (used for routing OBF and IBF onto P24 and P25 in the 8042) causes unpredictable results
and should not be issued.
FIGURE 3-3. Interrupt Request Logic
3.3.3 KBC Clock
The KBC clock frequency is selected by the Super I/O KBC
Configuration Register at index F0h of logical device 0 to be
either 8, 12 or 16 MHz. 16 MHz is not available when the
clock source on pin X1 is 24 MHz. This clock is generated
from a 32.768 KHz crystal connected to pins X1C and X2C,
or from either a 24 MHz or a 48 MHz clock input at pin X1.
See Section 2.5.1 "SuperI/O KBC Configuration Register"
on page 40. The clock source and frequency may only be
changed when the KBC is disabled.
For details regarding the configuration of each device, refer
to TABLES 2-12 "KBC Configuration Registers for Keyboard - Logical Device 0" and 2-13 "KBC Configuration
Registers for Mouse - Logical Device 1" on page 34.
FIGURE 3-4. External Clock Connection
From Mouse IRQ
A15-0
AEN
Address
Decoder
MR
Port 60
Read
Mouse IRQ Feedback
From KBC IRQ
PR
Q
D
CLR
“1”
0
1
MUX
Interrupt
KBC IRQ Feedback
CLK
Interrupt Enable
A15-0
AEN
Address
Decoder
Port 60
Read
Interrupt Enable
MR
(1 = Latch)
Interrupt
(0 = Invert)
To Selected KBC IRQ Pin
Type
Polarity
0
1
MUX
Plug and
Play Matrix
PR
Q
D
CLR
“1”
0
1
MUX
Interrupt
CLK
(1 = Latch)
Interrupt
(0 = Invert)
To Selected Mouse IRQ Pin
Type
Polarity
0
1
MUX
Plug and
Play Matrix
RD
RD
PC87317VUL
X1
+V
CC
External
Clock
Standard or
Open-Collector
TTL Driver
Page 50
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
50
EXTERNAL I/O INTERFACES
www.national.com
FIGURE 3-5. Timing Generation and Timer Circuit
3.3.4 Timer or Event Counter
The keyboard controller includes an 8-bit counter, which
can be used as a timer or an event counter, as selected by
the firmware.
Timer Operation
When the internal clock is chosen as the counter input, the
counter functions as a timer. The clock fed to the timer consists of the KBC instruction cycle clock, divided by 32. (See
FIGURES 3-9 "Instruction Timing" on page 52 and 3-5
"Timing Generation and Timer Circuit".) The divisor is reset
only by a hardware reset or when the timer is started by an
STRT T instruction.
Event Counter Operation
When the clock input of the counter is switched to the external input (MCLK), it becomes an event counter. The falling
edge of the signal on the MCLK pin causes the counter to
increment. Timer Overflow Flag and Timer interrupt operate
as in the timer mode.
3.4 EXTERNAL I/O INTERFACES
The PC chip set interfaces with the PC87317VUL as illustrated in FIGURE 3-2 "System Interfaces" on page 48.
All data transactions between the KBC and the PC chip set
are handled by the PC87317VUL.
The PC87317VUL decodes all I/O device chip-select functions from the address bus. The KBC chip-select codes are,
traditionally, 60h or 64h, as described in TABLE 3-1 "System Interface Operations" on page 51. (These addresses
are user-programmable.)
The external interface includes two sets of signals: the keyboard and mouse interface signals, and the general-purpose I/O signals.
3.4.1 Keyboard and Mouse Interface
Four serial I/O signals interface with the external keyboard
and mouse. These signals are driven by open-collector drivers with signals derived from two I/O ports residing on the
internal bus. Each output can drive 16 mA, making them
suitable for driving the keyboard and mouse cables. The
signals are named KBCLK, KBDAT, MCLK and MDAT, and
they are the logical complements of P26, P27, P23 and
P22, respectively.
TEST0 and TEST1 are dedicated test pins, internally connected to KBCLK and MCLK, respectively, as shown in FIGURES 3-1 "KBC System Functional Block Diagram" on
page 47 and 3-2 "System Interfaces" on page 48. These
pins may be used as logical conditions for conditional jump
instructions, which directly check the logical levels at the
pins.
KBDAT and MDAT are connected to pins P10 and P11, respectively.
MCLK also provides input to the event counter.
When the KBC is disabled, the KBCLK, KBDAT, MCLK and
MDAT pins can be put in TRI-STATE. The KBC can be disabled via the Activate register in logical device 0 or via bit 0
of FER1 register in logical device 8. The above pins can be
put in TRI-STATE via bit 0 of the SuperI/O KBC Configuration register in logical device 0 or via bit 0 of the PMC1 register in logical device 8. The Activate register in logical
device 1 has no effect on these pins.
3.4.2 General Purpose I/O Signals
The P12, P16, P17, P20 and P21 general purpose I/O signals interface to two I/O ports (port1 and port2). P12, P16
and P17 are mapped to port 1 and P20 and P21 are
mapped to port 2.
P12 port’s output can be routed internally to
POR and/or
SCI. (See Section 4.4.3 "System Power-Up and Power-Off
Activation Event Description" on page 67)
External
TEST1
3-State
5-Cycle
Timer
Prescaler
8-Bit Timer
or Counter
Overflow
Flag
Stop
Counter
Counter
Timer
Counter
Interrupt
(MCLK)
Frequency
X1
X1C
X2C
External
32768 Hz
Crystal
External Event Input
24 or 48 MHz
Clock
÷
KBC Clock
Clock
Select
48 MHz
2 or 3
÷ 2
Select
Frequency
Multiplier
(1465)
Source
32-Bit
Page 51
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
INTERNAL KBC - PC87317VUL INTERFACE
51
www.national.com
P12, P16 and P17 are driven by quasi-bidirectional drivers.
(See FIGURE 3-6 "Quasi-Bidirectional Driver".) These signals are called quasi-bidirectional because the output buffer
cannot be turned off (even when the I/O signal is used for
input).
During output, a 1 written to output is strongly pulled up for
the duration of a (short) write pulse, and thereafter maintained by a high impedance “weak” active pull-up (implemented by a degenerated transistor employed as a
switchable pull-up resistor). A series resistor to those port
lines used for input is recommended to limit the surge current during the strong pull-up. See FIGURE 3-7 "Current
Limiting Resistor".
If a 1 is asserted, an externally applied signal may pull down
the output. Therefore, input from this quasi-bidirectional circuit can be correctly read if preceded by a 1 written to output.
P20 and P21 are driven by open-drain drivers.
When the KBC is reset, all port data bits are initialized to 1.
FIGURE 3-6. Quasi-Bidirectional Driver
FIGURE 3-7. Current Limiting Resistor
3.5 INTERNAL KBC - PC87317VUL INTERFACE
The KBC interfaces internally with the PC87317VUL via
three registers: an input (DBBIN), output (DBBOUT) and
status (STATUS) register. See FIGURE 3-1 "KBC System
Functional Block Diagram" on page 47 and TABLE 3-1
"System Interface Operations".
TABLE 3-1 "System Interface Operations" illustrates the
use of address line A2 to differentiate between data and
commands. The device is selected by chip identification of
default address 60h (when A2 is 0) or 64h (when A2 is 1).
After reset, these addresses can be changed by software.
TABLE 3-1. System Interface Operations
MR
Port
Write
Internal Bus
PORT
F/F
ORL, ANL
+VCC
PAD
IN
Q1
Q2
Q3
D
P
Q
Q
PC87317VUL
Port Pin
Port Pin
R
R
R: current limiting resistor
A small-value series current limiting
resistor is recommended when
port pins are used for input.
100 500Ω–
100 500Ω–
RD WR
Default
Addresses
Operation
0 1 60h
Read DBBOUT
1 0 60h
Write DBBIN, F1 Clear (Data)
0 1 64h
Read STATUS
1 0 64h
Write DBBIN, F1 Set (Command)
Page 52
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
52
INSTRUCTION TIMING
www.national.com
3.5.1 The KBC DBBOUT Register, Offset 60h,
Read Only
The DBBOUT register transfers data from the keyboard
controller to the PC87317VUL. It is written to by the keyboard controller and read by the PC87317VUL for transfer
to the PC. The PC may be notified of the need to read data
from the KBC by an interrupt request or by polling the Output Buffer Full (OBF) bit (bit 0 of the KBC STATUS register
described in Section 3.5.3 "The KBC STATUS Register").
3.5.2 The KBC DBBIN Register, Offset 60h (F1 Clear)
or 64h (F1 Set), Write Only
The DBBIN register transfers data from the PC87317VUL
system to the keyboard controller. (This transaction is transparent to the user, who should program the device as if direct access to the registers were in effect.)
When data is received in this manner, an Input Buffer Full
(IBF) internal interrupt may be generated in the KBC, to deal
with this data. Alternatively, reception of data in this manner
can be detected by the KBC polling the Input Buffer Full bit
(IBF, bit 1 of the KBC STATUS register).
3.5.3 The KBC STATUS Register
The STATUS register holds information regarding the system interface status.The bitmap below shows the bit definition of this register. This register is controlled by the KBC
firmware and hardware, and is read-only for the system.
FIGURE 3-8. KBC STATUS Configuration Register Bit-
map
Bit 0 - OBF, Output Buffer Full
A 1 indicates that data has been written into the DBBOUT register by the KBC. It is cleared by a system
read operation from DBBOUT.
Bit 1 - IBF, Input Buffer Full
When a write operation is performed by the host system,
this bit is set to 1, which may be set up to trigger the IBF
interrupt. Upon executing an IN A, DBB instruction, it is
cleared.
Bit 2 - F0, General Purpose Flag
A general purpose flag that can be cleared or toggled by
the keyboard controller firmware.
Bit 3 - F1, Command/Data Flag
This flag holds the state of address line A2 while a write
operation is performed by the host system. It distinguishes between commands and data from the host
system. In this device, a write with A2 = 1 (hence F1 =
1) is defined as a command, and A2 = 0 (hence F1 = 0)
is data.
Bits 7-4, General Purpose Flags
These flags may be modified by KBC firmware.
3.6 INSTRUCTION TIMING
The KBC clock is first divided by 3 to generate the state timing, then by 5 to generate the instruction timing. Thus each
instruction cycle consists of five states and 15 clock cycles.
Most keyboard controller instructions require only one instruction cycle, while some require two cycles. Refer to the
8042 or PC87323VUL instruction set for details.
FIGURE 3-9. Instruction Timing
76543210
Reset
OBF Output Buffer Full
IBF Input Buffer Full
F0 General Purpose Flag
F1 Command or Data Flag
General Purpose
Flags
KBC Status Register
Offset 64h
00000000
Read Only
S1 S2 S3 S4 S5 S1
1 Instruction Cycle = 15 Clock Cycles
KBC CLK
Page 53
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
53
4.0 Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
www.national.com
4.0 Real-Time Clock (RTC) and
Advanced Power Control (APC)
(Logical Device 2)
The RTC logical device contains two major functions: the
Real-Time Clock (RTC) and Advanced Power Control
(APC).
The RTC is a timekeeping module that provides a time of
day clock and a multi-century calendar, alarm facilities and
three programmable timer interrupts. It maintains valid timekeeping and retains RAM contents during power-down using external battery backup power and offers RAM-Lock
schemes and Power Management options.
RTC software module is compatible with the DS1287 and
MC146818 clock chips. (The RTC module differs from
these two chips in the following feature: Port 70 is read/write
in this module, and is write-only in the DS1287 and
MC146818.)
The APC function enables automatic PC system powerstate control in response to external events, adding power
management ability to the PC host system.
Automatic Power-Up switching enables efficient use of the
PC system in applications which are typically powered up at
all times, such as telephone answering machines or fax receivers. Automatic Power-Down switching enables a controlled power-down sequence when switched off by the
user.
The PC87317VUL APC module supports a variety of external General Purpose Power Management interrupts, giving
the user software - selectable input signal definition for each
individual input. It maintains a specific Power Management
Timer for implementing operational logic and generating the
appropriate interrupt request.
The module complies with the ACPI (Rev 1.0) standard definition.
Battery-Backed Register Banks and RAM
The RTC and APC module has three battery-backed register banks. Two are used by the logical units themselves.
The host system uses the third for general purpose batterybacked storage.
Battery-backup power enables information retention during
system power down.
The banks are:
●
Bank 0 - General Purpose Register Bank
●
Bank 1 - RTC Register Bank
●
Bank 2 - APC Register Bank
The memory maps and register content for each of the three
banks are illustrated in Section 4.9 "REGISTER BANK TABLES" on page 89.
The lower 64-byte locations of the three banks are shared.
The first 14 bytes store time and alarm data and contain
control registers. The next 50 bytes are general purpose
memory.
The upper 64 bytes of bank addresses are utilized as follows:
●
Bank 0 supplies an additional 64 bytes of memory
backed RAM.
●
Bank 1 uses the upper 64 bytes for functions specific
to the RTC activity and for addressing Upper RAM.
●
Bank 2 uses the upper 64 bytes for functions specific
to the APC activity.
The active bank is selected by setting RTC Control Register
A (CRA) bits 6-4 (DV2-0). (See TABLE 4-3 "Divider Chain
Control and Bank Selection" on page 57.)
All RTC register are accessed by an Index and a Data register (at
base address
and
base address+1
). The Index register points to the register location being accessed, and the
Data register contains the data to be transferred to or from
the register. An additional 128 bytes of battery-backed RAM
(also called upper RAM) may be accessed via a second level address: the second level uses the upper RAM Index register at index 50h of bank 1 and the upper RAM Data
register at index 53h of bank 1.
Access to the three register banks and RAM may be locked.
For details see Section 4.5.8 "RAM Lock Register (RLR)" on
page 72.
4.1 RTC OVERVIEW
RTC operation is controlled using the control registers listed
in TABLE 4-1 "RTC Control Registers" below. These registers appear in all the RTC register banks. See Section 4.9
"REGISTER BANK TABLES" on page 89.
TABLE 4-1. RTC Control Registers
RTC configuration registers within the PC87317VUL store
the settings for all interface, configuration and power management options. These registers are described in detail in
Section 2.3 "THE CONFIGURATION REGISTERS" on
page 29.
The RTC employs an external crystal connected to an internal oscillator circuit or an optional external clock input, as
the basic clock for timekeeping.
Local battery-backed RAM serves as storage for all timekeeping functions.
4.1.1 RTC Hardware and Functional Description
Bus Interface
The RTC function is initially mapped to the default I/O registers at addresses 70h (index) and 71h (data) within the
PC87317VUL. These registers may be reassigned, in compliance with the Plug and Play requirements. See Section
2.2 "SOFTWARE CONFIGURATION" on page 28.
1. These registers have relocatable indexes.
See register descriptions.
Index Name Description
0Ah CRA RTC Control Register A
0Bh CRB RTC Control Register B
0Ch CRC RTC Control Register C
0Dh CRD RTC Control Register D
rel
1
DMAR Day-of-Month Alarm Register
rel
1
MAR Month Alar m Register
rel
1
CR Century Register
Page 54
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
54
RTC OVERVIEW
www.national.com
External Clock and Timing Generation
The RTC can use one of the following timekeeping input
clock options:
●
A 32768 Hz crystal connected externally at the X1C
and X2C pins completes an oscillator circuit and generates the 32768 Hz input clock. (See FIGURE 4-1
"Oscillator Internal and External Circuitry" on page
54.)
●
An external clock may be connected to pin X1C.
The time generation function divides the 32.768 KHz by 2
15
to derive a 1 Hz signal which serves as the input for timekeeping functions. Bits 6-4 of RTC Control Register A
(CRA) control the activity and location of the divider chain in
memory. Bits 3-0 of the CRA register select one of fifteen
taps from the divider chain to be used as a periodic interrupt. See Section 4.2.1 "RTC Control Register A (CRA)" on
page 56 for a description of divider configurations and rate
selections.
The divider chain is reset to 0 by bits 6-4 of the CRA register. An update occurs 500 msec after the divider chain is activated by setting normal operational mode (bits 6-4 of CRA
= 010). The periodic flag becomes active one half of the programmed period after the divider chain is activated.
FIGURE 4-1 "Oscillator Internal and External Circuitry" illustrates the internal and external circuitry that comprise the
oscillator.
FIGURE 4-1. Oscillator Internal and External Circuitry
This oscillator is active under normal power or during power
down. It stops only in the event of a power failure with the
oscillator disabled (see “Oscillator Activity” on page 56), or
when battery backup power drops below V
BAT
(Min) (see
TABLE 14-1 "Recommended Operating Conditions" on
page 232).
If oscillator input is from an external source, input should be
driven rail to rail and should have a nominal 50% duty cycle.
In this case, oscillator output X2C should be disconnected
and internal oscillator should be disabled.
External capacitor values should be chosen to provide the
manufacturer’s specified load capacitance for the crystal
when combined with the parasitic capacitance of the trace,
socket, and package, which can vary from 0 to 8 pF. The
rule of thumb in choosing these capacitors is:
C
L
= (C1 * C2) ÷ (C1 + C2) + C
PARASITIC
C2 > C1
C1 can be trimmed to achieve precisely 32768.0 Hz after insertion.
Start-up time for this oscillator may vary from two to seven
seconds due to the high Q of the crystal. The parameters
below describe the crystal requirements:
Parallel, resonant, tuning fork (N cut) or XY bar
Q ≥ 35000
Load Capacitance (C
L
) 9 to 13 pF
Accuracy and temperature coefficients are user defined.
4.1.2 Timekeeping
Time is kept in BCD or binary format as determined by bit 2
(DM) of Control Register B (CRB). Either 12 or 24 hour representation for the hours can be maintained as determined
by bit 1 of CRB. When changing formats, the time registers
must be re-initialized to the corresponding data format.
Daylight savings time and leap year exceptions are handled
by the timekeeping function. When bit 0 (the Daylight Saving Enable bit, DSE) of CRB is set to 1, time advances from
1:59:59 AM to 3:00:00 on the first Sunday in April, and
changes from 1:59:59 to 1:00:00 on the last Sunday of October. In leap years, February is extended to 29 days.
Updating
Timekeeping is performed by hardware updating a pre-programmed time value once per second. The preprogrammed
values are written by the user to the following locations:
The values for seconds, minutes, hours, day of week, date
of Month, month and year are located in the common storage area in all three memory banks (See TABLE 4-19
"Banks 0, 1 and 2 - Common 64-Byte Memory Map" on
page 89). The century value is located in the Century Register (See Section 4.2.7 on page 59).
Users must ensure that reading or writing to the time storage registers does not coincide with a system update of
these registers, which would cause invalid and unpredictable results.
There are several ways to avoid this contention. Four options follow:
Method 1 - Set the SET bit (bit 7 of the CRB register) to 1.
This takes a “snapshot” of the internal time registers and
loads it into the user copy. If user copy registers have
been updated, the user copy updates the internal registers when the SET bit goes from 1 to 0. This mechanism
enables loading new time parameters into the RTC.
Method 2 - Access after detection of an Update-Ended in-
terrupt.
This implies that an update has just completed and
there are 999 msec remaining until the next occurrence.
Method 3 - Poll Update-In-Progress (UIP) (bit 7 in Control
Register A).
The update occurs 244 µsec after the update-in-
progress bit goes high. Therefore if a 0 is read, there is
a minimum of 244µs in which the time is guaranteed to
remain stable.
Method 4 - Use a periodic interrupt to determine if an up-
date cycle is in progress.
The periodic interrupt is first set to a desired period. Pe-
riodic interrupt appearance then indicates there is a period of (Period of periodic interrupt ÷ 2 + 244 µsec)
remaining until another update occurs.
20 MΩ
Internal
External
R
EXT
X1C
X2C
C1 C2
R
EXT
= 120 KΩ
C1 = 10 pF
C2 = 33 pF
C
PARASITIC
= 8 pF
Page 55
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
RTC OVERVIEW
55
www.national.com
Alarms
The timekeeping function may generate an alarm when the
current time reaches a stored alarm time. After each RTC
time update, the seconds, minutes, hours, day-of-month
and month storage registers are compared with their counterparts in the alarm storage registers.
If equal, the alarm flag is set in Control Register C (CRC). If
the Alarm Interrupt Enable bit is set in Control Register B,
then setting the Alarm flag generates an RTC interrupt.
Any alarm register may be set to a “Don’t Care” state by setting bits 7,6 to 11. This results in periodic alarm activation at
an increased rate whose period is that of the Don’t Care
register, e.g., if bits 7,6 of the hours register is set to 11(its
”Don’t care” value), the alarm will be activated every hour. If
the day-of-month register is set to its ”Don’t care” value, the
alarm will be activated daily at the time defined by the remaining alarm values.
The seconds, minutes and hours alarm registers are shared
with the wake-up function, and are located at indexes 01h,
03h and 05h of banks 0, 1 and 2, respectively. The day-ofmonth alarm register is configurable. It may reside in bank
0 or bank 1. Upon first power-on, it resides in bank 1, Index
49h. The register is configured via the DADDR register in
bank 2. The month alarm register is also configurable and
may reside in bank 0 or bank 1. Upon first power-on, it resides in bank 1, Index 4Ah. The register is configured via
the MADDR register in bank 2. For more details, see the
RTC and APC Registers.
The century register is configurable. It may reside in bank 0
or bank 1. Upon first power-on, it resides in bank 1, Index
48h. The register is configured via the CADDR register in
bank 2. For more details, see the RTC and APC Registers.
4.1.3 Power Management
The host PC and PC87317VUL power is supplied by the
system power supply voltage, V
DD.
See FIGURE 4-2
"PC87317VUL Power Supplies".
A trickle voltage (V
CCH
) from the external AC power supply
powers the RTC and APC under normal conditions. The
V
DD
voltage reaches the RTC/APC as a sense signal, to de-
termine the presence or absence of a valid V
DD
supply.
A battery backup voltage V
BAT
maintains RTC/APC time-
keeping and backup memory storage when the V
CCH
voltage is absent, due to power failure or disconnection of the
external AC input power supply.
The APC function produces the
ONCTL signal, which con-
trols the V
DD
power supply voltage. (See Section 4.4.1 "The
ONCTL Flip-Flop and Signal" on page 62.)
To ensure proper operation, a 500 mV differential is needed
between V
CCH
and V
BAT
.
See FIGURE 4-3 "Typical Battery Configuration". No external diode is required to meet the UL standard, due to the internal serial resistor.
FIGURE 4-3. Typical Battery Configuration
System Bus Lockout
As the RTC switches to battery power, all input signals are
locked out so that the internal registers can not be modified
externally.
Power Up Detection
When system power is restored after a power failure, the
power failure lock condition continues for a delay of 62
msec (minimum) to 125 msec (maximum) after the RTC
switches from battery power to system power.
The power failure lock condition is switched off immediately
in the following situations:
●
If the Divider Chain Control bits (DV2-0, bits 6-4 in Control Register A) specify any mode other than 010, 100 or
011, all input signals are enabled immediately upon detection of system voltage above that of the battery voltage.
Host PC
Power Supply Module
Backup
External AC Power
V
DD
V
CCH
VDD Power
V
DD
Sense
V
CCH
Power
V
BAT
Power
RTC
and
APC
Modules
PC87317VUL
Battery
FIGURE 4-2. PC87317VUL Power Supplies
ONCTL
PC87317VUL
V
BAT
1µF
V
CCH
V
CCH
Page 56
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
56
THE RTC REGISTERS
www.national.com
●
When battery voltage is below 1 volt and MR is 1, all input signals are enabled immediately upon detection of
system voltage above that of battery voltage. This also
initializes registers at indexes 00h through 0Dh.
●
If the VRT bit (bit 7 in Control Register D) is 0, all input
signals are enabled immediately upon detection of system voltage above that of battery voltage.
Oscillator Activity
The RTC internal oscillator circuit is active whenever power
is supplied to the RTC with the following exceptions:
●
Software wrote 000 or 001 to the Divider Chain Control bits (DV2-0), i.e., bits 6-4, of Control Register A,
and the RTC is supplied by V
BAT,
or
●
The RTC is supplied by V
BAT
and the VRT bit of Con-
trol Register D is 0.
These conditions disables the oscillator.
When the oscillator becomes inactive, the APC is disabled.
4.1.4 Interrupt Handling
The RTC logic device has a single Interrupt Request line,
IRQ, which handles three interrupt conditions. The Periodic,
Alarm, and Update-Ended interrupts are generated (
IRQ is
driven low) if the respective enable bits in Control Register
B are set when an interrupt event occurs.
Reading RTC Control Register C (CRC) clears all interrupt
flags. Thus, it is recommended that when multiple interrupts
are enabled, the interrupt service routine should first read
and store the CRC register, then deal with all pending interrupts by referring to this stored status.
If an interrupt is not serviced before a second occurrence of
the same interrupt condition, the second interrupt event is
lost. FIGURE 4-5 "Interrupt/Status Timing" on page 57 illustrates interrupt and status timing in the PC87317VUL.
4.2 THE RTC REGISTERS
The RTC registers can be accessed at any time during nonbattery backed operation. The registers are listed in TABLE
4-1 "RTC Control Registers" on page 53 and described in
detail in the sections that follow.
The RTC registers and the RAM cannot be written to before
reading the VRT bit (bit 7 of the Section 4.2.4 "RTC Control
Register D (CRD)" on page 58), thus preventing bank selection and other functions. The user must read the VRT bit as
part of the startup activity in order to be able to access the
RTC/APC registers.
For registers with reserved bits, the “Read-Modify-Write”
technique should be used.
4.2.1 RTC Control Register A (CRA)
The CRA register controls periodic interrupt rate selection
and bank selection.
Bits 3-0 - Periodic Interrupt Rate Select (RS3-0)
These read/write bits select one of fifteen output taps
from the clock divider chain to control the rate of the periodic interrupt. See TABLE 4-2 "Periodic Interrupt Rate
Encoding" below and FIGURE 4-5 "Interrupt/Status Timing" on page 57.
Master reset does not affect these bits.
TABLE 4-2. Periodic Interrupt Rate Encoding
Bits 6-4 - Divider Chain Control (DV2-0)
These read/write bits control the configuration of the divider chain for timing generation and memory bank selection, as shown in TABLE 4-3 "Divider Chain Control
and Bank Selection" on page 57.
Master reset does not affect these bits.
RS3-0
3 2 1 0
Periodic Interrupt Rate
0 0 0 0 none
0 0 0 1 3.90625 msec
0 0 1 0 7.8125 msec
0 0 1 1 122.070 µsec
0 1 0 0 244.141 µsec
0 1 0 1 488.281 µsec
0 1 1 0 976.562 µsec
0 1 1 1 1.953125 msec
1 0 0 0 3.90625 msec
1 0 0 1 7.8125 msec
1 0 1 0 15.625 msec
1 0 1 1 31.25 msec
1 1 0 0 62.5 msec
1 1 0 1 125 msec
1 1 1 0 250 msec
1 1 1 1 500 msec
RS2
DV0
DV2
UIP
76543210
Index 0Ah
Power-Up
Required
RTC Control
00000100
RS0
RS3
DV1
RS1
(CRA)
Reset
Register A
Page 57
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
THE RTC REGISTERS
57
www.national.com
TABLE 4-3. Divider Chain Control and Bank Selection
Bit 7 - Update in Progress (UIP)
This read only bit is not affected by reset.
0: An update will not occur within the next 244 µsec.
Bit 7 (the SET bit) of Control Register B (CRB) is 1.
1: Timing registers are updated within 244 µsec.
1. The oscillator stops in this case only in the event
of a power failure.
4.2.2 RTC Control Register B (CRB)
This register enables the selection of various time and date
options, as well as the use of interrupts.
FIGURE 4-4. CRB Register Bitmap
Bit 0 - Daylight Savings Enable (DSE)
Master reset does not affect this read/write bit.
0: Disables the daylight savings feature.
1: Enables daylight savings feature, as follows:
In the spring, time advances from 1:59:59 to
3:00:00 on the first Sunday in April.
In the fall, time returns from 1:59:59 to 1:00:00 on
the last Sunday in October.
Bit 1 - 24 or 12 Hour Mode
This is a read/write bit that is not affected by reset.
0: Enables 12 hour format.
1: Enables 24 hour format.
Bit 2 - Data Mode (DM)
This is a read/write bit that is not affected by reset.
0: Enables BCD format.
1: Enables binary format.
DV2-0
6 5 4
Selected
Bank
Configuration
0 0 0 Bank 0 Oscillator Disabled
1
0 0 1 Bank 0
Oscillator Disabled
1
0 1 0 Bank 0 Normal Operation
0 1 1 Bank 1 Normal Operation
1 0 0 Bank 2 Normal Operation
1 0 1 Undefined Test
1 1 0 Bank 0 Divider Chain Reset
1 1 1 Bank 0 Divider Chain Reset
DM
UIE
AIE
PIE
SET
76543210
0000
DSE
24 or 12 Hour Mode
Unused
0
Index 0Bh
Power-Up
Required
RTC Control
(CRB)
Reset
Register B
A-B Update In Progress (UIP) bit high before update occurs = 244 µsec
D-C Periodic interrupt to update = Period (periodic int) / 2 + 244 µsec
C-E Update to Alarm Interrupt = 30.5 µs
UIP Update In Progress status bit
UF Update-Ended Interrupt Flag (Update-Ended Interrupt if enabled)
PF Periodic Flag (Periodic Interrupt if enabled)
AF Alarm Flag (Alarm Interrupt if enabled)
Flags (and IRQ) are reset at the conclusion of Control Register C (CRC) read or by reset.
UIP bit of CRA
UF bit of CRC
PF bit of CRC
AF bit of CRC
C
D
E
AB
FIGURE 4-5. Interrupt/Status Timing
Page 58
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
58
THE RTC REGISTERS
www.national.com
Bit 3 - Unused
This bit is defined as “Square Wave Enable” by the
MC146818 and is not supported by the RTC. This bit is
always read as 0.
Bit 4 - Update-Ended Interrupt Enable (UIE)
Master reset forces this read/write bit to 0.
0: Disables generation of the Update-Ended interrupt.
1: Enables generation of the Update-Ended interrupt.
This interrupt is generated at the time an update
occurs.
Bit 5 - Alarm Interrupt Enable (AIE)
Master reset forces this read/write bit to 0.
0: Disables generation of the alarm interrupt.
1: Enables generation of the Alarm interrupt. The
alarm interrupt is generated immediately after a
time update in which the Seconds, Minutes, Hours
Day-of-month and Month time equal their respective alarm counterparts.
Bit 6 - Periodic Interrupt Enable (PIE)
Master reset forces this read/write bit to 0.
0: Disables generation of the Periodic interrupt.
1: Enables generation of the Periodic interrupt. Bits 3-
0 of Control Register A (CRA) determine the rate of
the Periodic interrupt.
Bit 7 - Set Mode (SET)
Master reset does not affect this read/write bit.
0: The timing updates occur normally.
1: The user copy of time is “frozen”, allowing the time
registers to be accessed without regard for an occurrence of an update.
4.2.3 RTC Control Register C (CRC)
This register indicates the status of interrupt request flags.
FIGURE 4-6. CRC Register Bitmap
Bits 3-0 - Reserved
These bits are reserved and always return 0000.
Bit 4 - Update-Ended Interrupt Flag (UF)
Master reset forces this read-only bit to 0. In addition,
this bit is reset to 0 when this register is read.
0: No update has occurred since the last read.
1: Time registers have been updated.
Bit 5 - Alarm Interrupt Flag (AF)
Master reset forces this read-only bit to 0.
0: No alarm was detected since the last read.
1: An alar m condition was detected. This bit is reset
to 0 when this register is read.
Bit 6 - Periodic Interrupt Flag (PF)
Master reset forces this read-only bit to 0. In addition,
this bit is reset to 0 when this register is read.
0: Indicates no transition occurred on the selected tap
since the last read.
1: A transition occurred on the selected tap of the di-
vider chain.
Bit 7 - Interrupt Request Flag (IRQF)
This read-only bit is the inverse of the value on the
IRQ
output signal of the RTC/APC.
0:
IRQ is inactive (high).
1:
IRQ is active (low) and any of the following conditions exists: both PIE and PF are 1; both AIE and
AF are 1; both UIE and UF are 1. (PIE, AIE and
UIE are bits 6, 5 and 4, respectively of the CRB
register.)
4.2.4 RTC Control Register D (CRD)
This register indicates the validity of the RTC RAM data.
FIGURE 4-7. CRD Register Bitmap
Bits 6-0 - Reserved
These bits are reserved and always return 0.
Bit 7 - Valid RAM and Time (VRT)
The VRT bit senses the voltage that feeds this logical
device (V
CCH
or V
BAT
) and indicates whether or not it
was too low since the last time this bit was read. If it was
too low, the RTC and RAM data are not valid.
This read-only bit is set to 1 when this register is read.
0: The voltage that feeds the APC/RTC logical device
was too low.
1: The RTC and RAM data are valid.
WARNING:
If V
CCH
ramps down at a rate exceeding 1 V/msec, it
may reset this bit.
UF
AF
PF
IRQF
76543210
0000000
0000
Reserved
Index 0Ch
Power-Up
Required
RTC Control
(CRC)
Reset
Register C
VRT
76543210
00000000
0000000
Index 0Dh
Power-Up
Required
RTC Control
(CRD)
Reset
Register D
Reserved
Page 59
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
APC OVERVIEW
59
www.national.com
4.2.5 Date-of-Month Alarm Register (DMAR
This register contains the Day-of-Month alarm setting and
its “don’t care” enable bits. Upon first power-up it is located
at Bank 1, Index 49h and is initialized to C0h.
This register can be relocated anywhere in bank 0 or bank
1. Its location is programmed via the Section 4.5.16 "Dayof-Month Alarm Address Register (DADDR)" on page 77.
Master Reset does not affect the Day-of-Month Alarm register.
FIGURE 4-8. DMAR Register Bitmap
Bits 5-0 - Date-of-Month Alarm Bits
These read/write bits hold the Day-of-Month alarm value.
These six bits are set to the value of 0 upon first power-up,
and are unaffected by system resets. The legal values for
these six bits are, 00 to 31 in BCD format, and 00 to 1F in
binary format. Other values may cause unpredictable results. The BCD or Binary format is set by the DM bit, explained in Section 4.2.2 "RTC Control Register B (CRB)" on
page 57.
Bits 7,6 - “Don’t Care” Control Bits
The Day-of-Month Alarm is “Don’t Care” when bits 6 and 7
are set to 11.
4.2.6 Month Alarm Register (MAR)
This register contains the Month Alarm setting and its “don’t
care” enable bits.
Upon first power on, the Month Alarm register is located at
bank 1, Index 4Ah and is initialized to C0h. The default value is not guaranteed to any other location of the Month
Alarm Register.
This register can be relocated anywhere in bank 0 or bank
1. Its location is programmed via the MADDR Register, as
explained in Section 4.5.17 "Month Alarm Address Register
(MADDR)" on page 77.
Master Reset does not affect the Month Alarm register.
FIGURE 4-9. MAR Register Bitmap
Bits 5-0 - Day-of-Month Alarm Bits
These read/write bits hold the month alarm value. These six
bits are set to the value of 0 upon first power-up, and are unaffected by system resets. The legal values for these six bits
are, 01 to 12 in BCD format, and 00 to 0C in binary format.
Other values may cause unpredictable results. The BCD or
Binary format is set by the DM bit of the CRB Register, as
explained in Section 4.2.2 "RTC Control Register B (CRB)"
on page 57.
Bits 7,6 - “Don’t Care” Control Bits
The Month Alarm is “Don’t Care” when bits 6 and 7 are set
to 11.
4.2.7 Century Register (CR)
This register holds the century.
Upon first power on, the Century Register resides in Bank
1, Index 48h and holds 00h.This register can be relocated
anywhere in bank 0 or bank 1. Its location is programmed
via the CADDR Register, as described in Section 4.5.18
"Century Address Register (CADDR)" on page 77.
Master Reset does not affect this register.
FIGURE 4-10. MAR Register Bitmap
Bits 7 - 0
These read/write bits hold the century value.
4.3 APC OVERVIEW
Advanced Power Supply Control (APC) is implemented
within the RTC logical device. It enables the PC to power up
automatically in response to pre-programmed external
76543210
00000011
Power-Up
Required
Date-of-Month Alarm
(DMAR)
Reset
Register
Day-of-Month
Alarm Bits
“Don’t Care” control bits
Relocatable Index
in Bank0 or Bank1
76543210
00000011
Power-Up
Required
Month Alarm
(MAR)
Reset
Register
Month
Alarm Bits
“Don’t Care” control bits
Relocatable Index
in Bank0 or Bank1
76543210
00000000
Power-Up
Required
Century
(CR)
Reset
Register
Century
Bits
Relocatable Index
in Bank0 or Bank1
Page 60
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
60
APC OVERVIEW
www.national.com
events, or to power down in an orderly, controlled manner.
The APC assumes the function of the physical power supply
On/Off switch, which is replaced by a momentary switch
that enables the user to signal requests for power-state
changes to the APC.
The APC device is powered at all times that external AC
power or battery backup power are connected to the RTC
device. This is true even though the PC may be switched off
or disconnected from the external AC power outlet, in which
case the APC device is active but does not activate system
power. The APC device controls the power state of the entire PC system in response to various events (including the
power-on or power-off switch event).
WARNING:
The APC device does not function if the 32.768 KHz oscillator is not running.
The APC function produces four output signals:
●
the ONCTL signal - to activate the system power supply
●
the Power-Off-Request (POR) - an interrupt request
signal designed to enable software-controlled power
off activity
●
the SCI interrupt request - to comply with ACPI specifications for system power management.
●
The LED signal - to drive an external LED status indicator
ONCTL: The ONCTL signal is intended to activate or deactivate the system power supply.
The
ONCTL’s value depends on the following:
●
External events
●
Programmable parameter settings
●
The system’s state when an external event occurs
●
The state of the system’s power supply.
POR: The APC generates a Power-Off-Request (POR) (as
an interrupt request signal) in response to various “Power
Off events”, including the “Switch Off event” generated
when the power switch is manually toggled. This enables
various user-selectable choices of system response when
returning from a power Failure, or a software controlled exit
procedure (analogous to the autoexec.bat startup procedure in DOS operating systems) with automatic activation
of preprogrammed features such as system status backup,
system activity logging, file closing and backup, remote
communications termination, print completion, etc.
SCI: The APC meets ACPI requirements, with additional
optional features (see “ACPI Compliance” below). An SCI
interrupt is generated to send ACPI-relevant notifications to
the host operating system. (See “The SCI Signal” on page
69.)
LED: The APC supplies a programmable LED signal output
that may directly drive an external LED to indicate system
status under various power states (See TABLE 4-7 "LED
signal outputs" on page 68).
NOTE: The APC can distinguish between two events of the
same type if a minimum time of 2.5 periods of the 32Khz
clock passed between their arrivals. Thus, if the APC detects an event, and another event of the same nature occurs
once again in less than 70us from the previous event, the
APC might not detect the second event, i.e., the event will
be lost.
ACPI Compliance
The PC87317 supports all the minimum requirements of the
ACPI spec (Rev 1.0):
●
Power Management Timer.
●
Power Button.
●
Real Time Clock Alarm.
●
Suspend modes via software emulation.
●
Plug-and-Play SCI.
The following optional features are also supported:
●
Global Lock mechanism.
●
General Purpose events.
●
Day-of-Month Alarm.
●
Century byte.
Several programmable General Purpose Power Managements events may be utilized to wake-up the system or to
generate interrupts, as listed in “General Purpose Power
Management Events” on page 68. The module includes a
Power Management timer that can generate interrupt requests.
TABLE 4-4 "APC Control and Status Register List" lists the
registers used for Automatic Power Supply Control (APC) in
the PC87317VUL.
TABLE 4-4. APC Control and Status Register List
The ACPI Fixed Registers include four groups of registers,
as listed below.
Index Mnemonic Description
40h APCR1 APC Control Register 1
41h APCR2 APC Control Register 2
49h APCR3 APC Control Register 3
4Ah APCR4 APC Control Register 4
4Bh APCR5 APC Control Register 5
4Ch APCR6 APC Control Register 6
4Dh APCR7 APC Control Register 7
42h APSR APC Status Register
4Eh APSR1 APC Status Register 1
47h RLR RAM Lock Register
4Fh DADDR Day-of-Month Alarm Address
Register
50h MADDR Month Alar m Address Register
51h CADDR Century Address Register
43h WDW Wake up Day of Week
44h WDM Wake up Date of Month
45h WM Wake up Month
46h WY Wake up Year
48h WC Wake up Century
Page 61
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
APC OVERVIEW
61
www.national.com
TABLE 4-5. ACPI Fixed Register List.
The Power Management events are user-controlled via the
PM1 Event Registers: the enable bits in these registers give
the user the ability to tailor system response by enabling or
disabling Power Management options, and monitoring them
via the status bits. (e.g. Power Button, Real-Time Clock
Alarm or Wake State enabling or monitoring).
The PM Control registers enable control of system operation options (such as Power Button or Real-TIme CLock enabling, or reading Power Button override status).
The Power Management Timer registers house the values
of the Power Management Timer, which enables elapsedtime detection for power-state control.
The General Purpose Event registers give the user control
over the General Purpose Power Management events: the
enable bits in these registers give the user the ability to tailor system response by enabling or disabling the events
from triggering interrupt requests, and monitoring them via
the status bits.
The Offsets indicated in the ACPI Fixed Register list are the
address offset values to be added to the Base Address values, to obtain the real addresses of the registers. The Base
Addresses are user-defined, at the following locations:
PM1 Event Registers (Status and Enable registers) base
address is located at the PM1 Event Base Address Bits 7-0
register and PM1 Event Base Address Bits 15-8 register of
the Power Management device (Logical Device 8).
PM1 Control Registers base address is located at the PM1
Control Base Address Bits 7-0 register and PM1 Control
Base Address Bits 15-8 register of the Power Management
device (Logical Device 8)
PM TImer Registers base address is located at the PM
Timer Base Address Bits 7-0 register and PM Timer Base
Address Bits 15-8 register of the Power Management device (Logical Device 8)
General Purpose Event Registers base address is located at the General Purpose Status Base Address Bits 7-0
register and General Purpose Status Base Address Bits 158 register of the Power Management device (Logical Device
8)
User Selectable Parameters
The APC function allows tailoring the system response to
power up, power down, power failure and battery operation
and other events.
User-selectable parameters include:
●
Enabling various external events to wake up the system. See Section 4.4.2 "Entering Power States" on
page 65.
●
Wake-up time for an automatic system wake-up. See
“Predetermined Wake-Up” on page 68.
●
Type of system recovery after a Power Failure state.
See “The MOAP Bit” on page 62 and APCR6 bit 6 and
7 in “Bits 7,6 - Extended Wakeup options after Power
Failure.” on page 76.
●
Immediate or delayed Switch Off shutdown. See “The
SWITCH Input Signal” on page 67.
●
5 or 21 second time-out fail-safe shutdown. See “The
SWITCH Input Signal” on page 67.
●
LED signal response.
●
Mechanism for recognizing system power states. See
Section 4.3.2 "System Power Switching Logic" on
page 62.
●
Trigger characteristics for General Purpose events.
4.3.1 System Power States
The system power state may be one of: No Power, Power
On, Power Off (suspended) or Power Failure. These states
are illustrated in FIGURE 4-11 "APC State Diagram" on
page 64. TABLE 4-6 "System Power States" on page 62 indicates the power-source combinations for each state. No
other power-source combinations are valid.
In addition, the power sources and distribution for the entire
PC system are described in FIGURE 4-2 "PC87317VUL
Power Supplies" on page 55.
WARNING:
It is illegal for V
DD
to be present when V
CCH
is absent.
Offset Mnemonic Description
PM1 Event Registers (Status and Enable registers)
00h PM1_STS_LOW PM 1 Status Low Byte Register
01h PM1_STS_HIGH PM 1 Status High Byte Register
02h PM1_EN_LOW PM 1 Enable Low Byte Register
03h PM1_EN_HIGH PM 1 Enable High Byte Register
PM1 Control Registers
00h PM1_CNT_LOW PM 1 Control Low Byte Register
01h PM1_CNT_HIGH PM 1 Control High Byte Register
PM TImer Registers
00h PM1_TMR_LOW PM Timer Low Byte Register
01h PM1_TMR_MID PM Timer Middle Byte Register
02h PM1_TMR_HIGH PM Timer High Byte Register
03h PM1_TMR_EXT PM Timer Extended Byte Register
General Purpose Event Registers
00h GP1_STS0 General Purpose 1 Status 0 Reg.
01h GP1_STS1 General Purpose 1 Status 1 Reg.
02h GP1_STS2 General Purpose 1 Status 2 Reg.
03h GP1_STS3 General Purpose 1 Status 3 Reg.
04h GP1_EN0 General Purpose 1 Enable 0 Reg.
05h GP1_EN1 General Purpose 1 Enable 1 Reg.
06h GP1_EN2 General Purpose 1 Enable 2 Reg.
07h GP1_EN3 General Purpose 1 Enable 3 Reg.
08h GP2_EN0 General Purpose 2 Enable 0 Reg.
09h-
0Bh
Reserved
0Ch SMI_CMD SMI Command Register
0Dh-
0Fh
Reserved
Page 62
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
62
APC DETAILED DESCRIPTION
www.national.com
TABLE 4-6. System Power States
No Power
This state exists when no external or battery power is connected to the device. This condition will not occur once a
backup battery has been connected, except in the case of a
malfunction. The APC undergoes initialization only when
leaving this state.
Power On
This is the normal state when the PC is active. This state
may be initiated by various events in addition to the normal
physical switching on of the system. In this state, the PC
power supply is powered by external AC power and produces V
DD
and V
CCH
. The PC system and the PC87317VUL
device are powered by V
DD
, with the exception of the RTC
logical device, which is powered by V
CCH.
Power Off (Suspended)
This is the normal state when the PC has been switched off
and is not required to be active, but is still connected to a
live external AC input power source. This state may be initiated directly or by software, and causes the PC system to
be powered down. The RTC logical device remains active,
powered by V
CCH
.
Power Failure
This state occurs when the external power source to the PC
stops supplying power, due to disconnection or power failure on the external AC input power source. The RTC continues to maintain timekeeping and RAM data under battery
power (V
BAT
), unless the oscillator stop bit was set in the
RTC. In this case, the oscillator stops functioning if the system goes to battery power, and timekeeping data becomes
invalid.
4.3.2 System Power Switching Logic
In the Power On state, the PC host is powered by the power-supply voltage V
DD
. From this state the system enters
the Power Off state if the conditions for this state occur (See
Section 4.4.3 on page 67), or the Power Failure state if external power is removed.
In the Power Off state, the PC hosts does not receive power
from the system power supply, except for RTC and APC
which receive V
CCH.
The system may enter the Power On
state if the conditions for this state occur (see Section 4.4.3
on page 67), or the Power Failure state if external power is
removed.
Knowing the system’s state is important for the correct detection of the Switch Events. The PC87317 distinguishes
between Power On and Power Off as follows:
●
VDD exists implies power On
●
V
CCH
exists and VDD does not implies Power Off.
V
DD
must be at least V
BAT
+500 mvolt, to prevent the possibility of the APC entering the Power Failure state and
switching to battery power.
If V
BAT
falls below 2V with V
CCH
absent, the oscillator, the
timekeeping functions and the APC all stop functioning.
If no external or battery-backup power is available, the sys-
tem enters a No Power state. Upon leaving this state, the
system is initialized.
4.4 APC DETAILED DESCRIPTION
4.4.1 The
ONCTL Flip-Flop and Signal
The APC checks when activation or deactivation conditions
are met, and drives the
ONCTL signal accordingly. This sig-
nal activates the system power supply.
ONCTL is physically
generated as the output of the
ONCTL set-reset flip-flop.
The state of the
ONCTL flip-flop depends on the following:
●
Presence of activation conditions
●
The status of the Mask ONCTL Activation (MOAP) bit
and APCR6 bits 6 and 7
●
Power source condition
●
The preceding state of ONCTL
The Preceding State of the
ONCTL Signal
A power failure may occur when the system is active or inactive. The
ONCTL flip-flop maintains the state of the
ONCTL signal at the time of the power failure. When power
is restored, the
ONCTL signal returns the system to a state
determined by the saved status of
ONCTL and the saved
value of the MOAP bit if this option is selected via APCR6
bits 6 and 7.
The MOAP Bit
The Mask
ONCTL Activation in Power Failure (MOAP) bit
(bit 4 of APCR1) is controlled by software. It makes it possible to choose the desired system response upon return
from a power failure and decide whether the system remains inactive until it is manually switched on, or resumes
the state that prevailed at the time of the power failure, including enabling of “wake-up” events, as described in the
next section.
Logical Conditions that Define the Status of the
ONCTL
Flip-Flop
The logical conditions described here set or reset the
ONCTL flip-flop. They reflect the events described in Section 4.4.3 on page 67.
Conditions that put the
ONCTL flip-flop in a 0 state (active
ONCTL signal):
●
Switch On event occurred.
●
RTC Alarm Status bit (bit 2 of PM1_STS_HIGH) and
RTC Alarm Enable bit (bit 2 of PM1_EN_HIGH)are set
●
Match Enable bit is 1 (APCR2 bit 0) and there is a
match between the real-time clock and the time specified in the pre-determined date and time registers.
V
DD
V
CCH
V
BAT
Power State
−− − No Power
−− + Power Failure
− + + or - Power Off
+ + + or - Power On
+ − + or - Illegal State
Page 63
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
APC DETAILED DESCRIPTION
63
www.national.com
User software must ensure unused date/time fields are
coherent, to ensure the comparison of valid bits gives
the correct results.
●
The RING enable bit (bit 3 of APCR2) is 1 and one of
the following occurs:
— Bit 2 of APCR2 is 0, and a high-to-low transition is
detected on the
RING input pin.
— Bit 2 of APCR2 is 1 and a train of pulses is detected
on the
RING input pin.
●
RI1,2 Enable bits (bits 3 and 4 of APCR2) are 1 and a
high to low transition is detected on the
RI1,2 input
pin(s).
●
Software On Command by asserting bit 7 of APCR2
●
PME1 Status bit (GP1_STS0 bit 0) and PME1 Enable
bit (GP1_EN0 bit 0) are set.
●
PME2 Status bit (GP1_STS0 bit 1) and PME2 Enable
bit (GP1_EN0 bit 1) are set.
●
IRRX1 Status bit (GP1_STS0 bit 2) and IRRX1 Enable
(GP1_EN0 bit 2) bit are set.
●
IRRX2 Status bit (GP1_STS0 bit 3) and IRRX2 Enable
(GP1_EN0 bit 3) bit are set.
●
GPIO10 Status bit (GP1_STS0 bit 6) and GPIO10 Enable bit (GP1_EN0 bit 6) are set.
Conditions that put the
ONCTL flip-flop in a 1 state (inactive
ONCTL signal):
●
Switch Off Delay Enable bit is 0 and Switch Off event
occurred. (The Switch-Off event can inactivate
ONCTL
only when SCI/
POR bit is 0 - see PM1_CNT_LOW
register in the ACPI Fixed registers). The Power Button Enable bit has no effect - see PM1_EN_HIGH register in the ACPI Fixed registers.
●
Switch Off Delay Enable bit is 1 and Fail-safe Timer
reached terminal count. (The Failsafe Timer’s ter minal
count can inactivate
ONCTL only when SCI/POR bit is
0 - see PM1_CNT_LOW register in the ACPI Fixed
registers). The Power Button Enable bit has no effect see PM1_EN_HIGH register in the ACPI Fixed registers.
●
Software Off Command by asserting bit 5 of APCR1.
Power Override
When the debounced
SWITCH is 0 and Vdd exists (both)
for more than 3.95 seconds or 4 seconds (the time is selected via bit 3 of the APCR7 register),
ONCTL is deasserted
regardless of the Fail-safe Timer state. Once a power button override is detected, the
ONCTL can be asserted again
only after Vdd does not exist.
For the last 500 msec
ONCTL is asserted but Vdd does not
exist. This reset condition overrides any set condition of the
ONCTL flip-flop. This condition can reset the ONCTL flipflop, only if enabled via bit 4 of APCR7 register.
When Activate and Inactivate conditions of the
ONCTL flipflop occur at the same time, the Activate overrides the Inactivate. Exception to this are the following Inactivate conditions. They override any Activate condition that occurs at
the same time:
●
The SWITCH pin is 0 for more than 3.95 seconds or 4
seconds. See detailed description above.
●
For the last 500 msec ONCTL is asserted but Vdd
does not exist. See detailed description above.
When bit 4 of APCR7 register is 0,
ONCTL can be asserted
only after 1 second passed since it was deasserted. A wake
up event that happens during this 1 second, will activate the
ONCTL signal at the end of the 1 second. Off events are ignored during the 1 second period.
When bit 4 of APCR7 register is 1,
ONCTL can be asserted
immediately after it was deasserted. (i.e., a wake-up event
can activate
ONCTL immediately after ONCTL was deas-
serted.)
The t
ONH
(see TABLE 14-69 "RING Trigger and ONCTL
Timing" on page 265) delay on power-up, when power returns after power failure, always occurs, regardless of bit 4
of APCR7 register.
Page 64
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
64
APC DETAILED DESCRIPTION
www.national.com
APC Inactive
APC Active
Initial Values
No
V
BAT
V
CCH
V
CCH
Switch On Event
A
Switch Off Event or
Software Off Command
APC Active
Programmed Values
Power
Power
Power
Power
Enabled Wake Up Event
Switch On Event Only
A
4
2
1
3
Off Event
Off
Off
On
Failure
Power
Failure
Power
On
Power
Off
Power
APC Programming
(can occur if V
DD
is not
A
A
APC Programming
1
V
CCH
∗ MOAP ∗ (Power Failure Bit = 0)
(can occur if V
DD
is not controlled by ONCTL)
2
3
V
CCH
∗ MOAP ∗ (APCR6 bits 7,6 = 0,0) ∗ (Power Failure Bit = 1)
V
CCH
∗ ( (MOAP ∗ (APCR6 bits 7,6 = 0,0) ∗ (Power was On) ) or
4
(MOAP ∗ (APCR6 bits 7,6 = 0,0) ∗ (Time Match During Power Failure) ) or
( (APCR6 bits 7,6 = 1,0) ∗ (Time Match During Power Failure) ) )
V
CCH
∗ ( (MOAP ∗ (APCR6 bits 7,6 = 0,0) ∗ (Power was Off) ) or
(APCR6 bits 7,6 = 0,1) )
( (APCR6 bits 7,6 = 1,0) ∗ (No Time Match During Power Failure) ) or
A
FIGURE 4-11. APC State Diagram
V
BAT
V
CCH
∗
V
BAT
V
CCH
∗
V
BAT
V
CCH
∗ V
BAT
V
CCH
∗ V
BAT
V
CCH
∗ V
BAT
controlled by
ONCTL)
V
CCH
∗ V
BAT
V
CCH
∗ V
BAT
V
CCH
∗
V
BAT
V
CCH
∗ V
BAT
V
CCH
∗
V
BAT
V
CCH
∗
V
BAT
Page 65
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
APC DETAILED DESCRIPTION
65
www.national.com
4.4.2 Entering Power States
Power Up
When power is first applied to the RTC, (referred to as first
Power on) the APC registers are initialized to the default
values defined in the register descriptions. (See TABLE
4-22 "Bank 2 Registers - APC Memory Bank" on page 90).
This situation is defined by the appearance of V
BAT
or V
CCH
with no previous power.
The APC powers up when the RTC supply is applied from
any source and is always in an active state. The RTC may
be powered up, but inactive; this occurs if bit 0 of the register at index 30h (see Section 2.3 "THE CONFIGURATION
REGISTERS" on page 29) of this logical device is not set.
In this situation, the APC registers are not accessible, since
they are only accessed via the RTC. This is also true of the
general-purpose battery-backed RAM.
Power Off Request (
POR)
The APC allows a maskable or non-maskable interrupt on
the
POR pin. This interrupt enables the user to perform an
orderly exit procedure, automatically performing housekeeping functions such as file backups, printout completion
and communications terminations, before powering down.
See FIGURE 4-12 "POR, SCI and ONCTL Generation" on
page 66.
The
POR signal can be asserted by the following events:
●
Power Button (Switch-Off Event).
●
ACPI Global Lock Release.
●
Sleep Enable.
●
SMI Command.
●
PME1 Event.
●
PME2 Event.
●
IRRX1 Event.
●
IRRX2 Event.
●
GPIO12 Event.
●
GPIO13 Event.
●
GPIO10 Event.
●
P12 Event.
An event will assert
POR, only if its corresponding status
and enable bits are set.
Each of the events (PME1 to P12, in the list above) has a
corresponding status bit in the GP1_STS0 register. The
events can be enabled via two registers. When bit 0 of the
PM1_CNT_LOW register is 0, the events can be enabled
via their corresponding bit in the GP1_EN0 register. A bit in
the GP2_EN0 register can always enable its corresponding
event (All registers referred to in this paragraph are in the
ACPI Fixed registers).
The PC87317 also supports the SMI Command of the ACPI. Thus, when bit 5 (status) and bit 6 (enable) of the ACPI
Support register are '1',
POR is asserted (see Power Management registers, Logical Device 8). This is the SMI Command event. It is initiated by the ACPI OS that writes to the
SMI Command register.
The PC87317 supports the Global Lock mechanism of the
ACPI. Thus, when bit 2 (status) and bit 3 (enable) of the
ACPI Support register are set to 1,
POR is asserted (see
Power Management registers, Logical Device 8). This is the
ACPI Global Lock Release event. It is initiated by the ACPI
OS that writes a 1 to the ACPI Global Lock Release bit in
the PM1_CNT_LOW register (see Fixed ACPI registers).
The system can enter suspend modes via software emulation. When bit 0 (status) and bit 1 (enable) of the ACPI Support register are set to 1,
POR is asserted (see Power
Management registers, Logical Device 8). This is the Sleep
Enable event. It is initiated by the ACPI OS that writes a 1
to the Sleep Enable bit in the PM1_CNT_HIGH register (see
Fixed ACPI registers).
The Power Button (Switch-Off Event) can assert the POR
pin, only when the SCI/
POR bit is 0 (see PM1_CNT_LOW
register in the ACPI Fixed registers). It will assert the
POR
pin, when a Switch-Off event is detected, regardless of the
Power Button Enable bit (see PM1_EN_HIGH register in
the ACPI Fixed registers).
When
POR is in level mode (bit 2 of APCR1 register is 1), it
is asserted until the corresponding event’s status bit or enable bit is cleared. The exception to this is the Switch-Off
event. For that event,
POR will be deasserted by the Level
POR Clear Command bit (bit 3 of the APCR1 register). Note
that if level events are configured, the
POR must be configured to level mode. When any of the following events is enabled,
POR must also be configured to level mode:
●
Writes to the SMI Command register.
●
Write 1 to the ACPI Global Lock Release bit of the
PM1_CNT_LOW register
●
Write 1 to the Sleep Enable bit of the
PM1_CNT_HIGH register.
Upon Master Reset, the
POR signal is in TRI-STATE.
Power Failure
The APC is in a Power Failure state when it is powered by
V
BAT
, without V
CCH
.
Upon entering a Power Failure state, the following occurs:
●
All APC inputs are masked (high).
●
These signals remain masked until one second after
exit from the Power Failure state, i.e., one second after
switching from V
BAT
to V
CCH
.
The
ONCTL pin state is internally saved, and ONCTL is
forced inactive.System Recovery after Power Failure
The nature of the system recovery after power failure is set
by bits 6 and 7 of the APCR6 control register (See Section
4.5.13 "APC Control Register 6 (APCR6)" on page 75).
In all cases, the system can be switched on manually after
power returns.
Three selectable automatic options exist:
●
the system response is controlled by the MOAP bit
●
the system remains inactive after power returns until
an enabled “wake-up” event occurs
●
the system is awakened when power returns by a new
enabled wake-up event, or by an enabled “match
event” that occurred while power was down.
Page 66
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
66
APC DETAILED DESCRIPTION
www.national.com
A "wake-up" event is any event that can activate the ONCTL
signal. The "wake-up" events are masked for one second
upon return from Power Failure, except the Match event
and the RTC Alarm event. These two events are not
masked but if they occur during Power Failure or during the
one second period after return from Power Failure, they will
assert
ONCTL only at the end of that one second period.
If the system is selected to respond to the MOAP bit value
(Mask
ONCTL Activation in Power Failure, i.e., bit 4 of the
APCR1 register - see Section 4.5.1 "APC Control Register
1 (APCR1)" on page 70) via the APCR6 bit 6 and 7 settings,
the following occurs:
One second after power returns, the
ONCTL signal reverts to its saved state, if the MOAP bit is cleared to 0. If the
MOAP bit is set to 1,
ONCTL remains inactive. If MOAP = 0
when the one second delay expires, new events can activate
ONCTL, unless a time match occurs during Power Fail-
ure, in which case the APC “remembers” to activate
ONCTL
at the end of the one second delay.
If the MOAP bit (bit 4 of APCR1) and the Power Failure
bit (bit 7 of APCR1) are both 1, then only the Switch On
event can activate
ONCTL.
SCI
Generator
POR
Generator
ONCTL
Generator
RTC Alarm
Power
Management
Timer
BIOS
Global
Lock
Release
ACPI
Global
Lock
Release
SLEEP
Enable
SELECT
rising/falling
high/low
SELECT
rising/falling
high/low
SWITCH
Event Type
Pulse/train
SELECT
MATCH
Fail-Safe
Timer
GPIO 12,13
P12
PME2,1
IRRX2,1
GPIO10
Restart
Stop
V
DD
SWITCH OFF EVENT
SWITCH ON EVENT
FIGURE 4-12.
POR, SCI and ONCTL Generation
SMI
Command
EXISTS
SWITCH
RING
RI2,1
Page 67
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
APC DETAILED DESCRIPTION
67
www.national.com
4.4.3 System Power-Up and Power-Off Activation
Event Description
The APC may activate the host power supply when the following “wake-up” events occur:
●
Physical On/Off switch is depressed and VDD is absent.
●
Preprogrammed wake-up time arrives.
●
Communications input is detected on a modem.
●
Ring signal is detected at a telephone input jack.
●
General Purpose Power Management wake-up event
occurs.
The PC may be powered down by the following events:
●
Physical On/Off switch is depressed with VDD present,
or depressed continuously for longer than 4 seconds.
●
Software controlled power down.
●
Fail-safe power down in the event of power-down software hang-up. (See “Switch-Off Event” below.)
●
ONCTL is active but VDD doesn’t exist for 500 ms
(See
ONCTL description).
The
SWITCH Input Signal
This signal provides two events: Switch On and Switch Off.
In both, the physical switch line is debounced, i.e., the signal state is transferred only after 14 to 16 msec without transitions, which ensures the switch is no longer bouncing. See
FIGURE 4-13.
Switch-On Event - Detection of a high to low transition on
the debounced
SWITCH input pin, when VDD does not
exist. The Switch-On event is masked (not detected) for
one to two seconds after V
DD
is removed.
The Switch-On event sets the Switch-On event detect
bit to 1 (bit 2 of APSR1).
Switch-Off Event - Detection of a high to low transition on
the debounced
SWITCH input pin, when VDD exists.
The Switch-Off event sets the Switch-Off Event Detect
bit (bit 5 in APSR) to 1.
Switch-Off Delay - When the Switch-Off Delay Enable bit
(bit 6 in register APCR2) is 0, the Switch-Off event powers the system off immediately, i.e., the
ONCTL output
pin is deactivated immediately.
When the Switch-Off Delay Enable bit is 1, occurrence of a
Switch-Off event will trigger a Fail-safe Timer countdown of
5 or 21 seconds. (Countdown length is set by bit 1 of the
APCR1 register. See Section 4.5.1 "APC Control Register
1 (APCR1)" on page 70.) If it is allowed to complete this
countdown (i.e., no reset or retrigger occurs while counting
down), the Fail-safe Timer sets the
ONCTL signal high (inactive). This Fail-safe Timer countdown may also be triggered (or retriggered if a countdown is already in progress)
by writing a 1 to bit 0 of APCR1. Triggering sets the timer to
its initial countdown value and starts the countdown sequence. Switch-Off events occurring while a countdown is
in progress will not affect the countdown.
Switch-Off Event detection activates the Power-Off Request (
POR) that triggers a user-defined interrupt routine to
conduct housekeeping activities prior to powering down.
(The user may also detect the Switch-Off Event by polling
the Switch-Off Detect bit, rather than by using the interrupt
routine). The user must ensure that the power-off routine
duration does not exceed the 5 or 21 second Switch-Off Delay. If required, a user routine may deactivate the countdown by setting the Fail-safe Timer Reset Command bit, (bit
6 of APCR1). Setting this bit will stop and reset the Fail-safe
Timer, thus preventing the fail-safe timer from causing power off before completion.
If the power-off routine gets “hung up”, and the timer was
not stopped and reset, then after the delay time has elapsed
the timer will conclude its countdown and activate power off
(deactivate
ONCTL).
The Fail-safe Timer is stopped, and reset, by writing 1 to the
Fail-safe Timer reset bit (bit 6 of APCR1). Switch-off events
detected while the timer is already counting are ignored. If,
V
DD
goes down while the Fail-safe Timer is counting, the
timer is stopped and reset, and
ONCTL is not deactivated.
POR may be asserted on a Switch-Off Event. It can be configured as either edge or level triggered, according to the
APCR1 register, bit 2. In edge mode, it is a negative pulse,
and in level mode it remains asserted until cleared by a level
POR Clear Command (bit 3 of the APCR1 register, see FIGURE 4-12 "POR, SCI and ONCTL Generation" on page
66). Selection of
POR on the GPIO22/POR pin is via the SuperI/O Configuration 2 register (at index 22h). Selection of
the
POR output buffer is via GPIO22 output buffer control
bits (Port 2 Output Type and Port 2 Pull-up Control registers). See TABLE 9-2 "The GPIO Registers, Bank 0" on
page 216.
FIGURE 4-13. Switch Event Detector
Debounce
Switch-On Event
Switch-Off Event
SWITCH
V
DD
V
CCH
Falling
Edge
Detector
VDD Exists
POR
Edge or Trigger POR Select
Level POR Clear
APCR1 Register, Bit 2
APCR1 Register, Bit 3
Page 68
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
68
APC DETAILED DESCRIPTION
www.national.com
Predetermined Wake-Up
The second, minute, and hour values of the pre-determined
wake-up times are contained in the Seconds Alarm, Minutes Alarm, and Hours alarm registers, respectively (indexes 01h, 03h and 05h of banks 0, 1 and 2). The Day-ofWeek, Day-of-Month, Month, Year and Century of the predetermined date are held in bank 2, registers indexes 43h46h and 48h. These eight registers are compared with the
corresponding Seconds, Minutes, Hours, Day-of-Week,
Day-of-Month, Month and Year, in all banks, register indexes 00, 02, 04, 06, 07, 08, 09 and the Century register which
can be located anywhere in bank 0 or bank 1 - its location
is programmed via the Century Address Register in bank 2.
(The Century bit value - bit 6 0f RTC Control Register d - is
not used for this function).
Any Wake Up register in bank 2 (Index 43h-46h and 48h)
may be set to a "Don't Care" state by setting bits 7,6 to 11.
This results in periodic Match Event activation at an increased rate whose period is that of the Don’t Care location,
e.g., if the Wake Up Day-of-Week location and the Wake Up
Month are both set to a Don’t Care, a Match Event will be
activated once a month during the specified year.
Ring Signal Event
An incoming telephone call is an event that may activate a
transfer from the Power-Off state to a Power-On state, in order to deal with the pending incoming voice, fax or modem
communication.
The PC87317VUL can detect a
RING pulse falling edge or
a
RING pulse train with a frequency of at least 16 Hz, that
lasts at least 0.19 seconds.
During
RING pulse train detection, the existence of falling
edges on
RING is monitored during time slots of 62.5 msec
(16 Hz cycle time). A
RING pulse train detect event occurs
if falling edge(s) of
RING were detected in three consecutive time slots, following a time slot in which no falling edge
of
RING was detected.
This method of detecting a
RING pulse train filters out (does
not detect) a
RING pulse train of less then 11 Hz, might de-
tect a
RING pulse train of 11 Hz to 16 Hz, and guarantees
detection of a
RING pulse train of at least 16 Hz.
RI1,2 Event
High to Low transitions on
RI1 or RI2 indicate communications activity on the UART inputs, and these conditions may
be used as events to “wake-up” the system.
General Purpose Power Management Events
The APC supports additional events that can wake-up the
system from the power off state, or generate an interrupt if
the system is in the power on state.
An event is defined as the detection of falling edge, rising
edge, low level, or high level on a specific signal. Each signal’s event is configurable via software.
The following events may wake up the system from the
Power Off state, or generate an interrupt if the system is in
the Power On state:
●
PME1 Event defined by bits 2-0 of the APCR4 register.
●
PME2 Event defined by bits 5-3 of the APCR4 register.
●
IRRX1 Event defined by bits 2-0 of the APCR5 register.
●
IRRX2 Event defined by bits 5-3 of the APCR5 register.
The following events may generate an interrupt if the system is in the Power On state:
●
GPIO12 Event defined by bits 2-0 of the APCR6 register.
●
GPIO13 Event defined by bits 5-3 of the APCR6 register.
●
GPIO10 Event defined by bits 7-5 of the APCR3 register.
●
P12 Event defined by bits 2-0 of the APCR7 register.
Each of the events has a corresponding status bit in the
GP1_STS0 register. The events can be enabled via two
registers: GP1_EN0 register and GP2_EN0 register.
An event will wake up the system or generate an interrupt,
only if its corresponding status and enable bits are set.
LED Signal
This output signal enables an external LED to be driven directly by the PC87317, and may be programmed to give
various responses under various power conditions.
Three signal outputs may be selected:
●
High - Impedance (HI-Z)
●
Drive 0 level
●
a 1 hz “blink” signal, alternating between the previous
two outputs.
The High Impedance output will leave the LED unlit. The
Drive 0 value will switch on an external LED connected to
an external power source and grounded by the LED signal
output.
The outputs of this signal depend on programmed values
selected at bits 6 and 7 of APCR4, and on the prevailing
power state.
Signal outputs under all conditions are listed in the following
table:
TABLE 4-7. LED signal outputs
The LED signal is functional, when V
DD
and V
CCH
exist or
when only V
CCH
exists. When only V
BAT
exists, the LED signal is not functional (output is set to HI-Z) but its control bits
are saved. Thus, when V
CCH
is applied again, the LED signal returns to the previous state. Upon first power-on (application of one of the voltages V
BAT
or V
CCH
when no
previous voltage was present), the LED signal is configured
to be in the high-impedance state. The One Hz blink requires a 32.768 KHz clock.
APCR4
Bits
7 6
LED State
V
CCH
V
BAT
only
0 0 HI-Z HI-Z
0 1 Drive 0 HI-Z
1 0 1 Hz blink HI-Z
1 1 Reserved HI-Z
Page 69
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
APC REGISTERS
69
www.national.com
The SCI Signal
The SCI interrupt is used to send ACPI relevant notifications
to the host Operating System. The following events assert
the SCI signal:
●
RTC alarm
●
Power Button (Switch-Off event)
●
Timer Carry
●
BIOS Global Lock Release
●
PME1 Event
●
PME2 Event
●
IRRX1 Event
●
IRRX2 Event
●
GPIO12 Event
●
GPIO13 Event
●
GPIO10 Event
●
P12 Event.
An event will assert SCI, only if its corresponding status and
enable bits are set. Exception to this is the Switch-Off event,
as explained below.
Each of the general purpose events (PME1 to P12, in the
list above) has a corresponding status bit in the GP1_STS0
register. When bit 0 of the PM1_CNT_LOW register is 1, the
events can be enabled via their corresponding bit in the
GP1_EN0 register.
The Timer status bit is in the PM1_STS_LOW register. It is
enabled via the PM1_EN_LOW register. The RTC alarm
status bit and the Power Button status bit are in the
PM1_STS_HIGH register. They are enabled via the
PM1_EN_HIGH register. Note that the Power Button status
bit holds two events: Switch-Off and Switch-On. Only the
Switch-Off event can assert SCI. The Switch-On events
have no effect. During the suspended state (defined in the
Wake Status bit of the PM1_STS_HIGH register), SwitchOff events always assert SCI, regardless of the Power Button Enable bit.
When bit 5 of the PM1_STS_LOW register and bit 5 of the
PM1_EN_LOW register are set to 1, SCI is asserted (see
the ACPI Fixed registers). This is the BIOS Global Lock Release event. It is initiated by the BIOS that writes a 1 to the
BIOS Global Lock Release bit in the ACPI Support register
(see Power Management registers, Logical Device 8).
SCI is a level interrupt. Its polarity is software programmable (see Section 2.4.7 "SuperI/O Configuration 3 Register
(SIOC3)" on page 39). It is asserted until the corresponding
event’s status bit are both set to 1. Exception to this is the
Switch-Off event during suspend mode that asserts (or
deasserts) SCI according to its status bit, regardless of its
enable bit.
Upon Master Reset, the SCI signal is not configured to any
IRQ pin. At that time, SCI can be active due to the RTC
alarm or Switch-Off event.
The SCI signal can be routed (via software) to one of the following IRQ pins: IRQ1, IRQ3-IRQ12, IRQ14-IRQ15 (see
Section 2.4.7 "SuperI/O Configuration 3 Register (SIOC3)"
on page 39). Note that the SCI is a shareable interrupt, i.e.,
it can share the IRQ pin with another device (and the two interrupt sources can be enabled at the same time). The SCI
can share the IRQ pin with another device provided they are
configured in the same manner (e.g., both are configured as
active high level interrupts). This IRQ pin should be configured as an open-drain output. It is the software’s responsibility to share the correct device with the SCI.
The following table summarizes the various events and
their connection to
ONCTL, POR and SCI
TABLE 4-8. Trigger Events for
ONCTL, POR and SCI
Power Management Timer
The Power Management Timer is a 24-bit fixed rate running
count-up timer that runs off a 3.579545 MHz clock (derived
from the 14.31818 MHz clock input). Upon Master Reset,
the timer is disabled since its clock is disabled (bit 0 of the
PMC3 register, logical device 8). It is functional only when
V
DD
exists.
The Power Management Timer operates only if a 14.31818
MHz clock is fed via the X1 pin and the chip is configured to
work with the on-chip clock multiplier.
When the most significant bit (bit #23) of the timer changes
from either high to low or low to high, the Timer status bit
(PM1_STS_LOW register) is set to 1. An SCI interrupt is
generated, when both the Timer status bit and the Timer enable bit (PM1_EN_LOW register) are set to 1.
The Power Management Timer can be read via four byte
registers, placed in consecutive addresses:
PM1_TMR_LOW, PM1_TMR_MID, PM1_TMR_HIGH and
PM1_TMR_EXT registers. For proper operation, the
PM1_TMR_LOW register should be placed on a doubleword boundary.
Whenever the PM1_TMR_LOW register is read, the
PM1_TMR_LOW, PM1_TMR_MID and PM1_TMR_HIGH
registers are updated with the internal timer’s value. The
PM1_TMR_EXT register always reads 0. This scheme
guarantees that a coherent time is read.
4.5 APC REGISTERS
The APC registers reside in the APC bank 2 memory. The
RAM Lock register also resides in this bank. See TABLE
4-22 "Bank 2 Registers - APC Memory Bank" on page 90.
Power Management
Trigger Event
ONCTL
POR
SCI
RTC Alarm
++
Power Button
+++
Power Management Timer
Carry
+
BIOS Global Lock Release
+
ACPI Global Lock Release
+
Sleep Enable
+
PME2,1 Event
+++
IRRX2,1 Event
+++
GPIO10 Event
+++
GPIO12/13 Events
++
P12 Event
++
SMI Command
+
Page 70
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
70
APC REGISTERS
www.national.com
The APC registers are not affected by Master Reset. They
are initialized to 0 only when power is applied for the first
time, i.e., application of one of the voltages V
BAT
or V
CCH
when no previous voltage was present.
4.5.1 APC Control Register 1 (APCR1)
FIGURE 4-14. APCR1 Register Bitmap
Bit 0 - Fail-safe Timer Trigger Command
This write-only bit returns 0 when read. Writing a 1 to
this bit resets the failsafe timer and triggers a 5 or 21
second countdown, as selected by bit 1 of this register.
0: Ignored.
1: 5 or 21 second failsafe countdown triggered.
Bit 1 - Switch Off Delay Option
0: 5 seconds.
1: 21 seconds.
Bit 2 -
POR Edge or Level Select
0: Edge
POR.
1: Level
POR. Once POR is asserted, it remains as-
serted until cleared by Level
POR Clear Command
(bit 3).
Bit 3 - Level
POR Clear Command
This is a write-only non-sticky bit. Read returns 0.
0: Ignored.
1:
POR output signal is deactivated.
Bit 4 - Mask
ONCTL Activation if Power Fail (MOAP)
The function of this bit is enabled by extended wakeup
options settings in APCR6, bits 6 and 7.
0: When power returns and APCR6 bit 6 and 7 are
00, sets the system to the power state that existed
when power failed.
1: While the Power Failure bit (bit 7 of APCR1) is set,
mask
ONCTL activation, except as a result of a
Switch On Event.
Bit 5 - Software Off Command (SOC)
This bit is write-only and non-sticky. Read returns 0.
0: Ignored.
1:
ONCTL output signal is deactivated.
Bit 6 - Fail-safe Timer Reset Command
This bit is write-only and non-sticky. Read returns 0.
0: Ignored.
1: Fail-safe timer is stopped and reset.
Bit 7 - Power Failure
Set to 1 when RTC/APC switches from V
CCH
to V
BAT
.
Cleared to 0 by writing 1 to this bit. Writing 0 to this bit
has no effect.
4.5.2 APC Control Register 2 (APCR2)
FIGURE 4-15. APCR2 Register Bitmap
Bit 0 - Timer Match Enable (TME)
0: Pre-determined date or time event is ignored.
1: Match between the RTC and the pre-determined
date and time activates the
ONCTL output signal.
See MOAP (bit 4) of APCR1 and APCR6 bit 6,7 for
an overriding case.
Bit 1 -
RING Source Select (RSS)
0:
RING source is RING/XDCS signal, regardless of
X-bus Data Buffer (XDB) select bit of SuperI/O
Configuration 1 register.
1:
RING source is GPIO23/RING signal.
Bit 2 -
RING Pulse or Train Detection Mode (RPTDM)
0: Detection of
RING pulse falling edge.
1: Detection of
RING pulse train above 16 Hz for 0.19
sec.
Bit 3 -
RING Enable (RE)
0:
RING input signal is ignored.
1:
RING detection activates the ONCTL output signal,
unless it is overridden by the MOAP bit, bit 4 of the
APCR1 register and bits 6,7 0f APCR6.
Bit 4 -
RI1 Enable (R1E)
0:
RI1 input signal is ignored.
1: A high to low transition on the
RI1 input pin acti-
vates the
ONCTL output pin.
See MOAP (bit 4) of APCR1 and APCR6 bit 6,7 for
an overriding case.
Bit 5 -
RI2 Enable (R2E)
0:
RI2 input signal is ignored.
1: A high to low transition on the
RI2 input pin acti-
vates the
ONCTL output pin.
POR Edge or Level Select
MOAP
SOC
Fail-safe Timer Reset Command
Power Failure
76543210
00000000
Failsafe Timer Trigger Cmd.
Switch Off Delay Option
Level
POR Clear Command
Bank 2
Power-Up
Required
APC Control
(APCR1)
Reset
Register 1
Index 40h
RPTDM
R1E
R2E
SODE
Software On Command
76543210
TME
RSS
RE
00000000
Bank 2
Power-Up
Required
APC Control
(APCR2)
Reset
Register 2
Index 41h
Page 71
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
APC REGISTERS
71
www.national.com
See MOAP (bit 4) of APCR1 and APCR6 bit 6,7 for
an overriding case.
Bit 6 - Switch Off Delay Enable (SODE)
0:
ONCTL output pin is deactivated immediately after
the Switch Off event.
1: After the Switch Off event,
ONCTL output signal is
deactivated after the 5 or 21 seconds Switch Off
delay.
Bit 7 - Software On Command
This bit is write-only and non-sticky. Read returns 0.
0: Ignored
1:
ONCTL output signal is activated.
4.5.3 APC Status Register (APSR)
Bits 5-0 in this register are cleared to 0, when this register
is read.
FIGURE 4-16. APSR Register Bitmap
Bit 0 - Timer Match Detect (TMD)
This bit is set to 1 when the RTC reaches the pre-determined date, regardless of the Timer Match Enable bit
(bit 0 of APCR2). After first Power-Up, the RTC and the
pre-determined date, are 0 and so this bit is set. It is recommended to clear this bit by reading this register after
first Power-Up.
Bit 1 -
RING Detect (RID)
This bit is set to 1 when a high to low transition is detected on the
RING input pin and bit 2 of APCR2 is 0, or
when a
RING pulse train is detected on the RING input
pin and bit 2 of APCR2 is 1, regardless of the status of
the
RING enable bit.
Bit 2 -
RI1 Detect
This bit is set to 1 when a high to low transition is detected on the
RI1 input signal, regardless of the RI1 Enable
bit.
Bit 3 -
RI2 Detect
This bit is set to 1 when a high to low transition is detected on the
RI2 input pin, regardless of the RI2 Enable bit.
Bit 4 - Fail-Safe Timer Detect (FTD)
This bit is set to 1 when the Fail-safe timer reaches terminal count.
Bit 5 - Switch Off Event Detect (SOED)
This bit is set to 1 when a Switch Off event is detected,
regardless of the Switch Off Delay Enable bit.
Bit 6 - Reserved
Bit 7 -
RING Status Bit (RS)
Holds the instantaneous value of the selected
RING pin.
4.5.4 Wake up Day of Week Register (WDWR)
This register contains the Wake up Day of Week settings.
FIGURE 4-17. WDWR Register Bitmap
Bits 5-0 Wake up Day of Week Bits
These bits contain the day of week setting. Values may
be 01 to 07 in BCD format or 01 to 07 in Binary format.,
where sunday = 01. See “Predetermined Wake-Up” on
page 68.
Bits 7,6 - Don’t Care control bits
When both bits are set to 11, these bits set the Wake up Day
of Week field to a “don’t care” state
RI1 Detect
FTD
SOED
Reserved
RS
76543210
TMD
RID
RI2 Detect
Bank 2,
Power-Up
Required
APC Status
(APSR)
Reset
Register
100000
Index 42h
76543210
00000011
Power-Up
Required
Wake up Day of Week Register
Reset
Wake up Day-of-Week Bits
“Don’t Care” control bits
(WDWR)
Bank 2
Index 43h
Page 72
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
72
APC REGISTERS
www.national.com
4.5.5 Wake up Date of Month Register (WDMR)
This register contains the Wake up Date of Month settings.
FIGURE 4-18. WDMR Register Bitmap
Bits 5-0 Wake up Date of Month Bits
These bits contain the Date of Month setting. Values
may be 01 to 31 in BCD format or 01 to 1F in Binary format.
See “Predetermined Wake-Up” on page 68.
Bits 7,6 - Don’t Care control bits
When both bits are set to 11, these bits set the Wake up
Date of Month field to a “don’t care” state
4.5.6 Wake up Month Register (WMR)
This register contains the Wake up Month settings.
FIGURE 4-19. WMR Register Bitmap
Bits 5-0 Wake up Month Bits
These bits contain the Month setting. Values may be 01
to 12 in BCD format or 01 to 0C in Binary format. See “Predetermined Wake-Up” on page 68.
Bits 7,6 - Don’t Care control bits
When both bits are set to 11, these bits set the Wake up
Month field to a “don’t care” state
4.5.7 Wake up Year Register (WYR)
This register contains the Wake up Year settings.
FIGURE 4-20. WYR Register Bitmap
Bits 5-0 - Wake up Year Bits
These bits contain the Year setting. Values may be 01
to 99 in BCD format or 01 to 63 in Binary format. See “Predetermined Wake-Up” on page 68.
Bits 7,6 - Don’t Care control bits
When both bits are set to 11, these bits set the Wake up
Year field to a “don’t care” state.
4.5.8 RAM Lock Register (RLR)
Once a non-reserved bit is set to 1 it can be cleared only by
hardware (MR pin) reset.
FIGURE 4-21. RLR Register Bitmap
Bit 2-0 - Reserved
Bit 3 - Upper RAM Block
Controls access to the upper 128 RAM bytes, accessed
via the Upper RAM Address and Data Ports of bank 1
0: This bit has no effect on upper RAM access.
1: Upper RAM Data Port of bank 1 is blocked: writes
are ignored and reads return FFh.
Bit 4 - RAM Block Read
This bit controls reads from RAM bytes 80h-9Fh (00h-
1Fh of upper RAM).
0: This bit has no effect on upper RAM access.
1: Reads from bytes 00h-1Fh of upper RAM return
FFh.
76543210
00000011
Power-Up
Required
Wake up Date-of-Month
(WDMR)
Reset
Register
Wake up Date of Month Bits
“Don’t Care” control bits
Bank 2
Index 44h
76543210
00000011
Power-Up
Required
Wake up Month
(WMR)
Reset
Register
Wake up Month Bits
“Don’t Care” control bits
Bank 2
Index 45h
76543210
00000011
Power-Up
Required
Wake up Year
(WYR)
Reset
Register
Wake up Year Bits
“Don’t Care” control bits
Bank 2
Index 46h
Reserved
RAM Block Read
RAM Block Write
RAM Mask Write
RAM Lock
76543210
Reserved
Reserved
Upper RAM Block
000
00000000
Bank 2,
Power-Up
Required
RAM Lock
(RLR)
Reset
Register
Index 47h
Page 73
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
APC REGISTERS
73
www.national.com
Bit 5 - RAM Block Write
This bit controls writes to bytes 80h-9Fh (00h-1Fh of upper RAM).
0: This bit has no effect on upper RAM access.
1: Writes to bytes 00h-1Fh of upper RAM are ignored.
Bit 6 - RAM Mask Write
This bit controls writes to all RTC RAM.
0: This bit has no effect on RAM access.
1: Wr ites to bank 0 RAM and to upper RAM are ig-
nored.
Bit 7 - RAM Lock
0: This bit has no effect on RAM access.
1: Read and write to locations 38h-3Fh of all banks
are blocked. Writes are ignored, and reads return
FFh.
4.5.9 Wake up Century Register (WCR)
This register contains the Wake up Century settings.
FIGURE 4-22. WCR Register Bitmap
Bits 5-0 Wake up Century Bits
These bits contain the Century setting. Values may be
01 to 99 in BCD format or 01 to 63 in Binary format. See
“Predetermined Wake-Up” on page 68.
Bits 7,6 - Don’t Care control bits
When both bits are set to 11, these bits set the Wake up
Century field to a “don’t care” state
4.5.10 APC Control Register 3 (APCR3)
This register defines device I/O pin designations, and
GPIO10 event polarity/edge settings.
This register in not affected by Master reset. Upon first Power-Up, it is initialized to A0h.
FIGURE 4-23. APCR3 Register Bitmap
Bit 0 - PME1 or GPIO16 Pin Select
This bit selects PME1 or GPIO16 to be connected to I/O
pin.
When PME1 is not selected, its enable bit (bit 0 of
GP1_EN) should be cleared to 0.
0: GPIO16 selected.
1: PME1 selected.
Bit 1 - PME2 or GPIO15 pin select
This bit selects PME2 or GPIO15 to be connected to I/O
pin.
When PME2 is not selected, its enable bit (bit 1 of
GP1_EN) should be cleared to 0.
0: GPIO15 selected.
1: PME2 selected.
Bit 2 - LED or
CS0 Pin select
This bit selects LED or
CS0 to be connected to I/O pin.
0:
CS0 selected.
1: LED selected.
Bit 3 - GPIO24 or IRRX1 Pin Select
This bit selects GPIO24 or IRRX1 to be connected to I/O
pin.
When IRRX1 is not selected, its enable bit (bit 2 of
GP1_EN) must be cleared to 0.
0: IRRX1 selected.
1: GPIO24 selected.
Bit 4 - GPIO37 or IRRX2/IRSL0/ID0 Pin Select
This bit selects GPIO37 or IRRX2/IRSL0/ID0 to be connected to I/O pin. Selection between IRRX2/IRSL0/ID0
is described in the UART2 registers (device 5).
When IRRX2 is not selected, its enable bit must be
cleared to 0.
0: IRRX2/IRSL0/ID0 selected.
1: GPIO37 selected.
Bits 7-5 - GPIO10 Event Polarity/Edge Select
These bits determine the physical conditions that trig-
ger the GPIO10 General Purpose Event.
76543210
00000011
Power-Up
Required
Wake up Century
(WCR)
Reset
Register
Wake up Century Bits
“Don’t Care” control bits
Bank 2
Index 48h
LED or
CS0 select
GPIO37 or IRRX2/IRSL0/ID0 Select
76543210
PME1 or GPIO16 select
PME2 or GPIO15 select
GPIO24 or IRRX1 select
00000101
Bank 2,
Power-Up
Required
APC Control
(APCR3)
Reset
Register 3
GPIO10 Event Polarity/Edge select
Index 49h
Page 74
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
74
APC REGISTERS
www.national.com
TABLE 4-9. GPIO10 Event settings select
4.5.11 APC Control Register 4 (APCR4), Bank 2, Index
4Ah
This register configures the LED output signal operational
mode and PME2,1 event polarity/edge settings.
Upon first Power-Up, this register is initialized to 2Dh. The
bit settings are unaffected by Master Reset.
FIGURE 4-24. APCR4 Register Bitmap
Bits 2-0 - PME1 Event Polarity/Edge Select
These bits determine the physical conditions that trigger
the PME1 Power Management Event.
These bits are unaffected by Master Reset.
TABLE 4-10. PME1 Event settings select
Bits 5-3 - PME2 Event Polarity/Edge Select
These bits determine the physical conditions that trigger
the PME2 Power Management Event.
These bits are unaffected by Master Reset.
TABLE 4-11. PME2 Event settings select
Bits 7,6 -
LED Configuration
These bits determine the LED output signal.
TABLE 4-12. LED Configuration settings
APCR3 bits
7 6 5
Physical trigger condition
0 0 0 Low level
0 0 1 High level
0 1 0
Reserved0 1 1
1 0 0
1 0 1 Falling Edge
1 1 0 Rising Edge
1 1 1 Falling or Rising Edge
76543210
10110100
Bank 2,
Power-Up
Required
APC Control
(APCR4)
Reset
Register 4
PME1 Event Polarity/Edge select
PME2 Event Polarity/Edge select
LED configuration
Index 4Ah
APCR4 bits
2 1 0
Physical trigger condition
0 0 0 Low level
0 0 1 High level
0 1 0
Reserved0 1 1
1 0 0
1 0 1 Falling Edge
1 1 0 Rising Edge
1 1 1 Falling or Rising Edge
APCR4 bits
5 4 3
Physical trigger condition
0 0 0 Low level
0 0 1 High level
0 1 0
Reserved0 1 1
1 0 0
1 0 1 Falling Edge
1 1 0 Rising Edge
1 1 1 Falling or Rising Edge
APCR4 bits
7 6
LED output
0 0 High Impedance
0 1 Drive 0
1 0 One Hz blink
1 1 Reserved
Page 75
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
APC REGISTERS
75
www.national.com
4.5.12 APC Control Register 5 (APCR5)
This register contains the IRRX2,1 event polarity/edge settings and configures I/O pin designations.
Upon first Power-Up this register is reset to 2Dh. The bit settings are unaffected by Master Reset.
FIGURE 4-25. APCR5 Register Bitmap
Bits 2-0 - IRRX1 Event Polarity/Edge Select
These bits determine the physical conditions that trig-
ger the IRRX1 Event.
These bits are unaffected by Master Reset.
TABLE 4-13. IRRX1 Event settings select
Bits 5-3 - IRRX2 Event Polarity/Edge Select
These bits determine the physical conditions that trigger
the IRRX2 Event.
These bits are unaffected by Master Reset.
TABLE 4-14. IRRX2 Event settings select
Bit 6 - GPIO33 or
RI2 Pin select
This pin routes signal GPIO33 or
RI2 to I/O pin.
0:
RI2 selected
1: GPIO33 selected
Bit 7 - Reserved
4.5.13 APC Control Register 6 (APCR6)
This register contains the GPIO13,12 event polarity/edge
settings and setting for extended wakeup options after power failure.
Upon first Power-Up this register is reset to 2Dh. The bit settings are unaffected by Master Reset.
FIGURE 4-26. APCR6 Register Bitmap
Bits 2-0 - GPIO12 Event Polarity/Edge Select
These bits determine the physical conditions that trig-
ger the GPIO12 Event.
These bits are unaffected by Master Reset.
TABLE 4-15. GPIO12 Event settings select
APCR5 bits
2 1 0
Physical trigger condition
0 0 0 Low level
0 0 1 High level
0 1 0
Reserved0 1 1
1 0 0
1 0 1 Falling Edge
1 1 0 Rising Edge
1 1 1 Falling or Rising Edge
APCR5 bits
5 4 3
Physical trigger condition
0 0 0 Low level
0 0 1 High level
0 1 0
Reserved0 1 1
1 0 0
76543210
10110100
Bank 2,
Power-Up
Required
APC Control
(APCR5)
Reset
Register 5
IRRX1 Event Polarity/Edge selec
t
IRRX2 Event Polarity/Edge select
GPIO33 or
RI2 select
Reserved
Index 4Bh
1 0 1 Falling Edge
1 1 0 Rising Edge
1 1 1 Falling or Rising Edge
APCR6 bits
2 1 0
Physical trigger condition
0 0 0 Low level
0 0 1 High level
0 1 0
Reserved0 1 1
1 0 0
1 0 1 Falling Edge
1 1 0 Rising Edge
1 1 1 Falling or Rising Edge
APCR5 bits
5 4 3
Physical trigger condition
76543210
10110100
Bank 2,
Power-Up
Required
APC Control
(APCR6)
Reset
Register 6
GPIO12 Event Polarity/Edge
GPIO13 Event Polarity/Edge select
select
Extended wake-up options after Power failure
Index 4Ch
Page 76
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
76
APC REGISTERS
www.national.com
Bits 5-3 -GPIO13 Event Polarity/Edge Select
These bits determine the physical conditions that trigger
the GPIO13 Event.
These bits are unaffected by Master Reset.
TABLE 4-16. GPIO13 Event settings select
Bits 7,6 - Extended Wakeup options after P ower Failure.
These bits determine the system wake-up behavior after return from Power failure, as follows:
TABLE 4-17. Extended Wake-up Option settings
4.5.14 APC Control Register 7 (APCR7)
This register contains the P12 event polarity/edge settings,
the Power Button Override time and the Power Supply Protect Mode bit.
Upon first Power-Up this register is reset to 05h. The bit settings are unaffected by Master Reset.
FIGURE 4-27. APCR7 Register Bitmap
Bits 2-0 - P12 Event Polarity/Edge Select
These bits determine the physical conditions that trigger
the P12 event.
Note that P12 is multiplexed with the
CS0. In any case,
it is the internal P12 port’s output that is detected.
TABLE 4-18. P12 Event settings select
Bit 3 - Power Button Override Time Select
(PWRBTNOR)
This bit selects the Power Button Override time.
0: 4 seconds override time select.
1: 3.95 seconds override time select
Bit 4 - Power Supply Protect Mode
0:
ONCTL can be asserted only after 1 second
passed since it was deasserted.
When for the last 500 msec
ONCTL is asserted but
Vdd does not exist,
ONCTL is deasserted.
1:
ONCTL can be asserted immediately after it was
deasserted.
The case in which Vdd does not exist for 500 msec
has no affect on
ONCTL.
Bits 7-5 - Reserved
APCR6 bits
5 4 3
Physical trigger condition
0 0 0 Low level
0 0 1 High level
0 1 0
Reserved0 1 1
1 0 0
1 0 1 Falling Edge
1 1 0 Rising Edge
1 1 1 Falling or Rising Edge
APCR6
Bits
7 6
Wake up Option
0 0 The MOAP bit (bit 4, APCR1) determines
system response upon return from power failure
0 1 While the Power Failure bit (bit 7, APCR1) is
set, mask
ONCTL activation except if a new
enabled event occurs after power returns.
1 0 While the Power Failure bit (bit 7, APCR1) is
set, mask
ONCTL activation except:
●
if a MATCH event occurred during power
failure
●
if a new enabled event occurs after power
returns
1 1 Reserved
APCR7 bits
2 1 0
Physical trigger condition
0 0 0 Low level
0 0 1 High level
0 1 0
Reserved0 1 1
1 0 0
1 0 1 Falling Edge
1 1 0 Rising Edge
1 1 1 Falling or Rising Edge
Power Supply Protect Mode
76543210
10100000
Bank 2,
Power-Up
Required
APC Control
(APCR7)
Reset
Register 7
P12 Event Polarity/Edge select
Reserved
PWRBTNOR
Index 4Dh
Page 77
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
APC REGISTERS
77
www.national.com
4.5.15 APC Status Register 1 (APSR1)
This is read-only register. The bit settings are unaffected by
Master Reset.
FIGURE 4-28. APSR1 Register Bitmap
Bit 0 -
Switch Pin Status
This bit is holds the value of the
SWITCH pin (before the
debouncer).
Bit 1 - Switch On event Detect
This bit is set to 1 when a Switch On event is detected,
regardless of the Power Button Enable bit (See “Bit 0 Power Button Enable (PWRBTN_EN)” on page 79). It is
cleared to 0 when the register is read.
Bits 7-2 - Reserved
4.5.16 Day-of-Month Alarm Address Register
(DADDR)
This register defines the Day-of-Month Alarm register location. The bit settings are unaffected by Master Reset.
FIGURE 4-29. DADDR Register Bitmap
Bits 6-0 - Offset Address of the Day-of-Month Alarm
Register
Bit 0 is the least significant bit of the address.
Bit 7 - Bank Select
0: Bank 0.
1: Bank 1.
Upon first power on, it is initialized to C9h.
4.5.17 Month Alarm Address Register (MADDR)
This register defines the Month Alarm register location. The
bit settings are unaffected by Master Reset.
FIGURE 4-30. MADDR Register Bitmap
Bits 6-0 - Offset Address of the Month Alarm Register
Bit 0 is the least significant bit of the address.
Bit 7 - Bank Select
0: Bank 0.
1: Bank 1.
Upon first power on, it is initialized to CAh.
4.5.18 Century Address Register (CADDR)
This register defines the Century register location. The bit
settings are unaffected by Master Reset.
FIGURE 4-31. CADDR Register Bitmap
Bits 6-0 - Offset Address of the Century Register
Bit 0 is the least significant bit of the address.
Bit 7 - Bank Select
0: Bank 0.
1: Bank 1.
Upon first power on, it is initialized to C8h.
Reserved
76543210
SWITCH pin status
Switch-On Event detect
Bank 2,
Power-Up
Required
APC Status
(APSR1)
Reset
Register 1
X0
Index 4Eh
Bank Select
76543210
10010011
Bank 2
Power-Up
Required
Day-of-Month Alarm Address
(DADDR)
Reset
Register
Day-of-Month
Alarm Address
Index 4Fh
Bank Select
76543210
01010011
Bank 2
Power-Up
Required
Month Alarm Address
(MADDR)
Reset
Register
Month
Alarm Address
Index 50h
Bank Select
76543210
00010011
Bank 2
Power-Up
Required
Century Address
(CADDR)
Reset
Register
Century Address
Index 51h
Page 78
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
78
ACPI FIXED REGISTERS
www.national.com
4.6 ACPI FIXED REGISTERS
The APCI fixed registers are divided into four groups:
●
PM1 Event registers
●
PM1 Control registers
●
PM TImer registers
●
General Purpose Event registers
These registers, their base address locations and their address offsets are listed in TABLE 4-5 "ACPI Fixed Register
List." on page 61. These registers are accessed using their
base address and the offset from the base address.
The APCI Fixed registers are reset to 0 upon first Power Up,
and are unaffected by Master Reset (unless specifically
mentioned otherwise).
Access to these registers is disabled by default and must be
enabled via FER2 (see Section 10.2.4 on page 219). The
access is not controlled by the Active register (Index 30h) of
Logical Device 2 (RTC/APC) or by the Active register (Index
30h) of Logical Device 8 (Power Management).
PM1 EVENT REGISTERS
4.6.1 Power Management 1 Status Low Byte Register
(PM1_STS_LOW)
All implemented bits are “sticky” bits: they are set to 1 by a
hardware event, and are reset to 0 only by software writing
a 1 to the bit location. (Set overrides reset in the event of
conflict).
Reserved bits are read-only, and will always return 0.
FIGURE 4-32. PM1_STS_LOW Register Bitmap
Bit 0 - Timer Status (TMR_STS)
This bit is set to 1 when the most significant bit of the
Power Management Timer (bit 23 - See
PM1_TMR_HIGH) changes from low to high or from
high to low.
Bits 4-1 - Reserved
Bit 5 - Global Lock Status (GBL_STS)
This bit is set to 1 when a 1 is written to the BIOS Global
Lock Release bit (See ACPI Support register, Power
Management registers, in Logical device 8).
Bits 7-6 - Reserved
POWER MANAGEMENT REGISTERS
4.6.2 Power Management 1 Status High Byte
Register (PM1_STS_HIGH)
All implemented bits are “sticky” bits: they are set to 1 by a
hardware event, and are reset to 0 only by software writing
a 1 to the bit location.Reserved bits are read-only, and will
always return 0. Set overrides reset.
FIGURE 4-33. PM1_STS_HIGH Register Bitmap
Bit 0 - Power Button Status (PWRBTN_STS)
This bit is set to 1 when a high to low transition is detected on the
SWITCH, regardless of the Power Button Enable bit (bit 0 of the PM1_EN_HIGH register). This bit
may be cleared to 0 by either software (as described
above) or by hardware, when the
SWITCH input signal
is 0 for over 3.95 or 4 seconds (as selected by bit 3 of
APCR7). A high to low transition on the
SWITCH input
pin that occurs while the Power Button Status bit is being cleared by software may be lost. The
SWITCH state
is detected after the debouncer.
Bit 1- Reserved
Bit 2 - Real Time Clock Status (RTC_STS)
This bit is set to 1 when the real time clock detects an
alarm condition (even if bit 5 of the RTC Control Register C is already set to 1). It is set to 1 regardless of the
Real Time Clock Enable bit (bit 2 of PM1_EN_HIGH
register). It is reset by software, as described above.
Upon first power up, this bit may be 1
Bit 3 - Power Button Override Status
(PWRBTNOR_STS)
This bit is set to 1 when the
SWITCH input pin is 0 for
over 3.95 or 4 seconds (as selected by bit 3 of APCR7),
i.e., when the user presses the power button for more
than 3.95 o r4 seconds. The
SWITCH state is detected
after the debouncer.
Bit 6-4 - Reserved
Reserved
76543210
Offset 00h
Power-Up
Required
Power Management 1 Status
(PM1_STS_LOW)
Reset
Low Byte Register
000000
0
0
TMR_STS
Reserved
GBL_STS
Reserved
76543210
Offset 01h
Power-Up
Required
Power Management 1 Status
(PM1_STS_HIGH)
Reset
High Byte Register
00X000
0
0
PWRBTN_STS
RTC_STS
PWRBTNOR_STS
Reserved
WAK_STS
Page 79
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
ACPI FIXED REGISTERS
79
www.national.com
Bit 7 - Wake Status (WAK_STS)
This bit is set to 1, when the system is in the suspended
state and an enabled Power Management event occurs.
Exception to this is the Switch-Off event that can set this
bit to '1', regardless of the Power Button Enable bit. Unlike the other status bits of this register, reset overrides
set.
Suspend state starts when Sleep Enable bit (of
PM1_CNT_HIGH register) is written with a 1.
Suspend state ends when PM1_STS_LOW,
PM1_STS_HIGH, PM1_EN_LOW, PM1_EN_HIGH,
PM1_CNT_LOW, PM1_CNT_HIGH, GP1_STS0,
GP1_EN0, GP2_EN0, PM1_TMR_LOW,
PM1_TMR_MID, PM1_TMR_HIGH or PM1_TMR_EXT is
accessed while Wake Status bit (of PM1_STS_HIGH register) is set. It ends on first access to any of these registers.
Power Management events that affect this bit: RTC
Alarm, Power Button, PME1, PME2, IRRX1, IRRX2,
GPIO10, GPIO12, GPIO13, P12 (enabled by the
GP1_EN0 register).
4.6.3 Power Management 1 Enable Low Byte
Register (PM1_EN_LOW)
Reserved bits are read-only. Read returns 0.
FIGURE 4-34. PM1_EN_LOW Register Bitmap
Bit 0 - Timer Enable (TMR_EN)
This pin is reset to 0 upon Master Reset.
0: Timer Status bit is ignored (bit 0 of the
PM1_STS_LOW register)
1: Activate the SCI signal, when the Timer Status bit
is set to 1.
Bits 4-1 - Reserved
Bit 5 - Global Lock Enable (GBL_EN)
This pin is reset to 0 upon Master Reset.
0: Global Lock Status bit is ignored (bit 5 of the
PM1_STS_LOW register)
1: Activate the SCI signal, when the Global Lock Sta-
tus bit is set to 1.
Bits 7-6 - Reserved
4.6.4 Power Management 1 Enable High Byte
Register (PM1_EN_HIGH)
Reserved bits are read-only, and will always return 0.
FIGURE 4-35. PM1_EN_HIGH Register Bitmap
Bit 0 - Power Button Enable (PWRBTN_EN)
This pin is reset to 0 upon Master Reset.
0: Power Button Status bit is ignored (bit 0 of
PM1_STS_HIGH)
1: Activate the SCI pin when the Power Button Status
bit is set to 1.
Bit 1 - Reserved
Bit 2 - Real Time Clock Alarm Enable (RTC_EN)
0: Real Time Clock Alar m status bit is ignored (bit 2 of
PM1_STS_HIGH)
1: Activate the
ONCTL pin and the SCI signal when
the Real Time Clock Status bit is set to 1.
Bits 7-3 - Reserved
Reserved
76543210
Offset 02h
Power-Up
Required
Power Management 1 Enable
(PM1_EN_LOW)
Reset
Low Byte Register
000000
0
0
TMR_EN
Reserved
GBL_EN
Reserved
76543210
Offset 03h
Power-Up
Required
Power Management 1 Enable
(PM1_EN_HIGH)
Reset
High Byte Register
000000
0
0
PWRBTN_EN
RTC_EN
Reserved
Page 80
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
80
ACPI FIXED REGISTERS
www.national.com
4.6.5 Power Management 1 Control Low Byte
Register (PM1_CNT_LOW)
Reserved bits are read-only, and will always return 0.
FIGURE 4-36. PM1_CNT_LOW Register Bitmap
Bit 0 - SCI/
POR Select (SCI_EN)
This pin routes Power Management events to either the
POR or the SCI.
The power management events affected are Power Button, PME2,1, IRRX2,1, GPIO10/12/13 or P12.
Upon Master Reset, this bit is initialized to 0.
0: Power management events are routed to
POR.
1: Power management events are routed to SCI
(which is routed to an IRQ assignment).
Bit 1 - Reserved
Bit 2 - ACPI Global Lock Release (GBL_RLS)
When a 1 is written to this bit, the ACPI GLobal Lock
Status bit is set to 1 (See ACPI Support register, Logical
device 8). This can assert
POR. Writing a 0 to this bit
has no effect on
POR.
Upon Master Reset, this bit is initialized to 0.
Bits 7-3 - Reserved
4.6.6 Power Management 1 Control High Byte
Register (PM1_CNT_HIGH)
Reserved bits are read-only, and will always return 0.
FIGURE 4-37. PM1_CNT_HIGH Register Bitmap
Bits 0,1 - Reserved
Bits 4-2 - Sleep Type (SLP_TYP)
These read/write bits do not affect the PC87317. They are
implemented only for compliance with the ACPI standard.
In the ACPI standard they define the type of suspend mode the
system should enter (when the Sleep Enable bit is set to 1).
Bit 5 - Sleep Enable (SLP_EN)
This bit is a write-only non-sticky bit. Read returns 0.
0: Ignored
1: Sleep Enable Status bit in the ACPI Support register is
set to 1 (See Logical device 8). This can assert
POR.
Bits 7,6 - Reserved
PM TIMER REGISTERS
4.6.7 Power Management Timer Low Byte Register
(PM1_TMR_LOW)
This is a read-only register.
FIGURE 4-38. PM1_TMR_LOW Register Bitmap
Bits 7-0 - Power Management Low Byte Bits
Reserved
76543210
Offset 00h
Power-Up
Required
Power Management 1 Control
(PM1_CNT_LOW)
Reset
Low Byte Register
000000
0
0
SCI_EN
Reserved
GBL_RLS
76543210
Offset 01h
Power-Up
Required
Power Management 1 Control
(PM1_CNT_HIGH)
Reset
High Byte Register
000000
0
0
Reserved
Reserved
SLP_EN
SLP_TYP
Power Management Timer Low Byte
76543210
Offset 00h
Power-Up
Required
Power Management Timer
(PM1_TMR_LOW)
Reset
Low Byte Register
xxxxxx
x
x
Page 81
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
GENERAL PURPOSE EVENT REGISTERS
81
www.national.com
4.6.8 Power Management Timer Middle Byte Register
(PM1_TMR_MID)
This is a read-only register.
.
FIGURE 4-39. PM1_TMR_MID Register Bitmap
Bits 7-0 - Power Management Timer Middle Byte bits.
4.6.9 Power Management Timer High Byte Register
(PM1_TMR_HIGH)
This is a read-only register.
.
FIGURE 4-40. PM1_TMR_HIGH Register Bitmap
Bits 7-0 - Power Management Timer High Byte bits.
4.6.10 Power Management Timer Extended Byte
Register (PM1_TMR_EXT)
This read-only register always returns 00h.
FIGURE 4-41. PM1_TMR_EXT Register Bitmap
.Bits 7-0 - Power Management Timer extended Byte bits.
4.7 GENERAL PURPOSE EVENT REGISTERS
4.7.1 General Purpose 1 Status Register (GP1_STS0)
All implemented bits are “sticky” bits: they are set to 1 by a
hardware event, and are reset to 0 only by software writing
a 1 to the bit location. Set overrides reset. Read returns 0.
Upon first power Up, these bits are initialized to 0. Upon
Master Reset, bits 4 to 7 are reset to 0.
FIGURE 4-42. GP1_STS0 Register Bitmap
Bit 0 - PME1 Status (PME1_S)
This bit is set to 1, when a PME1 event occurs, regardless of the PME1 Enable bit setting (bit 0 of the
GP1_EN0 and GP2_EN0 registers). PME1 Event is defined by bits 2-0 of the APCR4 register.
Bit 1 - PME2 Status (PME2_S)
This bit is set to 1, when a PME2 event occurs, regardless of the PME2 Enable bit setting (bit 1 of the
GP1_EN0 and GP2_EN0 registers). PME2 Event is defined by bits 5-3 of the APCR4 register.
Power Management Timer Middle Byte
76543210
Offset 01h
Power-Up
Required
Power Management Timer
(PM1_TMR_MID)
Reset
Middle Byte Register
xxxxxx
x
x
Power Management Timer High Byte
76543210
Offset 02h
Power-Up
Required
Power Management Timer
(PM1_TMR_HIGH)
Reset
High Byte Register
xxxxxx
x
x
Power Management Timer
76543210
00000000
Offset 03h
Power-Up
Required
Power Management Timer
(PM1_TMR_EXT)
Reset
Extended Byte Register
000000
0
0
Extended Byte
IRRX1_S
GPIO12_S
GPIO13_S
GPIO10_S
P12_S
76543210
PME1_S
PME2_S
IRRX2_S
00000000
Offset 00h
Power-Up
Required
General Purpose 1
(GP1_STS0)
Reset
Status Register
Page 82
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
82
GENERAL PURPOSE EVENT REGISTERS
www.national.com
Bit 2 - IRRX1 Status (IRRX1_S)
This bit is set to 1, when an IRRX1 event occurs, regardless of the IRRX1 Enable bit setting (bit 2 of the
GP1_EN0 and GP2_EN0 registers). IRRX1 Event is defined by bits 2-0 of the APCR5 register.
Bit 3 - IRRX2 Status (IRRX2_S)
This bit is set to 1, when an IRRX2 event occurs, regardless of IRRX2 Enable bit (bit 3 of the GP1_EN0 and
GP2_EN0 registers). IRRX2 Event is defined by bits 53 of the APCR5 register.
Note that if bit 3 of the GP1_EN0 register and bit 3 of the
GP2_EN0 register are both cleared to 0, spurious
IRRX2 events may be detected by this bit.
Bit 4 - GPIO12 Status (GPIO12_S)
This bit is set to 1, when a GPIO12 event occurs, regardless of the GPIO12 Enable bit setting (bit 4 of the
GP1_EN0 and GP2_EN0 registers). GPIO12 Event is
defined by bits 2-0 of the APCR6 register.
Bit 5 - GPIO13 Status (GPIO13_S)
This bit is set to 1, when a GPIO13 event occurs, regardless of the GPIO13 Enable bit setting (bit 5 of the
GP1_EN0 and GP2_EN0 registers). GPIO13 Event is
defined by bits 5-3 of the APCR6 register.
Bit 6 - GPIO10 Status (GPIO10_S)
This bit is set to 1, when a GPIO10 event occurs, regardless of the GPIO10 Enable bit setting (bit 6 of the
GP1_EN0 and GP2_EN0 registers). GPIO10 Event is
defined by bits 7-5 of the APCR3 register.
Bit 7 - P12 Status (P12_S)
This bit is set to 1, when a P12 event occurs, regardless
of the P12 Enable bit setting (bit 7 of the GP1_EN0 and
GP2_EN0 registers). P12 Event is defined by bits 2-0 of
the APCR7 register. Note that P12 is multiplexed with
CS0. In any case, the internal P12 port’s output is detected.
4.7.2 General Purpose 1 Status 1 Register
(GP1_STS1), Offset 01h
This register is reserved. Read returns 0.
4.7.3 General Purpose 1 Status 2 Register
(GP1_STS2), Offset 02h
This register is reserved. Read returns 0.
4.7.4 General Purpose 1 Status 3 Register
(GP1_STS3), Offset 03h
This register is reserved. Read returns 0.
4.7.5 General Purpose 1 Enable 0 Register
(GP1_EN0)
Upon first power Up, these bits are initialized to 0. Upon
Master Reset, bits 4 to 7 are reset to 0.
FIGURE 4-43. GP1_EN0 Register Bitmap
Bit 0 - PME1 Enable (PME1_E)
0: PME1 Status bit is ignored (bit 0 of the GP1_STS0
register).
1: When the PME1 Status bit is 1:
- Activate the
ONCTL pin.
- Activate the SCI signal or the
POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When PME1 is not selected on its corresponding
pin, this bit should be 0.
Bit 1 - PME2 Enable (PME2_E)
0: PME2 Status bit is ignored (bit 1 of the GP1_STS0
register).
1: When the PME2 Status bit is 1:
- Activate the
ONCTL pin.
- Activate the SCI signal or the
POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When PME2 is not selected on its corresponding
pin, this bit should be 0.
Bit 2 - IRRX1 Enable (IRRX1_E)
0: IRRX1 Status bit is ignored (bit 2 of the GP1_STS0
register).
1: When the IRRX1 Status bit is 1:
- Activate the
ONCTL pin.
- Activate the SCI signal or the
POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When IRRX1 is not selected on its corresponding
pin, this bit should be 0.
Bit 3 - IRRX2 Enable (IRRX2_E)
0: IRRX2 Status bit is ignored (bit 3 of the GP1_STS0
register).
1: When the IRRX2 Status bit is 1:
- Activate the
ONCTL pin.
- Activate the SCI signal or the
POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When IRRX2 is not selected on its corresponding
pin, this bit should be 0.
Bit 4 - GPIO12 Enable (GPIO12_E)
0: GPIO12 Status bit is ignored (bit 4 of the
GP1_STS0 register).
1: When the GPIO12 Status bit is 1:
- Activate the SCI signal or the
POR pin (according
to bit 0 of the PM1_CNT_LOW register).
IRRX1_E
GPIO12_E
GPIO13_E
GPIO10_E
P12_E
76543210
PME1_E
PME2_E
IRRX2_E
00000000
Offset 04h
Power-Up
Required
General Purpose 1
(GP1_EN0)
Reset
Enable 0 Register
Page 83
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
GENERAL PURPOSE EVENT REGISTERS
83
www.national.com
Bit 5 - GPIO13 Enable (GPIO13_E)
0: GPIO13 Status bit is ignored (bit 5 of the
GP1_STS0 register).
1: When the GPIO13 Status bit is 1:
- Activate the SCI signal or the
POR pin (according
to bit 0 of the PM1_CNT_LOW register).
Bit 6 - GPIO10 Enable (GPIO10_E)
0: GPIO10 Status bit is ignored (bit 6 of the
GP1_STS0 register).
1: When the GPIO10 Status bit is 1:
- Activate the
ONCTL pin.
- Activate the SCI signal or the
POR pin (according
to bit 0 of the PM1_CNT_LOW register).
Bit 7 - P12 Enable (P12_E)
0: P12 Status bit is ignored (bit 7 of the GP1_STS0
register).
1: When the P12 Status bit is 1:
- Activate the SCI signal or the
POR pin (according
to bit 0 of the PM1_CNT_LOW register).
4.7.6 General Purpose 1 Enable 1 Register
(GP1_EN1), Offset 05h
This register is reserved. Read returns 0.
4.7.7 General Purpose 1 Enable 2 Register
(GP1_EN2), Offset 06hr
This register is reserved. Read returns 0.
4.7.8 General Purpose 1 Enable 3 Register
(GP1_EN3), Offset 07h
This register is reserved. Read returns 0.
4.7.9 General Purpose 2 Enable 0 Register
(GP2_EN0)
Upon first power Up and Master Reset, these bits are initialized to 0.
.
FIGURE 4-44. GP2_EN0 Register Bitmap
Bit 0 - PME1 Enable (PME1_E)
0: PME1 Status bit is ignored (bit 0 of the GP1_STS0
register).
1: Activate the
POR pin, when the PME1 Status bit is 1,
regardless of bit 0 of the PM1_CNT_LOW register .
When PME1 is not selected on its corresponding pin,
this bit should be 0.
Bit 1 - PME2 Enable (PME2_E)
0: PME2 Status bit is ignored (bit 1 of the GP1_STS0
register).
1: Activate the
POR pin, when the PME2 Status bit
is 1, regardless of bit 0 of the PM1_CNT_LOW
register.
When PME2 is not selected on its corresponding pin,
this bit should be 0.
Bit 2 - IRRX1 Enable (IRRX1_E)
0: IRRX1 Status bit is ignored (bit 2 of the GP1_STS0
register).
1: Activate the
POR pin, when the IRRX1 Status bit
is 1, regardless of bit 0 of the PM1_CNT_LOW
register.
When IRRX1 is not selected on its corresponding pin,
this bit should be 0.
4.7.10 Bit 3 - IRRX2 Enable (IRRX2_E)
0: IRRX2 Status bit is ignored (bit 3 of the GP1_STS0
register)
1: Activate the
POR pin, when the IRRX2 Status bit
is 1, regardless of bit 0 of the PM1_CNT_LOW
register.
When IRRX2 is not selected on its corresponding pin,
this bit should be 0.
Bit 4 - GPIO12 Enable (GPIO12_E)
0: GPIO12 Status bit is ignored (bit 4 of the
GP1_STS0 register).
1: Activate the
POR pin, when the GPIO12 Status bit is
1, regardless of bit 0 of the PM1_CNT_LOW register .
Bit 5 - GPIO13 Enable (GPIO13_E)
0: GPIO13 Status bit is ignored (bit 5 of the
GP1_STS0 register)
1: Activate the
POR pin, when the GPIO13 Status bit is
1, regardless of bit 0 of the PM1_CNT_LOW register .
Bit 6 - GPIO10 Enable (GPIO10_E)
0: GPIO10 Status bit is ignored (bit 6 of the
GP1_STS0 register).
1: Activate the
POR pin, when the GPIO10 Status bit is
1, regardless of bit 0 of the PM1_CNT_LOW register .
Bit 7 - P12 Enable (P12_E)
0: P12 Status bit is ignored (bit 7 of the
GP1_STS0 register).
1: Activate the
POR pin, when the P12 Status bit is 1,
regardless of bit 0 of the PM1_CNT_LOW register.
4.7.11 SMI Command Register (SMI_CMD), Offset 0Ch
This is an 8-bit read/write register. The data held in this register has no affect on the PC87317. Any write to this register
sets bit 5 of the ACPI Support register (see Logical Device
8). This can assert
POR.
IRRX1_E
GPIO12 Enable
GPIO13_E
GPIO10_E
P12_E
76543210
PME1_E
PME2_E
IRRX2_E
00000000
Offset 08h
Power-Up
Required
General Purpose 2
(GP2_EN0)
Reset
Enable Register
Page 84
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
84
RTC AND APC REGISTER BITMAPS
www.national.com
4.8 RTC AND APC REGISTER BITMAPS
4.8.1 RTC Register Bitmaps
4.8.2 APC Register Bitmaps
RS2
DV0
DV2
UIP
76543210
00000100
RS0
RS3
DV1
RS1
Index 0Ah
Power-Up
Required
RTC Control
(CRA)
Reset
Register A
DM
UIE
AIE
PIE
SET
76543210
0000
DSE
24 or 12 Hour Mode
Unused
0
Index 0Bh
Power-Up
Required
RTC Control
(CRB)
Reset
Register B
UF
AF
PF
IRQF
76543210
0000000
0000
Reserved
Index 0Ch
Power-Up
Required
RTC Control
(CRC)
Reset
Register C
VRT
76543210
00000000
0000000
Index 0Dh
Power-Up
Required
RTC Control
(CRD)
Reset
Register D
Reserved
POR Edge or Level Select
MOAP
SOC
Fail-safe Timer Reset Command
Power Failure
76543210
Failsafe Timer Trigger Cmd.
Switch Off Delay Option
Level
POR Clear Command
index 40h
Power-Up
Required
APC Control
(APCR1)
Reset
Register 1
RPTDM
R1E
R2E
SODE
Software On Command
76543210
TME
RSS
RE
Index 41h
Power-Up
Required
APC Control
(APCR2)
Reset
Register 2
RI1 Detect
FTD
SOED
Reserved
RS
76543210
TMD
RID
RI2 Detect
Index 42h
Power-Up
Required
APC Status
(APSR)
Reset
Register
100000
76543210
00000011
Power-Up
Required
Wake up Day of Week
Reset
Wake up Day-of-Week Bits
“Don’t Care” control bits
(WDWR)
Index 43h
Register
Page 85
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
RTC AND APC REGISTER BITMAPS
85
www.national.com
76543210
00000011
Power-Up
Required
Wake up Date-of-Month
(WDMR)
Reset
Register
Wake up Date of Month Bits
“Don’t Care” control bits
Bank 2
Index 44h
76543210
00000011
Power-Up
Required
Wake up Month
(WMR)
Reset
Register
Wake up Month Bits
“Don’t Care” control bits
Bank 2
Index 45h
76543210
00000011
Power-Up
Required
Wake up Year
(WYR)
Reset
Register
Wake up Year Bits
“Don’t Care” control bits
Bank 2
Index 46h
Reserved
RAM Block Read
RAM Block Write
RAM Mask Write
RAM Lock
76543210
Reserved
Reserved
Upper RAM Block
000
00000000
Index 47h
Power-Up
Required
RAM Lock
(RLR)
Reset
Register
76543210
00000011
Power-Up
Required
Wake up Century
(WCR)
Reset
Register
Wake up Century Bits
“Don’t Care” control bits
Bank 2
Index 48h
LED or
CS0 select
76543210
PME1 or GPIO16 select
PME2 or GPIO15 select
GPIO24 or IRRX1 select
00000101
Index 49h
Power-Up
Required
APC Control
(APCR3)
Reset
Register 3
GPIO10 Event Polarity/Edge select
GPIO37 or IRRX2/IRSL0/ID0 Select
76543210
10110100
Index 4Ah
Power-Up
Required
APC Control
(APCR4)
Reset
Register 4
PME1 Event Polarity/Edge select
PME2 Event Polarity/Edge select
LED configuration
76543210
10110100
Index 4Bh
Power-Up
Required
APC Control
(APCR5)
Reset
Register 5
IRRX1 Event Polarity/Edge selec
t
IRRX2 Event Polarity/Edge select
Reserved
GPIO33 or RI2 select
Page 86
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
86
RTC AND APC REGISTER BITMAPS
www.national.com
76543210
10110100
Index 4Ch
Power-Up
Required
APC Control
(APCR6)
Reset
Register 6
GPIO12 Event Polarity/Edge
GPIO13 Event Polarity/Edge select
select
Extended wake-up options after Power failure
76543210
10100000
Index 4Dh
Power-Up
Required
APC Control
(APCR7)
Reset
Register 7
P12 Event Polarity/Edge select
Reserved
Power Button Override Select time
Power Supply Protect Mode
Reserved
76543210
SWITCH pin status
Switch -On Event detect
Index 4Eh
Power-Up
Required
APC Status
(APSR1)
Reset
Register 1
X0
Bank Select
76543210
10010011
Bank 2
Power-Up
Required
Day-of-Month Alarm Address
(DADDR)
Reset
Register
Day-of-Month
Alarm Address
Index 4Fh
76543210
00000011
Power-Up
Required
Date-of-Month Alarm
(DMAR)
Reset
Register
Day-of-Month
Alarm Bits
“Don’t Care” control bits
Relocatable Index
in Bank0 or Bank1
76543210
00000011
Power-Up
Required
Month Alarm
(MAR)
Reset
Register
Month
Alarm Bits
“Don’t Care” control bits
Relocatable Index
in Bank0 or Bank1
Bank Select
76543210
01010011
Bank 2
Power-Up
Required
Month Alarm Address
(MADDR)
Reset
Register
Month
Alarm Address
Index 50h
76543210
00000000
Power-Up
Required
Century
(CR)
Reset
Register
Century
Bits
Relocatable Index
in Bank0 or Bank1
Page 87
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
RTC AND APC REGISTER BITMAPS
87
www.national.com
Bank Select
76543210
00010011
Bank 2
Power-Up
Required
Century Address
(CADDR)
Reset
Register
Century Address
Index 51h
Reserved
76543210
Offset 00h
Power-Up
Required
Power Management 1 Status
(PM1_STS_LOW)
Reset
Low Byte Register
000000
0
0
TMR_STS
Reserved
GBL_STS
Reserved
76543210
Offset 01h
Power-Up
Required
Power Management 1 Status High
(PM1_STS_HIGH)
Reset
Byte Register
000000
0
0
PWRBTN_STS
RTC_STS
PWRBTNOR_STS
Reserved
WAK_STS
Reserved
76543210
Offset 02h
Power-Up
Required
Power Management 1 Enable Low
(PM1_EN_LOW)
Reset
Byte Register
000000
0
0
TMR_EN
Reserved
GBL_EN
Reserved
76543210
Offset 01h
Power-Up
Required
Power Management 1 Enable High
(PM1_EN_HIGH)
Reset
Byte Register
000000
0
0
PWRBTN_EN
RTC_EN
Reserved
Reserved
76543210
Offset 00h
Power-Up
Required
Power Management 1 Control
(PM1_CNT_LOW)
Reset
Low Byte Register
000000
0
0
SCI_EN
Reserved
GBL_RLS
76543210
Offset 01h
Power-Up
Required
Power Management 1 Control
(PM1_CNT_HIGH)
Reset
High Byte Register
000000
0
0
Reserved
Reserved
SLP_EN
SLP_TYP
Power Management Timer Low Byte
76543210
Offset 00h
Power-Up
Required
Power Management Timer Low
(PM1_TMR_LOW)
Reset
Byte Register
000000
0
0
Page 88
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
88
RTC AND APC REGISTER BITMAPS
www.national.com
Power Management Timer Middle Byte
76543210
Offset 00h
Power-Up
Required
Power Management Timer Middle
(PM1_TMR_MID
)
Reset
Byte Register
000000
0
0
Power Management Timer High Byte
76543210
Offset 02h
Power-Up
Required
Power Management Timer
(PM1_TMR_HIGH)
Reset
High Byte Register
000000
0
0
Power Management Timer
76543210
00000000
Offset 00h
Power-Up
Required
Power Management Timer
(PM1_TMR_EXT)
Reset
Extended Byte Register
000000
0
0
Extended Byte
IRRX1_S
GPIO12_S
GPIO13_S
GPIO10_S
P12_S
76543210
PME1_S
PME2_S
IRRX2_S
00000000
Offset 00h
Power-Up
Required
General Purpose 1
(GP1_STS0)
Reset
Status Register
IRRX1_E
GPIO12_E
GPIO13_E
GPIO10_E
P12_E
76543210
PME1_E
PME2_E
IRRX2_E
00000000
Offset 04h
Power-Up
Required
General Purpose 1
(GP1_EN0)
Reset
Enable Register
IRRX1_E
GPIO12_E
GPIO13_E
GPIO10_E
P12_E
76543210
PME1_E
PME2_E
IRRX2_E
00000000
Offset 08h
Power-Up
Required
General Purpose 2
(GP2_EN0)
Reset
Enable Register
Page 89
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
REGISTER BANK TABLES
89
www.national.com
4.9 REGISTER BANK TABLES
TABLE 4-19. Banks 0, 1 and 2 - Common 64-Byte Memory Map
TABLE 4-20. Bank 0 Registers - General Purpose Memory Bank
TABLE 4-21. Bank 1 Registers - RTC Memory Bank
Index FUNCTION BCD FORMAT BINARY FORMAT COMMENTS
00h Seconds 00-59 00-3b R/W
01h Seconds Alarm 00-59 00-3b R/W
02h Minutes 00-59 00-3b R/W
03h Minutes Alarm 00-59 00-3b R/W
04h Hours 12hr = 01-12 (AM) 01-0c (AM) R/W
12hr = 81-92 (PM) 81-8c (PM) R/W
24hr = 00-23 00-17 R/W
05h Hours Alarm 12hr = 01-12 (AM) 01-0c (AM) R/W
12hr = 81-92 (PM) 81-8c (PM) R/W
24hr = 00-23 00-17 R/W
06h Day-of-Week 01-07 01-07 (Sunday = 1) R/W
07h Day-of-Month 01-31 01-1f R/W
08h Month 01-12 01-0c R/W
09h Year 00-99 00-63 R/W
0Ah Control Register A R/W (bit 7 is read only)
0Bh Control Register B R/W (bit 3 is read only)
0Ch Control Register C All bits read only
0Dh Control Register D All bits read only
0Eh-3Fh General Purpose RAM R/W
Register Index Type Power-on Value Function
00h-3Fh
The first 14 RTC registers and the first 50 RTC
RAM bytes are shared among banks 0, 1 and 2.
40h - 7Fh R/W General Purpose 64-Byte Battery-Backed RAM.
Register Index Type Power-on Value Function
00h-3Fh
Banks 0, 1 and 2 share the first 14 RTC registers and the
first 50 RTC RAM bytes.
40h-47h Reserved. Writes have no effect and reads return 00h
Century 48h(relocatable) R/W 00h BCD Format: 00-99. Binary Format: 00-63
Date 0f Month
Alarm
49h R/W C0h
BCD Format: 01-31. Binary Format 01-1F. Bits 6,7 are
“don’t care” control
Month Alarm 4Ah R/W C0h
BCD Format: 01-12. Binary Format 01-0c. Bits 6,7 are
“don’t care” control
4Bh-4Fh Reserved
Page 90
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
90
REGISTER BANK TABLES
www.national.com
TABLE 4-22. Bank 2 Registers - APC Memory Bank
Upper RAM
Address Port
50h R/W
Bits 6-0: Address of the upper 128 RAM bytes.
Bit 7: Reserved
51h-52h Reserved
Upper RAM Data
Port
53h R/W
The byte pointed by the Upper RAM Address Port is
accessed via this register.
54h-7Fh Reser ved
Register Index Type Power-On Value Function
00h - 3Fh Banks 0, 1 and 2 share the first 14 RTC
registers and the first 50 bytes of RTC RAM.
APC Control Register 1
(APCR1)
40h R/W 00h See Section 4.5.1
APC Control Register 2
(APCR2)
41h R/W 00h See Section 4.5.2
APC Status Register (APSR) 42h R 1000001 (binary)
(bit 7 is indeterminate)
See Section 4.5.3
Wake Up Day-of-Week 43h R/W BCD Format: 01-07
Binary Format: 01-07 (Sunday = 1)
Wake Up Day-of-Month 44h R/W BCD For mat: 01-31
Binary Format: 01-1F
Wake Up Month 45h R/W BCD Format: 01-12
Binary Format: 01-0C
Wake Up Year 46h R/W BCD Format: 00-99
Binary Format: 00-63
RAM Lock 47h R/W 00h
initialized also on
MR pin reset.
See Section 4.5.8
Wake Up Century 48h R/W BCD Format: 00-99
Binary Format: 00-63
APC Control Register 3
(APCR3)
49h R/W A0h See Section 4.5.10
APC Control Register 4
(APCR4)
4Ah R/W 2Dh See Section 4.5.11
APC Control Register 5
(APCR5)
4Bh R/W 2Dh See Section 4.5.12
APC Control Register 6
(APCR6)
4Ch R/W 2Dh See Section 4.5.13
APC Control Register 7
(APCR7)
4Dh R/W 05h See Section 4.5.14
APC Status Register 1
(APSR1)
4Eh R X See Section 4.5.15
Date of Month Alarm
Address Register
4Fh R/W C9h Contains the Date of Month Alarm Relocatable
index within bank 0 or 1
Register Index Type Power-on Value Function
Page 91
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
REGISTER BANK TABLES
91
www.national.com
TABLE 4-23. Available General Purpose Bytes
Month Alarm Address
Register
50h R/W CAh Contains the Month Alarm Relocatable index
within bank 0 or 1
Century Address Register 51h R/W C8h Contains the Century Relocatable index within
bank 0 or 1
52h-7Fh Reser ved
Index Bank Number of Bytes Notes
0Eh - 3Fh All 50
40h - 7Fh Bank 0 64
50h, 53h Bank 1 128 Indirect access via 50h for address and 53h for data.
Total 242
Register Index Type Power-On Value Function
Page 92
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
92
5.0 The Digital Floppy Disk Controller (FDC) (Logical Device 3)
www.national.com
5.0 The Digital Floppy Disk Controller
(FDC) (Logical Device 3)
The Floppy Disk Controller (FDC) is suitable for all PC-AT,
EISA, PS/2, and general purpose applications. DP8473 and
N82077 software compatibility is provided. Key features include a 16-byte FIFO, PS/2 diagnostic register support, perpendicular recording mode, CMOS disk input and output
logic, and a high performance Digital Data Separator
(DDS).
FIGURE 5-1 "FDC Functional Block Diagram" shows a
functional block diagram of the FDC. The rest of this chapter
describes the FDC functions, data transfer, the FDC registers, the phases of FDC commands, the result phase status
registers and the FDC commands, in that order.
5.1 FDC FUNCTIONS
FDC functions are enabled when the FDC Function Enable
bit (bit 3) of the Function Enable Register 1 (FER1) at offset
00h in logical device 8 is set to 1. See Section 10.2.3 "Function Enable Register 1 (FER1)" on page 219.
The PC87317 is software compatible with the DP8473 and
82077 Floppy Disk Controllers (FDCs). Upon a power-on
reset, the 16-byte FIFO is disabled. Also, the disk interface
output signals are configured as active push-pull output signals, which are compatible with both CMOS input signals
and open-collector resistor terminated disk drive input signals.
The FIFO can be enabled with the CONFIGURE command.
The FIFO can be very useful at high data rates, with systems that have a long DMA bus latency, or with multi-tasking systems such as the EISA or MCA bus structures.
The FDC supports all the DP8473 MODE command features as well as some additional features. These include
control over the enabling of the FIFO for read and write operations, disabling burst mode for the FIFO, a bit that will
configure the disk interface outputs as open-drain output
signals, and programmability of the DENSEL output signal.
5.1.1 Microprocessor Interface
The Floppy Disk Controller (FDC) receives commands,
transfers data, and returns status information via an FDC
microprocessor interface. This interface consists of the
A9-3, AEN,
RD, and WR signals, which access the chip for
read and write operations; the data signals D7-0; the address lines A2-0, which select the appropriate register (see
TABLE 5-1 "The FDC Registers and Their Addresses" on
page 96) an IRQ signal, and the DMA interface signals
DRQ,
DACK, and TC.
5.1.2 System Operation Modes
The FDC operates in PC-AT or PS/2 drive mode, depending
on the value of bit 2 of the SuperI/O Configuration 1 register
at index 21h. See Section 2.4.3 "SuperI/O Configuration 1
Register (SIOC1)" on page 37.
FIGURE 5-1. FDC Functional Block Diagram
To Floppy Disk Interface Cable
Internal Control and Data Bus
Interface
Logic
Address
Decoder
DMA
Enable
Logic
Main Status
Register
16-Byte
FIFO
(MSR)
PC8477B
Micro-Engine
and
Timing/Control
Logic
Data Rate
Selection
Register
(DSR)
Configuration
Control
Register
(CCR)
2 KB x 16
Micro-Code
Status
Register A
Status
Register B
Digital Input
Register
(DIR)
Digital Output
Register
(DOR)
Write
Precompen-
Digital
Data
Separator
(DDS)
Disk
Input
and
Output
Logic
DRATE0
DENSEL
DIR
DR1
HDSEL
MTR0
sator
MTR1
STEP
WGATE
WDATA
DSKCHG
INDEX
RDATA
TRK0
WP
MSEN1,0
RD
FDC Chip
WR
A2-0
Reset
D7-0
FDC DMA
TC
FDC DMA
Interrupt
FDC Clock
Select
Acknowledge
Request
DR0
Page 93
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
DATA TRANSFER
93
www.national.com
PC-AT Drive Mode
The PC-AT register set is enabled. The DMA enable bit in
the Digital Output Register (DOR) becomes valid (the appropriate IRQ and DRQ signals can be put in TRI-STATE).
TC and DENSEL become active high signals (default to a
5.25" floppy disk drive).
PS/2 Drive Mode
This drive mode supports the PS/2 models 50/60/80 configuration and register set. The value of the DMA enable bit in
the Digital Output Register (DOR) becomes unimportant
(the IRQ and DRQ signals assigned to the FDC are always
valid). TC and DENSEL become active low signals (default
to 3.5" floppy drive).
5.2 DATA TRANSFER
5.2.1 Data Rates
The FDC supports the standard PC data rates of 250, 300
and 500 Kbps, as well as 1 Mbps. High performance tape
and floppy disk drives that are currently emerging in the PC
world, transfer data at 1 Mbps. The FDC also supports the
perpendicular recording mode, a new format used for some
high capacity disk drives at 1 Mbps.
The internal digital data separator needs no external components. It improves the window margin performance standards of the DP8473, and is compatible with the strict data
separator requirements of floppy disk drives and tape
drives.
The FDC contains write precompensation circuitry that defaults to 125 nsec for 250, 300, and 500 Kbps (41.67 nsec
at 1 Mbps). These values can be overridden in software to
disable write precompensation or to provide levels of precompensation up to 250 nsec.
The FDC has internal 24 mA data bus buffers which allow
direct connection to the system bus. The internal 40 mA totem-pole disk interface buffers are compatible with both
CMOS drive input signals and 150 resistor terminated disk
drive input signals.
5.2.2 The Data Separator
The internal data separator is a fully digital PLL. The fully
digital PLL synchronizes the raw data signal read from the
disk drive. The synchronized signal is used to separate the
encoded clock and data pulses. The data pulses are broken
down into bytes, and then sent to the microprocessor by the
controller.
The FDC supports data transfer rates of 250, 300, 500 Kbps
and 1 Mbps in Modified Frequency Modulation (MFM) format.
The FDC has a dynamic window margin and lock range performance capable of handling a wide range of floppy disk
drives. In addition, the data separator operates under a variety of conditions, including high fluctuations in the motor
speed of tape drives that are compatible with floppy disk
drives.
The dynamic window margin is the primary indicator of the
quality and performance level of the data separator. It indicates the toleration of the data separator for Motor Speed
Variation (MSV) of the drive spindle motor and bit jitter (or
window margin).
FIGURE 5-2 "PC87317 Dynamic Window Margin
Performance" shows the dynamic window margin in the
performance of the FDC at different data rates, generated
using a FlexStar FS-540 floppy disk simulator and a proprietary dynamic window margin test program written by
National Semiconductor.
FIGURE 5-2. PC87317 Dynamic Window Margin
Performance
The x axis measures MSV. MSV is translated directly to the
actual rate at which the data separator reads data from the
disk. In other words, a faster than nominal motor results in
a higher data rate.
The dynamic window margin performance curve also indicates how much bit jitter (or window margin) can be tolerated by the data separator. This parameter is shown on the yaxis of the graph. Bit jitter is caused by the magnetic interaction of adjacent data pulses on the disk, which effectively
shifts the bits away from their nominal positions in the middle of the bit window. Window margin is commonly measured as a percentage. This percentage indicates how far a
data bit can be shifted early or late with respect to its nominal bit position, and still be read correctly by the data separator. If the data separator cannot correctly decode a shifted
bit, then the data is misread and a CRC error results.
The dynamic window margin performance curve supplies
two pieces of information:
●
The maximum range of MSV (also called “lock range”)
that the data separator can handle with no read errors.
●
The maximum percentage of window margin (or bit jitter)
that the data separator can handle with no read errors.
Thus, the area under the dynamic window margin curves in
FIGURE 5-2 "PC87317 Dynamic Window Margin
Performance" is the range of MSV and bit jitter that the FDC
can handle with no read errors. The internal digital data separator of the FDC performs much better than comparable
digital data separator designs, and does not require any external components.
-14-12-10 -8 -6 -4 -2 0 2 4 4 8 10 12 14
10
20
30
40
60
70
80
50
Window Margin Percentage
Motor Speed Variation (% of Nominal)
250,300, 500 Kbps and 1 Mbps
Typical Performance at 500 Kbps,
V
DD
= 5.0 V, 25 C
Page 94
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
94
DATA TRANSFER
www.national.com
The controller maximizes the internal digital data separator
by implementing a read algorithm that enhances the lock
characteristics of the fully digital Phase-Locked Loop (PLL).
The algorithm minimizes the effect of bad data on the synchronization between the PLL and the data.
It does this by forcing the fully digital PLL to re-lock to the
clock reference frequency any time the data separator attempts to lock to a non-preamble pattern. See the state diagram of this read algorithm in FIGURE 5-3 "Read
Algorithm State Diagram".
FIGURE 5-3. Read Algorithm State Diagram
5.2.3 Perpendicular Recording Mode Support
The FDC is fully compatible with perpendicular recording
mode disk drives at all data transfer rates. These perpendicular drives are also called 4 Mbyte (unformatted) or 2.88
Mbyte (formatted) drives. This refers to their maximum storage capacity.
Perpendicular recording orients the magnetic flux changes
(which represent bits) vertically on the disk surface, allowing for a higher recording density than conventional longitudinal recording methods. This increased recording density
increases data rate by up to 1 Mbps, thereby doubling the
storage capacity. In addition, the perpendicular 2.88 MB
drive is read/write compatible with 1.44 MB and 720 KB diskettes (500 Kbps and 250 Kbps respectively).
The 2.88 MB drive has unique format and write data timing
requirements due to its read/write head and pre-erase head
design. This is illustrated in FIGURE 5-4 "Perpendicular Recording Drive Read/Write Head and Pre-Erase Head".
Unlike conventional disk drives which have only a
read/write head, the 2.88 MB drive has both a pre-erase
head and read/write head. With conventional disk drives,
the read/write head, itself, can rewrite the disk without problems. 2.88 MB drives need a pre-erase head to erase the
magnetic flux on the disk surface before the read/write head
can write to the disk surface. The pre-erase head is activated during disk write operations only, i.e. FORMAT and
WRITE DATA commands.
In 2.88 MB drives, the pre-erase head leads the read/write
head by 200 µm, which translates to 38 bytes at 1 Mbps (19
bytes at 500 Kbps).
FIGURE 5-4. Perpendicular Recording Drive
Read/Write Head and Pre-Erase Head
For both conventional and perpendicular drives,
WGATE is
asserted with respect to the position of the read/write head.
With conventional drives, this means that
WGATE is asserted when the read/write head is located at the beginning of
the preamble to the data field.
With 2.88 MB drives, since the preamble must be erased
before it is rewritten,
WGATE should be asserted when the
pre-erase head is located at the beginning of the preamble
to the data field. This means that
WGATE should be asserted when the read/write head is at least 38 bytes (at 1 Mbps)
before the preamble. TABLES 5-15 "Effect of Drive Mode
and Data Rate on FORMAT TRACK and WRITE DATA
Commands" on page 122 and 5-16 "Effect of GDC Bits on
FORMAT TRACK and WRITE DATA Commands" on page
122 show how the perpendicular format affects gap 2 and,
consequently,
WGATE timing, for different data rates.
Because of the 38-byte spacing between the read/write
head and the pre-erase head at 1 Mbps, the gap 2 length of
22 bytes used in the standard IBM disk format is not long
enough. The format standard for 2.88 MB drives at 1 Mbps
called the Perpendicular Format, increases the length of
gap 2 to 41 bytes. See FIGURE 5-19 "IBM, Perpendicular,
and ISO Formats Supported by the FORMAT TRACK Command" on page 118.
The PERPENDICULAR MODE command puts the Floppy
Disk Controller (FDC) into perpendicular recording mode,
which allows it to read and write perpendicular media. Once
this command is invoked, the read, write and format commands can be executed in the normal manner. The perpendicular mode of the FDC functions at all data rates,
adjusting format and write data parameters accordingly.
See Section 5.7.9 "The PERPENDICULAR MODE Command" on page 121 for more details.
5.2.4 Data Rate Selection
The FDC sets the data rate in two ways. For PC compatible
software, the Configuration Control Register (CCR) at offset
07h programs the data rate for the FDC. The lower bits D1
and D0 in the CCR set the data rate. The other bits should
be set to zero. TABLE 5-6 "Data Transfer Rate Encoding"
on page 101 shows how to encode the desired data rate.
Not
sixth bit.
Read Gate = 1
Read Gate = 0
PLL
to data.
Wait six bits.
Three address
Wait for
is not a
bit.
Bit is
preamble.
Bit is not
preamble.
Three address
marks found.
Check for
three address
mark bytes.
Not third
address mark.
PLL idle
locked
to clock.
Operation
completed.
Read ID
field or
data field.
locking
first bit that
preamble
marks not found.
200 µm
(38 bytes @ 1 Mbps)
End of
ID Field
Data Field
Preamble
Intersector
Read/
PreHead
Head
Write
Gap 2
= 41 x 4Eh
Erase
Page 95
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
DATA TRANSFER
95
www.national.com
The lower two bits of the Data rate Select Register (DSR) at
offset 04h can also set the data rate. These bits are encoded like the corresponding bits in the CCR. The remainder of
the bits in the DSR have other functions. See the description of the DSR in Section 5.3.6 "Data Rate Select Register
(DSR)" on page 101 for more details.
The data rate is determined by the last value written to either the CCR or the DSR. Either the CCR or the DSR can
override the data rate selection of the other register. When
the data rate is selected, the micro-engine and data separator clocks are scaled appropriately.
5.2.5 Write Precompensation
Write precompensation enables the
WDATA output signal
to adjust for the effects of bit shift on the data as it is written
to the disk surface.
Bit shift is caused by the magnetic interaction of data bits as
they are written to the disk surface. It shifts these data bits
away from their nominal position in the serial MFM data pattern. Bit shift makes it much harder for a data separator to
read data and can cause soft read errors.
Write precompensation predicts where bit shift could occur
within a data pattern. It then shifts the individual data bits
early, late, or not at all so that when they are written to the
disk, the shifted data bits are back in their nominal position.
The FDC supports software programmable write precompensation. Upon power up, the default write precompensation values shown in TABLE 5-8 "Default Precompensation
Delays" on page 102, are used. In addition, the default starting track number for write precompensation is track zero
You can use the DSR to change the write precompensation
using any of the values in TABLE 5-7 "Write Precompensation Delays" on page 102. Also, the CONFIGURE command
can change the starting track number for write precompensation.
5.2.6 FDC Low-Power Mode Logic
The FDC of the PC87317 supports two low-power modes,
manual and automatic.
In low-power mode, the micro-code is driven from the clock.
Therefore, it is disabled while the clock is off. Upon entering
the power-down state, bit 7, the RQM (Request For Master)
bit, in the Main Status Register (MSR) of the FDC is cleared
to 0.
For details about entering and exiting low-power mode by
setting bit 6 of the Data rate Select Register (DSR) or by executing the LOW PWR option of the FDC MODE command,
see “Recovery from Low-Power Mode” later in this section,
Section 5.3.6 "Data Rate Select Register (DSR)" on page
101 and Section 5.7.7 "The MODE Command" on page
119.
The DSR, Digital Output Register (DOR), and the Configu-
ration Control Register (CCR) are unaffected and remain
active in power-down mode. Therefore, you should make
sure that the motor and drive select signals are turned off.
If the power to an external clock driving the PC87317 will be
independently removed while the FDC is in power-down
mode, it must not be done until 2 msec after the LOW PWR
option of the FDC MODE command is issued.
Manual Low-Power Mode
Manual low power is enabled by writing a 1 to bit 6 of the
DSR. The chip will power down immediately. This bit will be
cleared to 0 after power up.
Manual low power can also be triggered by the MODE command. Manual low power mode functions as a logical OR
function between the DSR low power bit and the LOW PWR
option of the MODE command.
Automatic Low-Power Mode
Automatic low-power mode switches the controller to low
power 500 msec (at the 500 Kbps MFM data rate) after it
has entered the Idle state. Once automatic low-power mode
is set, it does not have to be set again, and the controller automatically goes into low-power mode after entering the Idle
state.
Automatic low-power mode can only be set with the LOW
PWR option of the MODE command.
Recovery from Low-Power Mode
There are two ways the FDC section can recover from the
power-down state.
Power up is triggered by a software reset via the DOR or
DSR. Since a software reset requires initialization of the
controller, this method might be undesirable.
Power up is also triggered by a read or write to either the
Data Register (FIFO) or Main Status Register (MSR). This
is the preferred way to power up since all internal register
values are retained. It may take a few milliseconds for the
clock to stabilize, and the microprocessor will be prevented
from issuing commands during this time through the normal
MSR protocol. That means that bit 7, the Request for Master (RQM) bit, in the MSR will be a 0 until the clock has stabilized. When the controller has completely stabilized after
power up, the RQM bit in the MSR is set to 1 and the controller can continue where it left off.
5.2.7 Reset
The FDC can be reset by hardware or software.
A hardware reset consists of pulsing the Master Reset (MR)
input signal. A hardware reset sets all of the user addressable registers and internal registers to their default values.
The SPECIFY command values are unaffected by reset, so
they must be initialized again.
The major default conditions affected by reset are:
●
FIFO disabled
●
DMA disabled
●
Implied seeks disabled
●
Drive polling enabled
A software reset can be triggered by bit 2 of the Digital Output Register (DOR) or bit 7 of the Data rate Select Register
(DSR). Bit 7 of DSR clears itself, while bit 2 of DOR does
not clear itself.
If the LOCK bit in the LOCK command was set to 1 before
the software reset, the FIFO, THRESH, and PRETRK parameters in the CONFIGURE command will be retained. In
addition, the FWR, FRD, and BST parameters in the MODE
command will be retained if LOCK is set to 1. This function
eliminates the need for total initialization of the controller after a software reset.
After a hardware (assuming the FDC is enabled in the FER)
or software reset, the Main Status Register (MSR) is immediately available for read access by the microprocessor. It
will return a 00h value until all the internal registers have
been updated and the data separator is stabilized.
Page 96
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
96
THE FDC REGISTERS
www.national.com
When the controller is ready to receive a command byte, the
MSR returns a value of 80h (Request for Master (RQM, bit
7) bit is set). The MSR is guaranteed to return the 80h value
within 250 µsec after a hardware or software reset.
All other user addressable registers other than the Main
Status Register (MSR) and Data Register (FIFO) can be accessed at any time, even during software reset.
5.3 THE FDC REGISTERS
The FDC registers are mapped to the offset address shown
in TABLE 5-1 "The FDC Registers and Their Addresses",
with the base address range provided by the on-chip address decoder. For PC-AT or PS/2 applications, the offset
address range of the diskette controller is 00h through 07h
from the index of logical device 3.
TABLE 5-1. The FDC Registers and Their Addresses
The FDC supports two system operation modes: PC-AT
drive mode and PS/2 drive mode (MicroChannel systems).
Section 5.1.2 "System Operation Modes" on page 92 describes each mode and “Bit 2 - PC-AT or PS/2 Drive Mode
Select” on page 37 describes how each is enabled.
Unless specifically indicated otherwise, all fields in all registers are valid in both drive modes.
The FDC supports plug and play, as follows:
●
The FDC interrupt can be routed on one of the following
ISA interrupts: IRQ3-IRQ7, IRQ9-IRQ12 and IRQ15
(see PNP2 register).
●
The FDC DMA signals can be routed to one of three 8bit ISA DMA channels (see PNP2 register); and its base
address is software configurable (see FBAL and FBAH
registers).
●
Upon reset, the DMA of the FDC is routed to the DRQ2
and
DACK2 pins.
5.3.1 Status Register A (SRA)
Status Register A (SRA) monitors the state of assigned IRQ
signal and some of the disk interface signals. SRA is a readonly register that is valid only in PS/2 drive mode.
SRA can be read at any time while PS/2 drive mode is active. In PC-AT drive mode, all bits are in TRI-STATE during
a microprocessor read.
FIGURE 5-5. SRA Register Bitmap
Bit 0 - Head Direction
This bit indicates the direction of the head of the Floppy
Disk Drive (FDD). Its value is the inverse of the value of
the
DIR interface output signal.
0:
DIR is not active, i.e., the head of the FDD steps
outward. (Default)
1:
DIR is active, i.e., the head of the FDD steps inward.
Bit 1 - Write Protect (
WP)
This bit indicates whether or not the selected Floppy
Disk Drive (FDD) is write protected. Its value reflects the
status of the
WP disk interface input signal.
0:
WP is active, i.e., the FDD in the selected drive is
write protected.
1:
WP is not active, i.e., the FDD in the selected drive
is not write protected.
Bit 2 - Beginning of Track (
INDEX)
This bit indicates the beginning of a track. Its value reflects the status of the
INDEX disk interface input signal.
0:
INDEX is active, i.e., it is the beginning of a track.
1:
INDEX is not active, i.e., it is not the beginning of a
track.
Bit 3 - Head Select
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected by the head. Its value is the inverse of
the
HDSEL disk interface output signal.
0:
HDSEL is not active, i.e., the head of the FDD selects side 0. (Default)
1:
HDSEL is active, i.e., the head of the FDD selects
side 1.
Bit 4 - At Track 0 (
TRK0)
This bit indicates whether or not the head of the Floppy
Disk Drive (FDD) is at track 0. Its value reflects the status of the
TRK0 disk interface input signal.
0:
TRK0 is active, i.e., the head of FDD is at track 0.
1:
TRK0 is not active, i.e., the head of FDD is not at
track 0.
Symbol Description
Offset
R/W
A2 A1 A0
SRA Status Register A 0 0 0 R
SRB Status Register B 0 0 1 R
DOR Digital Output Register 0 1 0 R/W
TDR Tape Drive Register 0 1 1 R/W
MSR Main Status Register 1 0 0 R
DSR Data Rate Select Register 1 0 0 W
FIFO Data Register (FIFO) 1 0 1 R/W
- (Bus in TRI-STATE) 1 1 0 X
DIR Digital Input Register 1 1 1 R
CCR CCR Configuration
Control Register
111 W
76543210
Reset
Required
0000
Status Register
A (SRA)
Offset 00h
INDEX
TRK0
Step
Reserved
IRQ Pending
Head Direction
WP
Head Select
PS/2 Drive Mode
Page 97
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
THE FDC REGISTERS
97
www.national.com
Bit 5 - Step
This bit indicates whether or not the head of the Floppy
Disk Drive (FDD) should move during a seek operation.
Its value is the inverse of the
STEP disk interface output
signal.
0:
STEP is not active, i.e., the head of the FDD
moves. (Default)
1:
STEP is active (low), i.e., the head of the FDD does
not move.
Bit 6 - Reserved
Bit 7 - IRQ Pending
This bit signals the completion of the execution phase of
certain FDC commands. Its value reflects the status of
the IRQ signal assigned to the FDC.
0: The IRQ signal assigned to the FDC is not active.
1: The IRQ signal assigned to the FDC is active, i.e.,
the FDD has completed execution of certain FDC
commands.
5.3.2 Status Register B (SRB)
Status Register B (SRB) is a read-only diagnostic register
that is valid only in PS/2 drive mode.
SRB can be read at any time while PS/2 drive mode is active. In PC-AT drive mode, all bits are in TRI-STATE during
a microprocessor read.
Bit 0 - Motor 0 Status (MTR0)
This bit indicates the complement of the
MTR0 output
pin.
This bit is cleared to 0 by a hardware reset and unaffect-
ed by a software reset.
0:
MTR0 not active; motor 0 off
1:
MTR0 active; motor 0 on (default)
Bit 1 - Motor 1 Status (MTR1)
This bit indicates the complement of the
MTR1 output
pin.
This bit is cleared to 0 by a hardware reset and unaffect-
ed by a software reset.
0:
MTR0 not active; motor 1 off
1:
MTR0 active.; motor 1 on (default)
Bit 2 - Write Circuitry Status (WGATE)
This bit indicates the complement of the
WGATE output
pin.
0:
WGATE not active. The write circuitry of the selected FDD is enabled.
1:
WGATE active. The write circuitry of the selected
FDD is disabled. (Default))
Bit 3 - Read Data Status (
RDATA)
If read data was sent, this bit indicates whether an odd
or even number of bits was sent.
Every inactive edge transition of the
RDATA disk inter-
face output signal causes this bit to change state.
0: Either no read data was sent or an even number of
bits of read data was sent. (Default)
1: An odd number of bits of read data was sent.
Bit 4 - Write Data Status (
WDATA)
If write data was sent, this bit indicates whether an odd
or even number of bits was sent.
Every inactive edge transition of the
WDATA disk inter-
face output signal causes this bit to change state.
0: Either no wr ite data was sent or an even number of
bits of write data was sent. (Default)
1: An odd number of bits of write data was sent.
Bit 5 - Drive Select 0 Status
This bit reflects the status of drive select bit 0 in the Digital Output Register (DOR). See Section 5.3.3 "Digital
Output Register (DOR)".
It is cleared after a hardware reset and unaffected by a
software reset.
0: Either drive 0 or 2 is selected. (Default)
1: Either drive 1 or 3 is selected.
Bits 7,6 - Reserved
These bits are reserved and are always 1.
5.3.3 Digital Output Register (DOR)
DOR is a read/write register that can be written at any time.
It controls the drive select and motor enable disk interface
output signals, enables the DMA logic and contains a software reset bit.
The contents of the DOR is set to 00h after a hardware reset, and is unaffected by a software reset.
TABLE 5-2 "Drive and Motor Pin Encoding for Four Drive
Configurations and Drive Exchange Support" shows how
the bits of DOR select a drive and enable a motor when the
FDC is enabled (bit 3 of the Function Enable Register 1
(FER1) at offset 00h of logical device 8 is 1) and bit 7 of the
SuperI/O FDC Configuration register at index F0h is 1. Bit
patterns not shown produce states that should not be decoded to enable any drive or motor.
When the FDC is enabled and bit 7 of the of the SuperI/O
FDC Configuration register at index F0h is 1,
MTR1 pre-
sents a pulse that is the inverse of
WR. This pulse is active
whenever an I/O write to address 02h occurs. This pulse is
delayed for between 25 and 80 nsec after the leading edge
of
WR. The leading edge of this pulse can be used to clock
data into an external latch (e.g., 74LS175).
76543210
Reset
Required
00000011
11
SRB Register
Offset 01h
WGATE
WDATA
Drive Select 0 Status
Reserved
Reserved
MTR0
MTR1
RDATA
PS/2 Drive Mode
Page 98
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
98
THE FDC REGISTERS
www.national.com
TABLE 5-2. Drive and Motor Pin Encoding for Four
Drive Configurations and Drive Exchange Support
Usually, the motor enable and drive select output signals for
a particular drive are enabled together. TABLE 5-3 "Drive
Enable Hexadecimal Values" shows the DOR hexadecimal
values that enable each of the four drives.
TABLE 5-3. Drive Enable Hexadecimal Values
The motor enable and drive select signals for drives 2 and
3 are only available when four drives are supported, i.e., bit
7 of the SuperI/O FDC Configuration register at index F0h
is 1, or when drives 2 and 0 are exchanged. These signals
require external logic.
FIGURE 5-6. DOR Register Bitmap
Bits 1,0 - Drive Select
These bits select a drive, so that only one drive select
output signal is active at a time.
See “Bit 7 - Four Drive Encode” on page 40 and “Bits 3,2
- Logical Drive Control (Enhanced TDR Mode Only)” on
page 100 for more information.
00:Drive 0 is selected. (Default)
01:Drive 1 is selected.
10:If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11:If four drives are supported, drive 3 is selected.
Bit 2 - Reset Controller
This bit can cause a software reset. The controller remains in a reset state until this bit is set to 1.
A software reset affects the CONFIGURE and MODE
commands. See Sections 5.7.2 "The CONFIGURE
Command" on page 114 and 5.7.7 "The MODE Command" on page 119, respectively. A software reset does
not affect the Data rate Select Register (DSR), Configuration Control Register (CCR) and other bits of this register (DOR).
This bit must be low for at least 100 nsec. There is
enough time during consecutive writes to the DOR to reset software by toggling this bit.
0: Reset controller. (Default)
1: No reset.
Bit 3 - DMA Enable (DMAEN)
In PC-AT drive mode, this bit enables DMA operations
by controlling
DACK, TC and the appropriate DRQ and
IRQ DMA signals. In PC-AT mode, this bit is set to 0 after reset.
In PS/2 drive mode, this bit is reserved, and
DACK, TC
and the appropriate DRQ and IRQ signals are enabled.
During reset, these signals remain enabled.
0: In PC-AT drive mode, DMA operations are dis-
abled.
DACK and TC are disabled, and the appropriate DRQ and IRQ signals are put in TRI-STATE.
(Default)
1: In PC-AT drive mode, DMA operations are enabled,
i.e.,
DACK, TC and the appropriate DRQ and IRQ
signals are all enabled.
Digital Output
Register Bits
Control
Signals
Decoded Functions
MTR DR
765432101010
xxx1xx00-000
Activate Drive 0
and Motor 0
xx1xxx01-001
Activate Drive 1
and Motor 1
x1xxxx10-010
Activate Drive 2
and Motor 2
1xxxxx11-011
Activate Drive 3
and Motor 3
xxx0xx00-100
Activate Drive 0 and
Deactivate Motor 0
xx0xxx01-101
Activate Drive 1 and
deactivate Motor 1
x0xxxx10-110
Activate Drive 2 and
Deactivate Motor 2
0xxxxx11-111
Activate Drive 3 and
Deactivate Motor 3
Drive DOR Value (Hex)
01C
12D
24E
38F
76543210
Reset
Required
00000000
Digital Output
Register (DOR)
Offset 02h
Reset Controller
Motor Enable 0
Motor Enable 1
Motor Enable 2
Motor Enable 3
Drive Select
DMAEN
Page 99
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
THE FDC REGISTERS
99
www.national.com
Bit 4- Motor Enable 0
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 0, depending on
the remaining bits of this register. See TABLE 5-2
"Drive and Motor Pin Encoding for Four Drive Configurations and Drive Exchange Support" on page 98.
If two drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 0), this bit controls
the motor output signal for drive 0.
0: The motor signal for drive 0 is not active.
1: The motor signal for drive 0 is active.
Bit 5 - Motor Enable 1
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 0, depending on
the remaining bits of this register. See TABLE 5-2.
If two drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 0), this bit controls
the motor output signal for drive 1.
0: The motor signal for drive 1 is not active.
1: The motor signal for drive 1 is active.
Bit 6 - Motor Enable 2
If drives 2 and 0 are exchanged (see "Bits 3,2 - Logical
Drive Control (Enhanced TDR Mode Only)" on page
100), or if four drives are supported (bit 7 of the SuperI/O FDC Configuration register at index F0h is 1), this
bit controls the motor output signal for drive 2. See TABLE 5-2.
0: The motor signal for drive 2 is not active.
1: The motor signal for drive 2 is active.
Bit 7 - Motor Enable 3
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 3, depending on
the remaining bits of this register. See TABLE 5-2.
0: The motor signal for drive 3 is not active.
1: The motor signal for drive 3 is active.
5.3.4 Tape Drive Register (TDR)
The TDR register is a read/write register that acts as the
Floppy Disk Controller’s (FDC) media and drive type register.
The TDR functions differently, depending on the mode set
by bit 6 the SuperI/O FDC Configuration register at index
F0h. See “Bit 6 - TDR Register Mode” on page 40.
AT Compatible TDR Mode
In this mode, the TDR assigns a drive number to the tape
drive support mode of the data separator. All other logical
drives can be assigned as floppy drive support. Bits 7-2 are
in TRI-STATE during read operations.
Enhanced TDR Mode
In this mode, all the bits of the TDR define operations with
Enhanced floppy disk drives.
FIGURE 5-7. TDR Register Bitmap, AT Compatible
TDR Mode
FIGURE 5-8. TDR Register Bitmap, Enhanced TDR
Mode
TABLE 5-4. TDR Bit Utilization and Reset Values in Different Drive Modes
76543210
Reset
Required
001
Tape Drive
Register (TDR)
Offset 03h
Tape Drive Select 1,0
AT Compatible TDR Mode
TRI-STATE During Read Operations
Not Used
76543210
Reset
Required
001
Tape Drive
Register (TDR)
Offset 03h
High Density
Extra Density
Tape Drive Select 1,0
Logical Drive Exchange
Enhanced TDR Mode
Drive ID1 Information
Drive ID0 Information
TDR Mode
Bit 6 of SuperI/O
FDC Configuration
Register
Bits of TDR
Extra
Density
High
Density
Drive ID1 Drive ID0
Logical Drive
Exchange
Drive Select
76543210
At Compatible 0 Not used. Floated in TRI-STATE during read operations. 0 0
Enhanced 1 Not Reset Not Reset 1 1 0 0 0 0
Page 100
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
100
THE FDC REGISTERS
www.national.com
Bits 1,0 - Tape Drive Select 1,0
These bits assign a logical drive number to a tape drive.
Drive 0 is not available as a tape drive and is reserved
as the floppy disk boot drive.
00:No drive selected.
01:Drive 1 selected.
10:Drive 2 selected.
11:Drive 3 selected.
Bits 3,2 - Logical Drive Control (Enhanced TDR Mode
Only)
These read/write bits control logical drive exchange between drives 0 and 2, only.
They enable software to exchange the physical floppy
disk drive and motor control signals assigned to pins.
Drive 3 is never exchanged for drive 2.
When four drives are configured, i.e., bit 7 of SuperI/O
FDC Configuration register at index F0h is 1, logical
drives are not exchanged.
00:No logical drive exchange.
01: Disk dr ive and motor control signal assignment to
pins exchanged between logical drives 0 and 1.
10: Disk dr ive and motor control signal assignment to
pins exchanged between logical drives 0 and 2.
11:Reserved. Unpredictable results when configured.
Bits 5,4 - Drive ID1,0 Information
If the value of bits 1,0 of the Digital Output Register
(DOR) are 00, these bits reflect the ID of drive 0, i.e., the
value of bits 1,0, respectively, of the Drive ID register at
index F1h. See “Bits 1,0 - Drive 0 ID” on page 41.
If the value of bits 1,0 of the Digital Output Register
(DOR) are 01, these bits reflect the ID of drive 1, i.e., the
value of bits 3,2, respectively, of the Drive ID register at
index F1h. See “Bits 3,2 - Drive 1 ID” on page 41.
Bit 6 - High Density (Enhanced TDR Mode Only)
Together with bit 7, this bit indicates the type of media
currently in the active floppy disk drive. The value of this
bit reflects the state of the MSEN0 signal.
TABLE 5-5 "Media Type (Density) Encoding" shows
how these bits encode media type.
TABLE 5-5. Media Type (Density) Encoding
Bit 7 - Extra Density (Enhanced TDR Mode Only)
Together with bit 6, this bit indicates the type of media
currently in the active floppy disk drive. The value of this
bit reflects the state of the MSEN1 signal.
TABLE 5-5 shows how these bits encode media type.
5.3.5 Main Status Register (MSR)
This read-only register indicates the current status of the
Floppy Disk Controller (FDC), indicates when the disk controller is ready to send or receive data through the Data
Register (FIFO) and controls the flow of data to and from the
Data Register (FIFO).
The MSR can be read at any time. It should be read before
each byte is transferred to or from the Data Register (FIFO)
except during a DMA transfer. No delay is required when
reading this register after a data transfer.
The microprocessor can read the MSR immediately after a
hardware or software reset, or recovery from a power down.
The MSR contains a value of 00h, until the FDC clock has
stabilized and the internal registers have been initialized.
When the FDC is ready to receive a new command, it reports a value of 80h for the MSR to the microprocessor.
System software can poll the MSR until the MSR is ready.
The MSR must report an 80h value (RQM set to 1) within
2.5 msec after reset or power up.
FIGURE 5-9. MSR Register Bitmap
Bit 0 - Drive 0 Busy
This bit indicates whether or not drive 0 is busy.
It is set to 1 after the last byte of the command phase of
a SEEK or RECALIBRATE command is issued for drive
0.
This bit is cleared to 0 after the first byte in the result
phase of the SENSE INTERRUPT command is read for
drive 0.
0: Not busy.
1: Busy.
Bit 1 - Drive 1 Busy
This bit indicates whether or not drive 1 is busy.
It is set to 1 after the last byte of the command phase of
a SEEK or RECALIBRATE command is issued for drive
1.
This bit is cleared to 0 after the first byte in the result
phase of the SENSE INTERRUPT command is read for
drive 1.
0: Not busy.
1: Busy.
Bit 7 (MSEN1) Bit 6 (MSEN0) Media Type
0 0 5.25"
0 1 2.88 M
1 0 1.44 M
1 1 720 K
76543210
Reset
Required
00000000
Main Status
Register (MSR)
Offset 04h
Drive 2 Busy
Non-DMA Execution
Data I/O Direction
RQM
Drive 1 Busy
Drive 3 Busy
Command in Progress
Drive 0 Busy
Read Operations
Loading...