Datasheet PBL38630-2QNS, PBL38630-2QNT, PBL38630-2SHT, PBL38630-2SOS, PBL38630-2SOT Datasheet (Ericsson)

Page 1

Description

The PBL 386 30/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in Digital Loop Carrier, FITL and other telecommunications equipment. The PBL 386 30/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications.

The PBL 386 30/2 emulates resistive loop feed, programmable between 2x50 Ω and 2x900 Ω, with short loop current limiting adjustable to max 45 mA. In the current limited region the loop feed is nearly constant current with a slight slope corresponding to 2x30kΩ.

A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control.

The SLIC incorporates loop current and ring trip detection functions. The PBL 386 30/2 is compatible with loop start signaling.

Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable two-wire impendance, complex or real, is set by a simple external network.

Longitudinal voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet the DLC requirements.

The PBL 386 30/2 package options are 24-pin SSOP, 24-pin SOIC and 28-pin PLCC.

Figure 1. Block diagram.

March 2000

PBL 386 30/2

Subscriber Line

Interface Circuit

Key Features

• 24-pin SSOP package

• High and low battery supply with automatic switching

• 65 mW on-hook power dissipation in active state

• On-hook transmission

• Long loop battery feed tracks Vbat for maximum line voltage

• Only +5 V feed in addition to battery

• Selectable transmit gain (1x or 0.5x)

• No power-up sequence

• Programmable signal headroom

• 43V open loop voltage @ -48V battery feed

• Constant loop voltage for line leakage <5 mA (RLeak ~ >10 kΩ @ -48V)

• Full longitudinal current capability during on-hook state

• Analog over temperature protection permits transmission while the protection circuit is active

• Integrated Ring Relay Driver

• -40°C to +85°C ambient temperature range

24-pin SOIC, 24-pin SSOP, 28-pin PLCC

RRLY

DET

PSG

REF

PLD

PLC

VTX

RSN

PTG

BGND

AGND

VBAT

VBAT2

VCC

RINGX

TIPX

Ring Relay

Driver

Input

Decoder

and

Control

Ring Trip

Comparator

Line Feed Controller

and

Longitudinal

Signal

Suppression

Off-hook Detector

VF Signal

Transmission

Two-wire Interface

POV

PBL 386 30/2

PBL

38630/2

PBL 386 30/2

Page 2

PBL 386 30/2

Maximum Ratings

Parameter Symbol Min Max Unit

Temperature, Humidity

Storage temperature range

Stg

-55 +150 °C

Operating temperature range

Amb

-40 +110 °C

Operating junction temperature range, Note 1

-40 +140 °C

Power supply, -40 °C ≤ T

Amb

≤ +85 °C

with respect to A/BGND V

-0.4 6.5 V

Bat2

with respect to A/BGND V

Bat2

Bat

0.4 V

Bat

with respect to A/BGND, continuous V

Bat

-75 0.4 V

Bat

with respect to A/BGND, 10 ms V

Bat

-80 0.4 V

Power dissipation

Continuous power dissipation at T

Amb

≤ +85 °CP

1.5 W

Ground

Voltage between AGND and BGND V

-0.3 0.3 V

Relay Driver

Ring relay supply voltage BGND+14 V

Ring trip comparator

Input voltage V

, V

Bat

AGND V

Input current I

, I

-5 5 mA

Digital inputs, outputs (C1, C2, DET) Input voltage V

-0.4 V

Output voltage V

-0.4 V

TIPX and RINGX terminals, -40°C < T

Amb

< +85°C, V

Bat

= -50V

Maximum supplied TIPX or RINGX current I

TIPX

, I

RINGX

-100 +100 mA

TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 VTA, V

-80 2 V

TIPX or RINGX, pulse < 10 ms, t

Rep

> 10 s, Note 2 VTA, V

Bat

-10 5 V

TIPX or RINGX, pulse < 1 µs, t

Rep

> 10 s, Note 2 VTA, V

Bat

-25 10 V

TIPX or RINGX, pulse < 250 ns, t

Rep

> 10 s, Notes 2 & 3 VTA, V

Bat

-35 15 V

Recommended Operating Condition

Parameter Symbol Min Max Unit

Ambient temperature T

Amb

-40 +85 °C

with respect to AGND V

4.75 5.25 V

Bat

with respect to AGND V

Bat

-58 -8 V

AGND with respect to BGND V

-100 100 mV

Notes

1. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability.

2. With the diodes DVB and D

VB2

included, see figure 11.

3. R

and RF2 ≥ 20 Ω is also required. Pulse is applied to TIP and RING outside RF1 and RF2.

Page 3

PBL 386 30/2

Electrical Characteristics

-40 °C ≤ T

Amb

≤ +85 °C, PTG = open (see pin description), VCC = +5V ±5 %, V

Bat

= -58V to -40V, V

Bat2

= -32 V, RLC=32.4 kΩ,

= 27 mA. RL = 600 Ω, RF1= RF2 = 0, R

Ref

= 49.9 kΩ, CHP = 47 nF, CLP=0.15 µF, RT = 120 kΩ, RSG = 0 kΩ, RRX = 60 kΩ,

= 52.3 kΩ ROV = ∞, unless otherwise specified. Current definition: current is positive if flowing into a pin.

Ref

Parameter fig Conditions Min Typ Max Unit

Two-wire port

Overload level, V

TRO ,ILdc

> 18mA 2 Active state,

1% THD, R

= ∞ 2.7 V

Peak

On-Hook, I

Ldc

< 5mA Note 1 1.1 V

Peak

Input impedance, Z

Note 2 ZT/200

Longitudinal impedance, Z

LOT

, Z

LOR

0 < f < 100 Hz 20 35 Ω/wire

Longitudinal current limit, I

LOT

, I

LOR

active state 28 mA

rms

/wire

Longitudinal to metallic balance, B

IEEE standard 455-1985, Z

TRX

=736Ω

0.2 kHz < f < 1.0 kHz, T

amb

0-70°C63 66 dB

1.0 kHz < f < 3.4 kHz, T

amb

0-70°C60 66 dB

0.2 kHz < f < 1.0 kHz, T

amb

-40-85°C60 66 dB

1.0 kHz < f < 3.4 kHz, T

amb

-40-85°C55 66 dB

Longitudinal to metallic balance, B

LME

Longitudinal to four wire balance B

LFE

3 0.2 kHz < f < 1.0 kHz, T

amb

0-70°C63 66 dB

1.0 kHz < f < 3.4 kHz, T

amb

0-70°C60 66 dB

0.2 kHz ≤ f ≤ 1.0 kHz, T

amb

-40-85°C60 66 dB

1.0 kHz < f < 3.4 kHz, T

amb

-40-85°C55 66 dB

Metallic to longitudinal balance, B

MLE

4 0.2 kHz < f < 3.4 kHz 40 50 dB

VTR

MLE

= 20 · Log ; ERX = 0

Figure 2. Overload level, V

TRO

, two-wire

port

1 << R

, RL= 600 Ω

ωC R

= 120 kΩ, RRX = 60 kΩ

Figure 3. Longitudinal to metallic (B

LME

)

and Longitudinal to four-wire (B

LFE

)

balance

<< 150 Ω, R

LR =RLT

=RL /2=300Ω

ωC R

= 120 kΩ, RRX = 60 kΩ

LME

= 20 · Log

LFE

= 20 · Log

PBL 386 30/2

TIPX

RINGX

RSN

VTX

TRO

LDC

PBL 386 30/2

TIPX

RINGX RSN

VTX

Page 4

PBL 386 30/2

Parameter fig Conditions Min Typ Max Unit

Four-wire to longitudinal balance, B

FLE

4 0.2 kHz < f < 3.4 kHz 40 50 dB

FLE

= 20 · Log

Two-wire return loss, r |ZTR + ZL|

r = 20 · Log

- ZL|

0.2 kHz < f < 1.0 kHz 30 35 dB

1.0 kHz < f < 3.4 kHz, Note 3 20 22 dB

TIPX idle voltage, V

active, IL < 5 mA - 1.3 V

RINGX idle voltage, V

active, IL < 5 mA V

Bat

+3.0 V

active, IL < 5 mA V

Bat

+4.3 V

Four-wire transmit port (VTX) Overload level, V

TXO

, IL > 18mA 5 Load impedance > 20 kΩ, 2.7 V

Peak

1% THD, Note 4

On-hook, I

< 5mA 1.1 V

Peak

Output offset voltage, ∆V

-100 0 100 mV

Output impedance, z

0.2 kHz < f < 3.4 kHz 15 50 Ω

Four-wire receive port (RSN) Receive summing node (RSN) DC voltage I

RSN

= -55 µA 1.15 1.25 1.35 V Receive summing node (RSN) impedance 0.2 kHz < f < 3.4 kHz 8 20 Ω Receive summing node (RSN) 0.3 kHz < f < 3.4 kHz current (I

RSN

) to metallic loop current (IL) 200 ratio

gain,α

RSN

Frequency response

Two-wire to four-wire, g

2-4

6 relative to 0 dBm, 1.0 kHz. ERX = 0 V

0.3 kHz < f < 3.4 kHz -0.20 0.10 dB f = 8.0 kHz, 12 kHz, 16 kHz -1.0 0.1 dB

Figure 4. Metallic to longitudinal and fourwire to longitudinal balance

1 << 150 Ω, R

= RLR = RL /2 =300Ω

ωC R

= 120 kΩ, RRX = 60 kΩ

Figure 5. Overload level, V

TXO

, four-wire

transmit port

1 << R

, RL = 600 Ω

ωC R

= 120 kΩ, RRX = 60 kΩ

Ref

PBL 386 30/2

TIPX

RINGX RSN

VTX

LDC

TXO

PBL 386 30/2

TIPX

RINGX RSN

VTX

Page 5

PBL 386 30/2

Four-wire to two-wire, g

4-2

6 relative to 0 dBm, 1.0 kHz. EL=0 V

0.3 kHz < f < 3.4 kHz -0.2 0.1 dB f = 8 kHz, 12 kHz, -1.0 0 dB 16 kHz -2.0 0 dB

Four-wire to four-wire, g

4-4

6 relative to 0 dBm, 1.0 kHz, EL=0 V

0.3 kHz < f < 3.4 kHz -0.2 0.1 dB

Insertion loss

Two-wire to four-wire, G

2-4

6 0 dBm, 1.0 kHz, Note 5

2-4

= 20 · Log ; ERX = 0 -0.2 0.2 dB

PTG = AGND -6.22 -6.02 -5.82 dB

Four-wire to two-wire, G

4-2

6 0 dBm, 1.0 kHz, Note 6

4-2

= 20 · Log ; EL = 0 -0.2 0.2 dB

Gain tracking

Two-wire to four-wire 6 Ref. -10 dBm, 1.0 kHz, Note 7

-40 dBm to +3 dBm -0.1 0.1 dB

-55 dBm to -40 dBm -0.2 0.2 dB

Four-wire to two-wire 6 Ref. -10 dBm , 1.0 kHz

-40 dBm to +3 dBm -0.1 0.1 dB

-55 dBm to -40 dBm -0.2 0.2 dB

Noise

Idle channel noise at two-wire C-message weighting 12 dBrnC (TIPX-RINGX) or four-wire (VTX) output Psophometrical weighting -78 dBmp

Note 8

Harmonic distortion

Two-wire to four-wire 6 0 dBm -67 -50 dB Four-wire to two-wire 0.3 kHz < f < 3.4 kHz -67 -50 dB

Battery feed characteristics

Loop current, I

, in the current 12 18mA ≤ IL ≤ 45 mA 0.92 I

1.08 ILmA

limited region, reference A, B & C Open circuit state loop current, I

LOC

RL = 0Ω -100 0 100 µA

Ref

Parameter fig Conditions Min Typ Max Unit

Figure 6. Frequency response, insertion loss, gain tracking.

1 << R

, RL = 600 kΩ

ωC

= 120 kΩ, RRX = 60 kΩ

PBL 386 30/2

TIPX

RINGX RSN

VTX

LDC

Page 6

PBL 386 30/2

Loop current detector

Programmable threshold, I

LTh

500

0.85·I

LThILTh

1.15·I

LTh

RLD in kΩ, I

LTh

≥ 7 mA

Ring trip comparator

Offset voltage, ∆V

DTDR

Source resistance, RS = 0 Ω -20 0 20 mV

Input bias current, I

IB = (IDT + IDR)/2 -200 -20 200 nA

Input common mode range, V

, V

Bat

+1 -1 V

Ring relay driver

Saturation voltage, V

IOL = 50 mA 0.2 0.5 V

Off state leakage current, I

= 12 V 10 µA

Digital inputs (C1, C2) Input low voltage, V

0 0.5 V

Input high voltage, V

2.5 V

Input low current, I

VIL = 0.5 -50 µA

Input high current, I

VIH = 2.5 V 50 µA Detector output (DET) Output low voltage I

= 0.5 mA 0.7 V

Internal pull-up resistor 15 kΩ Power dissipation (V

Bat

= -48V,V

Bat2

= -32V)

Open circuit state, C1, C2 = 0, 0 10 15 mW

Active state, C1, C2 = 0, 1 P

Longitudinal current = 0 mA, I L=0 mA (on-hook) 65 85 mW P

RL =300Ω (off-hook) 730 mW P

RL =800Ω (off-hook) 360 mW

Power supply currents (V

Bat

= -48V)

current, I

Open circuit state 1.2 2.0 mA V

Bat

current, I

Bat

-0.10 -0.05 mA

current, I

Active state 2.8 4.0 mA V

Bat

current, I

Bat

On-hook, Long Current = 0 mA -1.5 -1.0 mA

Power supply rejection ratios

to 2- or 4-wire port Active State 30 42 dB

Bat

to 2- or 4-wire port f= 1kHz, Vn = 100mV 36 45 dB

Bat2

to 2- or 4-wire port 40 60 dB

Temperature guard

Junction threshold temperature, T

145 °C

Thermal resistance

28-pin PLCC, θ

JP28plcc

39 °C/W

24-pin SOIC, θ

JP24soic

43 °C/W

24-pin SSOP, θ

JP24ssop

55 °C/W

Parameter fig Conditions Min Typ Max Unit

Ref

Page 7

PBL 386 30/2

Notes

1. The overload level can be adjusted with the R

resistor

for higher levels e.g. min 3.1 V

Peak

and is specified at the two-wire port with the signal source at the four-wire receive port.

2. The two-wire impedance is programmable by selection of external component values according to:

TRX

= ZT/|G

2-4S α RSN

| where:

TRX

= impedance between the TIPX and RINGX

terminals

ZT= programming network between the VTX and RSN

terminals

2-4S

= transmit gain, nominally = 1 (or 0.5 see pin PTG)

RSN

= receive current gain, nominally = 200 (current

defined as positive flowing into the receivesumming node, RSN, and when flowing from ring to tip).

3. Higher return loss values can be achieved by adding a reactive component to R

, the two-wire terminating

impedance programming resistance, e.g. by dividing R

into two equal halves and connecting a capacitor from the common point to ground.

4. The overload level level can be adjusted with the R

resistor for higher levels e.g. min 3.1 V

Peak

and is specified at the four-wire transmit port, VTX, with the signal source at the two-wire port. Note that the gain from the two-wire port to the four-wire transmit port is G

2-4S

= 1 (or 0.5 see

pin PTG)

5. Pin PTG = Open sets transmit gain to nom. 0.0dB Pin PTG = AGND sets transmit gain to nom. -6.02 dB Secondary protection resistors RF impact the insertion loss as explained in the text, section Transmission. The specified insertion loss is for R

= RP = 0.

6. The specified insertion loss tolerance does not include errors caused by external components.

7. The level is specified at the two-wire port.

8. The two-wire idle noise is specified with the port terminated in 600 Ω (R

) and with the four-wire receive

port grounded (E

= 0; see figure 6). The four-wire idle noise at VTX is specified with the twowire port terminated in 600 Ω (RL). The noise specification is referenced to a 600 Ω programmed two-wire impedance level at VTX. The four-wire receive port is grounded (E

= 0).

Page 8

PBL 386 30/2

Pin Description

Figure 7. Pin configuration, 24-pin SSOP, 24-pin SOIC and 28 pin PLCC package, top view.

Refer to figure 7.

PLCC Symbol Description

1 PTG Prog. Transmit Gain. Left open transmit gain = 0.0 dB, connected to AGND transmit gain = -6.02 dB. 2 RRLY Ring Relay driver output. The relay coil may be connected to maximum +14V. 3 HP Connection for High Pass filter capacitor, CHP. Other end of CHP connects to TIPX. 4NCNo internal Connection 5 RINGX The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage

protection components and ring relay (and optional test relay). 6 BGND Battery Ground, should be tied together with AGND. 7 TIPX The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage

protection components and ring relay (and optional test relay). 8 VBAT Battery supply Voltage. Negative with respect to AGND. 9 VBAT2 An optional second (2) Battery Voltage connects to this pin. 10 PSG Programmable Saturation Guard. The resistive part of the DC feed characteristic is programmed by a

resistor connected from this pin to VBAT. 11 NC No internal Connection 12 LP Connection for Low Pass filter capacitor, C

. Other end of CLP connects to VBAT.

13 DT Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic

level low, indicating off-hook condition. The external ring trip network connects to this input. 14 DR Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic

level low, indicating off-hook condition. The external ring trip network connects to this input.

1 2 3 4 5 6 7 8

9 10 11

24 23 22 21 20 19 18 17 16 15 14

RRLY

PTG

RINGX

BGND

TIPX

VBAT

POV

VTX AGND

RSN REF

PLD VCC

PSG

PLC

VBAT2

DET

24-pin SOIC

and

24-pin SSOP

5 6 7 8

9 10 11

25 24 23 22 21 20 19

PTG

RRLY

BGND

TIPX

VBAT

VBAT2

PSG

DET

VCC

PLD

POV

PLC

REF

AGND

RSN

VTX

RINGX

28-pin PLCC

Page 9

PBL 386 30/2

SLIC Operating States

State C2 C1 SLIC operating state Active detector

0 0 0 Open circuit 1 0 1 Ringing state Ring trip detector (active low) 2 1 0 Active state Loop detector (active low) 3 1 1 Not applicable -

Table 1. SLIC operating states.

15 NU Pin Not Used. Must be connected to AGND. 16 C2 C1 and C2 are digital inputs (internal pull-up) controlling the SLIC operating states.

17 C1 Refer to section "Operating states" for details. 18 DET Detector output. Active low when indicating loop detection and ring trip. 19 NC No internal Connection 20 VCC +5 V power supply. 21 PLD Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor

connected from this pin to AGND.

22 POV Programmable Overhead Voltage. If pin is left open: The overhead voltage is internally set to min 2.7 V in

off-hook and min 1.1 V in On-hook. If a resistor is connected between this pin and AGND: the overhead voltage can be set to higher values.

23 PLC Prog. Line Current, the current limit, reference C in figure 12, is programmed by a resistor connected from

this pin to AGND. 24 REF A Reference, 49.9 kΩ, resistor should be connected from this pin to AGND. 25 NC No internal Connection 26 RSN Receive Summing Node. 200 times the AC-current flowing into this pin equals the metallic (transversal)

AC-current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain

connect to the receive summing node. A resistor should be connected from this pin to AGND. 27 AGND Analog Ground, should be tied together with BGND. 28 VTX Transmit vf output. The AC voltage difference between TIPX and RINGX, the AC metallic voltage, is

reproduced as an unbalanced GND referenced signal at VTX with a gain of one (or one half, see pin PTG).

The two-wire impedance programming network connects between VTX and RSN.

Page 10

PBL 386 30/2

Functional Description and Applications Information

Transmission

General

A simplified ac model of the transmission circuits is shown in figure 8. Circuit analysis yields:

(1)

(2)

= EL - IL · Z

(3)

where: V

is a ground referenced version of the ac metallic voltage between the TIPX and RINGX terminals.

2-4S

is the programmable SLIC two-wire to four-wire gain (transmit direction). See note below.

VTRis the ac metallic voltage between

tip and ring.

is the line open circuit ac metallic voltage.

is the ac metallic current.

is a fuse resistor. RPis part of the SLIC protection Z

is the line impedance. Z

determines the SLIC TIPX to RINGX

impedance at voice frequencies. ZRXcontrols four- to two-wire gain.

VZV

TXTRX

RXLRSN

VRXis the analog ground referenced re-

ceive signal.

RSN

is the receive summing node current to metallic loop current gain = 200.

Note that the SLICs two-wire to four-wire gain, G

2-4S

, is user programmable between two fix values. Refer to the datasheets for values on G

2-4S

Two-Wire Impedance

To calculate Z

, the impedance presented to the two-wire line by the SLIC including the fuse and protection resistors RF and RP, let:

= 0.

From (1) and (2):

Thus with Z

, α

RSN

, G

2-4S

, RP and RF known:

Two-Wire to Four-Wire Gain

From (1) and (2) with VRX = 0:

Four-Wire to Two-Wire Gain

From (1), (2) and (3) with EL = 0:

For applications where ZT/(α

RSN·G2-4S

) + 2RF + 2RP is chosen to be

equal to ZL the expression for G

4-2

simplifies

to:

Four-Wire to Four-Wire Gain

From (1), (2) and (3) with E

= 0:

Hybrid Function

The hybrid function can easily be implemented utilizing the uncommitted amplifier in conventional CODEC/filter combinations. Please, refer to figure 9. Via impedance Z

a current proportional to VRX is injected into the summing node of the combination CODEC/filter amplifier. As can be seen from the expression for the four-wire to four-wire gain a voltage proportional to V

is returned to VTX. This voltage is converted by RTX to a current flowing into the same summing node. These currents can be made to cancel by letting:

The four-wire to four-wire gain, G

4-4

, includes the required phase shift and thus the balance network ZB can be calculated from:

Figure 8. Simplified ac transmission circuit.

TXTXRX

+==00()

RX S4224

−

=− ⋅

IR R

LFP

=+⋅+

−24

22()

RSN S

⋅

−α24

ZGZRR

T RSN S TR F P

=⋅ ⋅−−

−α24

22()

V V

TX TR

T RSN

RSN S

−

⋅

/ α

V V

GZRR

TR RX

RSN

SL F P

−

−⋅ +⋅++

()

V V

GZRR

TX RX

SL F P

RSN

SL F P

−

−⋅

⋅+ +

+⋅++

()

V V

GZRR

BTX

RSN

SL F P

=− ⋅ =

⋅⋅

+⋅++

⋅++

−

()

PBL 386 30/2

VTX

RSN

/α

RSN

TIPX

RINGX

TIP

RING

2-4S

Page 11

PBL 386 30/2

When choosing RTX, make sure the output load of the VTX terminal is >20 kΩ.

If calculation of the ZB formula above yields a balance network containing an inductor, an alternate method is recommended. Contact Ericsson Microelectronics for assistance.

The PBL 386 30/2 SLIC may also be used together with programmable CODEC/ filters. The programmable CODEC/filter allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hardware. In addition, the transmit and receive gain may be adjusted. Please, refer to the programmable CODEC/filter data sheets for design information.

Longitudinal Impedance

A feed back loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase.

Thus longitudinal disturbances will appear as longitudinal currents and the TIPX and RINGX terminals will experience very small longitudinal voltage excursions, leaving metallic voltages well within the SLIC common mode range.

The SLIC longitudinal impedance per wire, Z

LoT

and Z

LoR

, appears as typically 20Ω to longitudinal disturbances. It should be noted that longitudinal currents may exceed the dc loop current without disturbing the vf transmission.

Capacitors CTC and C

The capacitors designated CTC and C

in figure 11, connected between TIPX and ground as well as between RINGX and ground, can be used for RFI filtering. The recommended value for CTC and C

is 2200 pF. Higher capacitance values may be used, but care must be taken to prevent degradation of either longitudinal balance or return loss. CTC and C

contribute to a metallic impedance of 1/(π⋅f⋅CTC) = 1/(π⋅f⋅CRC), a TIPX to ground impedance of 1/(2⋅π⋅f⋅CTC) and a RINGX to ground impedance of 1/(2⋅π⋅f⋅CRC).

Figure 9. Hybrid function.

AC - DC Separation Capacitor, C

The high pass filter capacitor connected between terminals HP and TIPX provides the separation of the ac signal from the dc part. CHP positions the low end frequency response break point of the ac loop in the SLIC. Refer to table 1 for recommended values of CHP. Example: A CHP value of 150 nF will position the low end frequency response 3dB break point of the ac loop at 1,8 Hz (f

3dB

)

according to f

3dB

= 1/(2⋅π⋅RHP⋅CHP) where

RHP = 600 kΩ.

High-Pass Transmit Filter

The capacitor C

in figure 11 connected between the VTX output and the CODEC/ filter forms, together with RTX and/or the input impedance of a programmable CODEC/filter, a high-pass RC filter. It is recommended to position the 3 dB break point of this filter between 30 and 80 Hz to get a faster response for the dc steps that may occur at DTMF signalling.

Capacitor C

The capacitor CLP, which connects between the terminals CLP and VBAT, positions together with the resistive loop feed resistor RSG (see section Battery Feed), the high end frequency break point of the low pass filter in the dc loop in the SLIC. CLP together with RSG, CHP and ZT (see section Two-Wire

Impedance) forms the total two wire output impedance of the SLIC. The choise of these programmable components have an influence on the power supply rejection ratio (PSRR) from VBAT to the two wire side at sub-audio frequencies. At these frequencies capacitor C

also influences the transversal to longitudinal balance in the SLIC. Table 1 suggests suitable values on CLP for different feeding characteristics. Typical values of the transversal to longitudinal balance (T-L bal.) at 200Hz is given in table 1 for the chosen values on C

Feed

T-L bal. C

@200Hz

[Ω][kΩ] [nF] [dB] [nF]

2⋅50 0 150 -46 47 2⋅200 60,4 100 -46 150 2⋅400 147 47 -43 150 2⋅800 301 22 -36 150

Table 1. R

, CLP and CHP values for differ-

ent feeding characteristics.

Combination CODEC/Filter

VTX

RSN

PBL

386 30/2

Page 12

PBL 386 30/2

tions and to fit both single and dual battery feed CODECs. The RSN terminal, connecting to the CODEC receive output via the resistor R

, is dc biased with +1,25V. This makes it possible to compensate for currents floating due to dc voltage differences between RSN and the CODEC output without using any capacitors. This is done by connecting a resistor R

between the RSN terminal and ground. With current directions defined as in figure 13, current summation gives:

where V

CODEC

is the reference voltage of the CODEC at the receive output. From this equation the resistor RR can be calculated as

For values on I

RSN

, see table 3. The resistor RR has no influence on the ac transmission.

SLIC I

RSN

[µA]

PBL 386 30/2 -55

Table 3. The SLIC internal bias current with the direction of the current defined as positive when floating into the terminal RSN.

Battery Feed

The PBL 386 30/2 SLIC emulate resistive loop feed, programmable between 2·50 Ω and 2·900 Ω, with adjustable current limitation. In the current limited region the loop current has a slight slope corresponding to 2·30 kΩ, see figure 12 reference B.

The open loop voltage measured between the TIPX and RINGX terminals is tracking the battery voltage V

Bat

. The sig-

nalling headroom, or overhead voltage V

TRO

, is programmable with a resistor ROV connected between terminal POV on the SLIC and ground. Please refer to section “Programmable overhead voltage(POV)”.

The battery voltage overhead, VOH, depends on the programmed signal overhead voltage. VOH defines the TIP to RING voltage at open loop conditions according to VTR(at IL = 0 mA) = |V

Bat

| - VOH.

Refer to table 2 for typical values on V

and V

OHVirt

. The overhead voltage is changed when the line current is approaching open loop conditions. To ensure maximum open loop voltage, even with a leaking telephone line, this occurs at a line current of approximately 6 mA. When the overhead voltage has changed, the line voltage is kept nearly constant with a steep slope corresponding to 2·25 Ω(reference G in figure 12).

The virtual battery overhead, V

OHvirt

, is defined as the difference between the battery voltage and the crossing point of all possible resistive feeding slopes, see figure 12 reference J. The virtual battery overhead is a theoretical constant needed to be able to calculate the feeding characteristics.

SLIC V

OH(typ)

OHvirt(typ)

(V) (V)

PBL 386 30/2 3.0 +V

TRO

4.9 +V

TRO

Table 2. Battery overhead.

The resistive loop feed (reference D in figure 12) is programmed by connecting a resistor, RSG, between terminals PSG and VBAT according to the equation:

Feed

RSG + 2 · 104

+ 2R

200 where R

Feed

is in Ω for RSG and RF in Ω.

The current limit (reference C in figure

12) is adjusted by connecting a resistor, RLC, between terminal PLC and ground according to the equation:

RLC =

1000

LProg

+ 4

where RLC is in kΩ for I

LProg

in mA.

A second, lower battery voltage may be connected to the device at terminal VBAT2 to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external control. The silent battery switching occurs when the line voltage passes the value |VB2| - 40·IL - (V

OHVirt

-1,3), if IL > 6mA.

For correct functionality it is important to connect the terminal VBAT2 to the second power supply via the diode D

VB2

in figure 11.

An optional diode D

connected between terminal VB and the VB2 power supply, see figure 11, will make sure that the SLIC continues to work on the second battery even if the first battery voltage disappears.

If a second battery voltage is not used, VBAT2 is connected to VBAT on the SLIC and C

VB2

, DBB and D

VB2

are removed.

Metering applications

For designs with metering applications please contact Ericsson Microelectronics for assistance.

CODEC Receive Interface

The PBL 386 30/2 SLIC have got a completely new receive interface at the four wire side which makes it possible to reduce the number of capacitors in the applica-

−=+ +=

− +

IIII

RSN RT RRX RR

CODEC

RX R

125 125 125,, ,

RSN

CODEC

−− −

−

125

Figure 10. Programmable overhead voltage (POV). RL = 600 Ω or ∞.

0 102030405060

off-hook on-hook

TRO

Peak

)

Rov (KΩ)

Page 13

PBL 386 30/2

Figure 11. Single-channel subscriber line interface with PBL 386 30/2 and combination CODEC/filter.

RESISTORS: (Values according to IEC E96 series)

= 0 Ω 1% 1/10 W

= 49,9 kΩ 1% 1/10 W

= User programmable

= 32,4 kΩ 1% 1/10 W

REF

= 49,9 kΩ 1% 1/10 W

= 64,9 kΩ 1% 1/10 W

= 105 kΩ 1% 1/10 W

= 24,9 kΩ 1% 1/10 W

= 22,1 kΩ 1% 1/10 W

= 52,3 kΩ 1% 1/10 W

Depending on CODEC / filter

= 604 kΩ 1% 1/10 W

= 249 kΩ 1% 1/10 W

= 280 kΩ 1% 1/10 W

= 330 Ω 5% 2 W

, R

= Line resistor, 40 Ω 1% match

RP1, R

= 10 Ω 1% 1/10 W,(Note 1)

CAPACITORS: (Values according to IEC E96 series)

= 100 nF 100 V 10%

VB2

= 150 nF 100 V 10%

VCC

= 100 nF 10 V 10%

= 2,2 nF 100 V 10%

= 47 nF 100 V 10%

= 150 nF 100 V 10%

= 100 nF 10 V 10%

= 220 nF 100 V 10%

= 330 nF 63 V 10%

DIODES:

= 1N4448

VB2

= 1N4448

OVP:

Secondary protection ( e. g. Power Innovations TISPPBL2). The ground terminals of the secondary protection should be connected to the common ground on the Printed Board Assembly with a track as short and wide as possible, preferable a groundplane.

REF

VCC

PBL 386 30/2

CODEC/

Filter

SYSTEM CONTROL

INTERFACE

VCC

BGND

TIPX

VBAT

VBAT2

PLC

POV

PLD

VCC

PSG

DET

RRLY

RINGX

AGND

RSN

REF

PTG VTX

DR NU

PBL 386 30/2

VB2

SLIC No. 2 etc.

TIP

RING

OVP

+12 V /+5V

VB2

Programmable overhead

voltage(POV)

With the POV function the overhead

voltage can be increased.

If the POV pin is left open the overhead

voltage is internally set to 3,2 V

Peak

in off-

hook and 1,3 V

Peak

on-hook. If a resistor

is connected between the POV pin and AGND, the overhead voltage can be set to higher values, typical values can be seen in figure 10. The R

and

corresponding V

TRO

(signal headroom) are typical values for THD <1% and the signal frequency 1000Hz.

Observe that the 4-wire output terminal

VTX can not handle more than 3,2 V

Peak.

So if the gain 2-wire to 4-wire is 0dB, 3,2 V

Peak

is maximum also for the 2-wire side. Signal levels between 3,2 and 6,4 V

Peak

on the 2-wire side can be handled with the PTG shorted so that the gain G

2-4S

become -6,02dB. Please note that the two-wire impedance, RR and the 4-wire to 4-wire gain has to be recalculated if the PTG is shorted.

Please note that the maximum signal current at the 2-wire side can not be greater than 9 mA.

How to use POV:

1. Decide what overhead voltage(V

TRO

) is needed. The POV function is only needed if the overhead voltage exceeds 3,2 V

Peak

2. In figure 10 the corresponding ROV for the decided V

TRO

can be found.

3. If the overhead voltage exceeds 3,2 V

Peak

, the G

2-4S

gain has to be changed to -6,02dB by connecting the PTG pin to AGND. Please note that the two-wire impedance, RR and the 4wire to 4-wire gain has to be recalculated.

NOTE:

1. R

and R

may be omitted if D

is in place.

Page 14

PBL 386 30/2

Analog Temperature Guard

The widely varying environmental conditions in which SLICs operate may lead to the chip temperature limitations being exceeded. The PBL 386 30/2 SLIC reduce the dc line current when the chip temperature reaches approximately 145°C and increases it again automatically when the temperature drops. Accordingly transmission is not lost under high ambient temperature conditions.

The detector output, DET, is forced to a logic low level when the temperature guard is active.

Loop Monitoring Functions

The loop current and ring trip detector report their status through a common output, DET. The detector to be connected to DET is selected via the two bit wide control interface C1 and C2. Please refer to section Control Inputs for a description of the control interface.

Loop Current Detector

The loop current detector is indicating that the telephone is off hook and that current is flowing in the loop by putting the output DET to a logical low level when selected.The loop current threshold value, I

LTh

, at which the loop current detector changes state is programmable by selecting the value of resistor RLD. RLD connects between pin PLD and ground and is calcu-

lated according to

500

LTh

The current detector is internally filtered and is not influenced by the ac signal at the two wire side.

Ring Trip Detector

Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. The ringing source can be balanced or unbalanced superimposed on V

or GND. The unbalanced ringing source may be applied to either the ring lead or the tip lead with return via the other wire. A ring relay driven by the SLIC ring relay driver connects the ringing source to tip and ring.

Figure 12. Battery feed characteristics (without the protection resistors on the line).

VTR[V]

[mA]

DC characteristics

A: IL (@ VTR = 0V) = I

LProg

Bat

| - V

OHVirt

- R

Feed

· (I

LProg

+ 4·10-3)

· 10

B: R

feedB

= 2 · 30 kΩ

C: I

LConst

(typ)= I

LProg

- 4·10

-3

VTR = |V

Bat

| - V

OHvirt

- R

Feed

· (I

LProg

+ 4·10-3)

D: R

Feed

+ 2 · 10

200

E: IL ≈ 6 mA

F: Apparent battery V

Bat

(@ IL = 0) =|V

Bat

| - V

OHvirt

- R

Feed

· 4·10-3)

G: R

feedG

= 2 · 25 Ω

H: V

TROpen

= |V

Bat

| - V

J: Virtual battery V

BatVirt

(@ IL = 4 mA) = |V

Bat

| - V

OHVirt

Page 15

PBL 386 30/2

The ring trip function is based on a polarity change at the comparator input when the line goes off-hook. In the on-hook state no dc current flows through the loop and the voltage at comparator input DT is more positive than the voltage at input DR. When the line goes off-hook, while the ring relay is energized, dc current flows and the comparator input voltage reverses polarity.

Figure 11 gives an example of a ring trip detection network. This network is applicable, when the ring voltage is superimposed on V

and is injected on the ring lead of the two-wire port. The dc voltage across sense resistor RRT is monitored by the ring trip comparator input DT and DR via the network R1, R2, R3, R4, C1 and C2. With the line on-hook (no dc current) DT is more positive than DR and the DET output will report logic level high, i.e. the detector is not tripped. When the line goes off-hook, while ringing, a dc current will flow through the loop including sense resistor RRT and will cause input DT to become more negative than input DR. This changes output DET to logic level low, i.e. tripped detector condition. The system controller (or line card processor) responds by de-energizing the ring relay, i.e. ring trip.

Complete filtering of the 20 Hz ac component at terminal DT and DR is not necessary. A toggling DET output can be exam-

ined by a software routine to deter-mine the duty cycle. When the DET output is at logic level low for more than half the time, offhook condition is indicated.

Relay driver

The PBL 386 30/2 SLIC incorporates a ring relay driver designed as open collector (npn) with a current sinking capability of 50 mA. The drive transistor emitter is connected to BGND. The relay driver has an internal zener diode clamp for inductive kick-back voltages. Care must be taken when using the relay driver together with relays that have high impedance.

Control Inputs

The PBL 386 30/2 SLIC have two digital control inputs, C1 and C2.

A decoder in the SLIC interprets the control input condition and sets up the commanded operating state. C1 and C2 are internal pull-up inputs.

Open Circuit State

In the Open Circuit State the TIPX and RINGX line drive amplifiers as well as other circuit blocks are powered down. This causes the SLIC to present a high impedance to the line. Power dissipation is at a

Figure 13. CODEC receive interface.

PBL386 30/2

CODEC

VTX

RSN

RRX

RSN

REFcodec

+1.25 V

DC-GND

minimum and no detectors are active.

Ringing State

The ring relay driver and the ring trip detector are activated and the ring trip detector is indicating off hook with a logic low level at the detector output. The SLIC is in the active normal state.

Active State

TIPX is the terminal closest to ground and sources loop current while RINGX is the more negative terminal and sinks loop current. Vf signal transmission is normal and the loop current detector is activated. The loop current detector is indicating off hook with a logic low level present at the detector output.

Overvoltage Protection

The PBL 386 30/2 SLIC must be protected against overvoltages on the telephone line caused by lightning, ac power contact and induction. Refer to Maximum Ratings, TIPX and RINGX terminals, for maximum allowable continuous and transient currents that

Page 16

PBL 386 30/2

Ordering Information

Package Temp. Range Part No.

24 pin SSOP Tape & Reel -40° - +85° C PBL 386 30/2SHT 24 pin SOIC Tube -40° - +85° C PBL 386 30/2SOS 24 pin SOIC Tape & Reel -40° - +85° C PBL 386 30/2SOT 28 pin PLCC Tube -40° - +85° C PBL 386 30/2QNS 28 pin PLCC Tape & Reel -40° - +85° C PBL 386 30/2QNT

Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics. These products are sold only according to Ericsson Microelectronics' general conditions of sale, unless otherwise confirmed in writing.

Ericsson Microelectronics AB

SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00

This product is an original Ericsson product protected by US, European and other patents.

may be applied to the SLIC.

Secondary Protection

The circuit shown in figure 11 utilizes series resistors together with a programmable overvoltage protector (e.g. Power Innovations TISPPBL2), serving as a secondary protection.

The TISPPBL2 is a dual forward-conducting buffered p-gate overvoltage protector. The protector gate references the protection (clamping) voltage to negative supply voltage (i e the battery voltage, V

). As the protection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimized.

Positive overvoltages are clamped to ground by a diode. Negative overvoltages are initially clamped close to the SLIC negative supply rail voltage and the protector will

crowbar into a low voltage on-state condition, by firing an internal thyristor.

A gate decoupling capacitor, C

, is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. C

shall be placed close to the overvoltage protection device. Without the capacitor even the low inductance in the track to the V

Bat

supply will limit the current and delay the activation of the thyristor clamp.

The fuse resistors R

serve the dual purposes of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross.

If a PTC is chosen for R

, note that it is important to always use PTC´s in series with resistors not sensitive to temperature, as the PTC will act as a capacitance for fast

transients and therefore will not protect the SLIC.

Power-up Sequence

No special power-up sequence is necessary except that ground has to be present before all other power supply voltages.

Printed Circuit Board Layout

Care in PCB layout is essential for proper function. The components connecting to the RSN input should be placed in close proximity to that pin, so that no interference is injected into the RSN pin. Ground plane surrounding the RSN pin is advisable.

Analog ground (AGND) should be connected to battery ground (BGND) on the PCB in one point.

The capacitors for the battery should be connected with short wide leads of the same length.