Datasheet PALLV22V10-15JC, PALLV22V10-15JI, PALLV22V10-15PC, PALLV22V10Z-25JI Datasheet (Lattice Semiconductor Corporation)

COM'L: -7/10/15 IND: -15PALLV22V10

PALLV22V10Z

IND: -25

PALLV22V10 and PALL V22V10Z Families

Low-Voltage (Zero Power) 24-Pin EE CMOS Versatile PAL Device

DISTINCTIVE CHARACTERISTICS

◆

Low-voltage operation, 3.3 V JEDEC compatible

—VCC = + 3.0 V to 3.6 V

Commercial and industrial operating temperature range

◆

7.5-ns t

◆

Electrically-erasable technology provides reconﬁgurable logic and full testability 10 macrocells programmable as registered or combinatorial, and active high or active low to

◆

match application needs

◆

Varied product term distribution allows up to 16 product terms per output for complex functions

◆

Global asynchronous reset and synchronous preset for initialization Power-up reset for initialization and register preload for testability

◆

Extensive third-party software and programmer support

◆

24-pin SKINNY DIP and 28-pin PLCC packages save space

PD

GENERAL DESCRIPTION

The PALLV22V10 is an advanced PAL erasable CMOS technology.

The PALLV22V10Z provides low voltage and zero standby power. At 30 µA maximum standby current, the PALLV22V10Z allows battery powered operation for an extended period.

The PALLV22V10 device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a ﬁxed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs.

The product terms are connected to the ﬁxed OR array with a varied distribution from 8 to 16

USE GAL DEVICES FOR

across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active high or active low. The output conﬁguration is determined by two bits controlling two multiplexers in each macrocell.

®

device built with low-voltage, high-speed, electrically-

NEW DESIGNS

Publication# Amendment/

18956 0

Rev:

F

Issue Date:

September 2000

BLOCK DIAGRAM

1

81012141616141210 8

CLK/I

I1 - I

0

11

PROGRAMMABLE

AND ARRAY

(44 x 132)

11

RESET

OUTPUT

LOGIC

MACRO

CELL

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

PRESET

18956D-001

FUNCTIONAL DESCRIPTION

The P ALL V22V10 is the low-voltage version of the PALCE22V10. It has all the architectural features of the PALCE22V10.

The PALLV2210Z is the low-voltage, zero-power version of the PALCE22V10. It has all the architectural features of the PALCE22V10. In addition, the PALLV22V10Z has zero standby power and an unused product term disable feature.

The P ALLV22V10 allows the systems engineer to implement a design on-chip by programming EE cells to conﬁgure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required time-consuming layout, are

USE GAL DEVICES FOR

lifted from the PC board and placed on silicon, where they can be easily modiﬁed during prototyping or production.

NEW DESIGNS

Product terms with all connections opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state.

The P ALL V22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four potential output conﬁgurations; registered output or combinatorial I/O, active high or active low (see Figure 2). The conﬁguration choice is made according to the user’s design speciﬁcation and

- S

corresponding programming of the conﬁguration bits S

. Multiplexer controls are connected

0

1

to ground (0) through a programmable bit, selecting the “0” path through the multiplexer. Erasing the bit disconnects the control line from GND and it ﬂoats to V

(1), selecting the “1” path.

CC

The device is produced with a EE cell link at each input to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easilyimplemented programming algorithm, these products can be rapidly programmed to any customized pattern.

2 PALLV22V10 and PALLV22V10Z Families

Variable Input/Output Pin Ratio

The PALLV22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to V

or GND.

CC

Registered Output Conﬁguration

Each macrocell of the P ALLV22V10 includes a D-type ﬂip-ﬂop for data storage and synchronization. The ﬂip-ﬂop is loaded on the LOW-to-HIGH transition of the clock input. In the registered conﬁguration (S

= 0), the array feedback is from

1

Q of the ﬂip-ﬂop.

Combinatorial I/O Conﬁguration

Any macrocell can be conﬁgured as combinatorial by selecting the multiplexer path that bypasses the ﬂip-ﬂop (S

= 1). In the combinatorial conﬁguration, the feedback is from the pin.

1

S

10 11 00 01

1

I/O

n

S

1

0 0 Registered/Active Low

S

0

0 1 Registered/Active High 1 0 Combinatorial/Active Low 1 1 Combinatorial/Active High

0 = Programmed EE bit 1 = Erased (charged) EE bit

S

0

Output Conﬁguration

CLK

AR

DQ

Q

SP

0 1

NEW DESIGNS

18956C-004

USE GAL DEVICES FOR

Figure 1. Output Logic Macrocell Diagram

PALLV22V10 and PALLV22V10Z Families 3

AR

DQ

CLK

a. Registered/active low

CLK

c. Registered/active high

Q

SP

AR

DQ

Q

SP

S0 = 0 S1 = 0

b. Combinatorial/active low

S0 = 1 S1 = 0

d. Combinatorial/active high

Figure 2. Macrocell Conﬁguration Options

S0 = 0 S1 = 1

S

= 1

0

S1 = 1

18956D-005

Programmable Three-State Outputs

Each output has a three-state output buffer with three-state control. A product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bi-directional I/O pin, and may be conﬁgured as a dedicated input if the buffer is always disabled.

Programmable Output Polarity

The polarity of each macrocell output can be active high or active low, either to match output

USE GAL DEVICES FOR

NEW DESIGNS

signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts.

Selection is controlled by programmable bit S

in the output macrocell, and affects both registered

0

and combinatorial outputs. Selection is automatic, based on the design speciﬁcation and pin deﬁnitions. If the pin deﬁnition and output equation have the same polarity, the output is programmed to be active high (S

= 1).

0

Preset/Reset

For initialization, the PALLV22V10 has additional preset and reset product terms. These terms are connected to all registered outputs. When the synchronous preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the asynchronous reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock.

4 PALLV22V10 and PALLV22V10Z Families

Note that preset and reset control the ﬂip-ﬂop, not the output pin. The output level is determined by the output polarity selected.

Beneﬁts of Lower Operating Voltage

The PALLV22V10 has an operating voltage range of 3.0 V to 3.6 V. Low voltage allows for lower operating power consumption, longer battery life, and/or smaller batteries for notebook applications.

Because power is proportional to the square of the voltage, reduction of the supply voltage from

5.0 V to 3.3 V signiﬁcantly reduces power consumption. This directly translates to longer battery life for portable applications. Lower power consumption can also be used to reduce the size and weight of the battery. Thus, 3.3 V designs facilitate a reduction in the form factor.

A lower operating voltage results in a reduction of I/O voltage swings. This reduces noise generation and provides a less hostile environment for board design. A lower operating voltage also reduces electromagnetic radiation noise and makes obtaining FCC approval easier.

3.3-V (CMOS) and 5-V (CMOS and TTL) Compatible Inputs and I/O

Input voltages can be at TTL levels. Additionally, the PALLV22V10 can be driven with true 5-V CMOS levels due to special input and I/O buffer circuitry.

Power-Up Reset

All ﬂip-ﬂops power up to a logic LOW for predictable system initialization. Outputs of the PALLV22V10 will depend on the programmed output polarity. The V and the reset delay time is 1000ns maximum.

Register Preload

The registers on the PALLV22V10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be veriﬁed by loading illegal states and observing proper recovery.

Security Bit

After programming and veriﬁcation, a PALLV22V10 design can be secured by programming the security EE bit. Once programmed, this bit defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security bit is programmed, the array will read as if every bit is erased, and preload will be disabled.

USE GAL DEVICES FOR

NEW DESIGNS

rise must be monotonic,

CC

The bit can only be erased in conjunction with erasure of the entire pattern.

Programming and Erasing

The PALLV22V10 can be programmed on standard logic programmers. It also may be erased to reset a previously conﬁgured device back to its unprogrammed state. Erasure is automatically performed by the programming hardware. No special erase operation is required.

PALLV22V10 and PALLV22V10Z Families 5

Quality and Testability

The PALLV22V10 offers a very high level of built-in quality. The erasability of the CMOS PALLV22V10 allows direct testing of the device array to guarantee 100% programming and functional yields.

Technology

The high-speed PALLV22V10 is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be 3.3-V and 5-V device compatible. This technology provides strong input-clamp diodes, output slew-rate control, and a grounded substrate for clean switching.

Zero-Standby Power Mode

The PALLV22V10Z features a zero-standby power mode. When none of the inputs switch for an extended period (typically 30 ns), the PALLV22V10Z will go into standby mode, shutting down most of its internal circuitry. The current will go to almost zero (I maintain the states held before the device went into the standby mode.

<30 µA). The outputs will

CC

If a macrocell is used in registered mode, switching pin CLK/I for that macrocell. If a macrocell is used in combinatorial mode, switching pin CLK/I standby mode status for that macrocell.

This feature reduces dynamic I macrocells are used as registers and only CLK/I mode, but dynamic I current. The use of combinatorial macrocells will add on average 5 mA per macrocell (at 25 MHz) under these same conditions.

When any input switches, the internal circuitry is fully enabled, and power consumption returns to normal. This feature results in considerable power savings for operation at low to medium frequencies.

Product-Term Disable

On a programmed PALLV22V10Z, any product terms that are not used are disabled. Power is cut off from these product terms so that they do not draw current. Product-term disabling results in considerable power savings. This saving is greater at the higher frequencies.

Further hints on minimizing power consumption can be found in a separate document entitled,

Minimizing Power Consumption with Zero-Power PLDs .

will typically be <2 mA. This is because only the CLK/I

CC

USE GAL DEVICES FOR

proportionally to the number of registered macrocells used. If all

CC

is switching, the device will not be in standby

0

NEW DESIGNS

will not affect standby mode status

0

will affect

0

buffer will draw

0

6 PALLV22V10 and PALLV22V10Z Families

LOGIC DIAGRAM

CLK/I01

I

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

GND

(3)

(4)

(5)

(6)

(7)

(9)

(10)

(11)

10 (12)

(13) 12

(14)

24

(2)

2

3

4

5

6

7

8

9

11

0 34 78 11121516 192023242728313235363940 43

0 1

9

10

20

21

33

34

48

49

65

66

82

83

97

98

110

111

121

122

130

131

USE GAL DEVICES FOR

0 34 78 11121516192023242728313235363940 43

NEW DESIGNS

AR

10

1

AR

D

Q

00

1

Q

0

SP

0 1

10

1

AR

D

Q

00

1

Q

0

SP

0 1

10

1

AR

D

Q

00

1

Q

0

SP

0 1

10

1

AR

D

Q

00

1

Q

0

SP

0 1

10

1

AR

D

Q

00

1

Q

0

SP

0 1

10

1

AR

D

Q

00

1

Q

0

SP

0 1

10

1

AR

D

Q

00

1

Q

0

SP

0 1

10

1

AR

D

Q

00

1

0

Q

SP

0 1

10

1

AR

D

Q

00

1

0

Q

SP

0 1

10

1

AR

D

Q

00

1

Q

0

SP

0

SP

1

(28)VCC

(27)

(26)

(25)

(24)

(23)

18

(21)

17

(20)

16

(19)

15

(18)

14

(17)

(16)

I/O923

I/O22

8

I/O21

7

I/O20

6

I/O19

5

I/O

4

I/O

3

I/O

2

I/O

1

I/O

0

I13

11

18956D-006

PALLV22V10 and PALLV22V10Z Families 7

ABSOLUTE MAXIMUM RATINGS

Storage Temperature. . . . . . . . . . . . . .-65 ° C to +150 ° C

Ambient Temperature with

Power Applied . . . . . . . . . . . . . . . . . .-55 ° C to +125 ° C

Supply Voltage with

Respect to Ground . . . . . . . . . . . . . . .-0.5 V to +7.0 V

DC Input Voltage . . . . . . . . . . . . . . . -0.5 V to +5.25 V

DC Output or I/O Pin Voltage . . . . . . -0.5 V to +5.25 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V

Latchup Current (T

Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.

= 0 ° C to +75 ° C) . . . . . . . . 100 mA

A

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T Supply Voltage (V

CC

Respect to Ground. . . . . . . . . . . . . . . +3.0 V to +3.6 V

Industrial (I) Devices

Ambient Temperature (T Supply Voltage (VCC) with

Respect to Ground. . . . . . . . . . . . . . . +3.0 V to +3.6 V

Operating ranges deﬁne those limits between which the functionality of the device is guaranteed.

). . . . . . . . . . . 0 ° C to +75 ° C

A

) with

). . . . . . . . . . -40 ° C to +85 °

A

DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

I

V

OH

Output HIGH Voltage

= V

V

IN

IH

VCC = Min

or V

IL

= -2 mA 2.4 V

OH

= -100 µAV

I

OH

-0.2 V

CC

C

V

OL

V

IH

V

IL

I

IH

I

IL

I

OZH

I

OZL

I

SC

I

(Static) Supply Current

CC

Notes:

1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. V

OUT

Output LOW Voltage V

Input HIGH Voltage

Input LOW Voltage

Input HIGH Leakage Current VIN = VCC, V Input LOW Leakage Current V Off-State Output Leakage

Current HIGH Off-State Output Leakage

Current LOW Output Short-Circuit Current V

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

USE GAL DEVICES FOR

and I

IL

Guaranteed Input Logical HIGH Voltage for all Inputs (Notes 1, 2)

Guaranteed Input Logical LOW Voltage for all Inputs (Notes 1, 2)

NEW DESIGNS

V V

Outputs f = 0 MHz, Open (I

(or IIH and I

OZL

or V

= V

IN

IH

IL

= Max (Note 2) 10 µA

CC IN OUT

IN OUT

OUT

= V

= 0 V, V

= Max (Note 2) -100 µA

CC

= VCC, VCC = Max

or VIL (Note 2)

IH

= 0 V, V

= 0.5 V, VCC = Max (Note 3) -5 -75 mA

= 0 mA)

= Max

CC

or VIL (Note 2)

IH

OZH

).

IOL = 16 mA 0.5 V

= 100 µA 0.2 V

I

OL

2.0 5.25 V

0.8 V

10 µA

-100 µA

-10/15 Commercial 60 mA

-7 75 mA

-15 Industrial 75 mA

8 PALLV22V10 - 7/10/15 (Com’l), -15 (Ind’l)

CAPACITANCE

Parameter

Symbol Parameter Description Test Condition Typ Unit

C

IN

C

OUT

Note:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiﬁed where capacitance may be affected.

1

Input Capacitance VIN = 2.0 V VCC = 3.3 V

T

= 25°C

Output Capacitance V

= 2.0 V 8

OUT

A

f = 1 MHz

5

pF

SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES

1

Parameter

Symbol Parameter Description

t

PD

t

S1

t

S2

t

H

t

CO

t

AR

t

ARW

t

ARR

t

SPR

t

WL

t

WH

f

MAX

t

EA

t

ER

Notes:

1. See “Switching Test Circuit” for test conditions.

2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiﬁed where frequency may be affected.

3. t

CF

t

CF

Input or Feedback to Combinatorial Output 7.5 10 15 ns Setup Time from Input, Feedback or SP to Clock 4.5 5.5 10 ns Setup Time from SP to Clock 5.5 7 10 ns Hold Time 0 0 0 ns Clock to Output 5.5 6.5 10 ns Asynchronous Reset to Registered Output 11 13 20 ns Asynchronous Reset Width 6 8 10 ns Asynchronous Reset Recovery Time 6 8 10 ns Synchronous Preset Recovery Time 6 8 10 ns

Clock Width

Maximum Frequency (Note 2)

Input to Output Enable Using Product Term Control 9 11 15 ns Input to Output Disable Using Product Term Control 10 11 15 ns

is a calculated value and is not guaranteed. tCF can be found using the following equation: = 1/f

(internal feedback) - tS.

MAX

USE GAL DEVICES FOR

LOW 3.5 4 6 ns HIGH 3.5 4 6 ns External Feedback 1/(t Internal Feedback (f No Feedback 1/(t

NEW DESIGNS

) 1/(tS + tCF) (Note 3) 133 110 58.8 MHz

CNT

+ tCO) 100 83.3 50 MHz

S

+ tWL) 143 125 83.3 MHz

WH

-7 -10 -15 UnitMin Max Min Max Min Max

PALLV22V10 - 7/10/15 (Com’l), -15 (Ind’l) 9

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C

Ambient Temperature with

Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C

Supply Voltage with

Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V

DC Input Voltage . . . . . . . . . . . . . . . .-0.5 V to +5.5 V

Industrial (I) Devices

Ambient Temperature (TA). . . . . . . . . . -40°C to +85°C

Supply Voltage (V

Respect to Ground. . . . . . . . . . . . . . . +3.0 V to +3.6 V

Operating ranges deﬁne those limits between which the functionality of the device is guaranteed.

CC

) with

DC Output or I/O Pin Voltage . . . . . . . -0.5 V to +5.5 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V

Latchup Current (TA = -40°C to 85°C). . . . . . . . 100 mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.

DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

I

V

I

IH

I

IL

I

OZH

I

OZL

I

SC

I

CC

OH

OL

IH

IL

= V

V

IN

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input HIGH Leakage Current VIN = VCC, V Input LOW Leakage Current V Off-State Output Leakage

Current HIGH Off-State Output Leakage

Current LOW Output Short-Circuit Current V

Supply Current

USE GAL DEVICES FOR

NEW DESIGNS

IH

VCC = Min

= V

V

IN

IH

VCC = Min Guaranteed Input Logical HIGH

Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW

Voltage for all Inputs (Note 1)

= 0 V, V

IN

V

= VCC, VCC = Max

OUT

V

= V

IN

IH

V

= 0 V, V

OUT

V

= V

IN

IH

= 0.5 V, VCC = Max (Note 3) -5 -75 mA

OUT

Outputs Open (I V

= Max (Note 4)

CC

or V

IL

or V

IL

= Max 10 µA

CC

= Max -10 µA

CC

or VIL (Note 2)

= Max

CC

or VIL (Note 2)

= 0 mA)

OUT

= -2 mA 2.4 V

OH

= -100 µAV

I

OH

I

= 2 mA 0.4 V

OL

= 100 µA 0.2 V

I

OL

f = 0 MHz 30 µA

f = 15 MHz 55 mA

-0.3 V

CC

2.0 5.5 V

0.8 V

10 µA

-10 µA

Notes:

1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

4. This parameter is guaranteed under worst case test conditions. Refer to the I

characteristics.

I

CC

and I

IL

(or IIH and I

OZL

OZH

).

vs. Frequency graph in this datasheet for typical

CC

10 PALLV22V10Z-25

CAPACITANCE

Parameter

Symbol Parameter Description Test Condition Typ Unit

C

IN

C

OUT

Note:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiﬁed where

capacitance may be affected.

Input Capacitance VIN = 2.0 V VCC = 3.3 V Output Capacitance V

1

5

T

= 25°C

= 2.0 V 8

OUT

A

f = 1 MHz

pF

SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES

Parameter

Symbol Parameter Description

t

PD

t

S

t

H

t

CO

t

AR

t

ARW

t

ARR

t

SPR

t

WL

t

WH

f

MAX

t

EA

t

ER

Notes:

1. See “Switching Test Circuit” for test conditions.

2. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the t

3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time

the design is modiﬁed where frequency may be affected.

is a calculated value and is not guaranteed. tCF can be found using the following equation:

4. t

CF

= 1/f

t

CF

Input or Feedback to Combinatorial Output (Note 2) 25 ns Setup Time from Input, Feedback or SP to Clock 15 ns Hold Time 0 ns Clock to Output 15 Asynchronous Reset to Registered Output 25 ns Asynchronous Reset Width 25 ns Asynchronous Reset Recovery Time 25 ns Synchronous Preset Recovery Time 25 ns

Clock Width

Maximum Frequency (Note 3)

Input to Output Enable Using Product Term Control 25 ns Input to Output Disable Using Product Term Control 25 ns

LOW 10 ns HIGH 10 ns External Feedback 1/(t Internal Feedback (f No Feedback 1/(t

) 1/(tS + tCF) (Note 4) 35.7 MHz

CNT

+ tCO) 33.3 MHz

S

+ tWL) 50 MHz

WH

NEW DESIGNS

USE GAL DEVICES FOR

may be slightly faster.

PD

(internal feedback) - tS.

MAX

-25

1

UnitMin Max

PALLV22V10Z-25 11

SWITCHING WAVEFORMS

Input or

Feedback

Combinatorial

Output

Clock

V

T

t

PD

a. Combinatorial output

t

WH

t

V

T

18956D-007

WL

Input or

Feedback

t

S

Clock

Registered

Output

b. Registered output

Input

t

ER

V

T

Output

V

OH OL

V

- 0.5V

+ 0.5V

t

H

T

t

CO

V

T

V

T

18956D-008

V

T

t

EA

V

T

18956D-010

c. Clock width

t

AR

ARW

V

NEW DESIGNS

V

T

.

Input

Asserting

Asynchronous

Notes:

1. V

2. Input pulse amplitude 0 V to 3.0 V

3. Input rise and fall times 2 ns to 5 ns typical.

Reset

Registered

Output

Clock

= 1.5 V for inputs signals and VCC/2 for outputs signals.

T

USE GAL DEVICES FOR

e. Asynchronous reset

18956D-009

T

t

ARR

V

18956D-011

d. Input to output disable/enable

Input

Asserting

Synchronous

Preset

Clock

Registered

T

Output

t

S

f. Synchronous preset

V

T

t

H

t

CO

t

SPR

V

T

18956D-012

V

T

12 PALLV22V10 and PALLV22V10Z Families

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

SWITCHING TEST CIRCUIT

VCC

Must be Steady

May Change from H to L

May Change from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Will be Steady

Will be Changing from H to L

Will be Changing from L to H

Changing, State Unknown

Center Line is HighImpedance “Off” State

18956D-013

Speciﬁcation S

, t

t

PD

CO

t

EA

t

ER

Closed Closed Z → H: Open

Z →L: Closed H →Z: Closed

L →Z: Closed

S

1

R

NEW DESIGNS

USE GAL DEVICES FOR

1

Output

S

Z → H: Closed Z →L: Open

H → Z: Closed L →Z: Open

2

1

Test Point

R

2

S

2

30 pF

C

5 pF

C

L

18956D-014

Measured

L

R

1

1.6K Ω 1.6K Ω

R

2

Output Value

/2

V

CC

V

/2

CC

H → Z: VOH - 0.5 V L →Z: V

+ 0.5 V

OL

PALLV22V10 and PALLV22V10Z Families 13

TYPICAL I

CHARACTERISTICS

CC

VCC = 3.3 V, TA = 25°C

150

140

130

120

110

100

90

80

(mA)

I

CC

70

60

50

40

30

20

10

0

0 5 10 15 20

The selected “typical” pattern utilized 50% of the de vice resources . Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching.

By utilizing 50% of the device, a midpoint is deﬁned f or I to estimate the I

CC

USE GAL DEVICES FOR

requirements for a particular design.

NEW DESIGNS

25 30 35 40 45

Frequency (MHz)

ICC vs. Frequency

. From this midpoint, a designer may scale the ICC graphs up or down

CC

PALLV22V10-7

PALLV22V10-10/15

50

18956D-015

14 PALLV22V10 and PALLV22V10Z Families

ENDURANCE CHARACTERISTICS

The P ALL V22V10 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed—a feature which allows 100% testing at the factory.

Symbol Parameter Test Conditions Value Unit

t

DR

N Min Reprogramming Cycles Normal Programming Conditions 100 Cycles

Min Pattern Data Retention Time

Max Storage Temperature 10 Years Max Operating Temperature 20 Years

ROBUSTNESS FEATURES

The PALLV22V10 has some unique features that make it extremely robust, especially when operating in high speed design environments. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise ﬁlter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns.

INPUT/OUTPUT EQUIVALENT SCHEMATICS

V

CC

V

CC

ESD

Protection

and

Clamping

> 50 KΩ

Programming Pins only

USE GAL DEVICES FOR

NEW DESIGNS

Programming

Detection

Typical Input

V

CC

5-V

Protection

Provides ESD Protection and Clamping

Voltage

Preload

Circuitry

Positive

Overshoot

Filter

Feedback

Input

Programming

Circuitry

Typical Output

PALLV22V10 and PALLV22V10Z Families 15

18956D-017

POWER-UP RESET

The power-up reset feature ensures that all ﬂip-ﬂops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways V to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are:

can rise

CC

◆ The V

◆ Following reset, the clock input must not be driven from LOW to HIGH until all applicable input

rise must be monotonic.

CC

and feedback setup times are met.

Parameter

Symbol Parameter Description Max Unit

t

PR

t

S

t

WL

Registered Active-Low

Power-Up Reset Time 1000 ns Input or Feedback Setup Time

Characteristics

Power

Output

Clock

Clock Width LOW

2.7 V

t

PR

t

S

See Switching

V

CC

t

NEW DESIGNS

USE GAL DEVICES FOR

16 PALLV22V10 and PALLV22V10Z Families

Figure 3. Power-Up Reset Waveform

WL

18956D-018

TYPICAL THERMAL CHARACTERISTICS

PALLV22V10-10

Measured at 25°C ambient. These parameters are not tested.

Parameter

Symbol Parameter Description

θjc Thermal impedance, junction to case 26 20 °C/W θja Thermal impedance, junction to ambient 86 69 °C/W

200 lfpm air 72 57 °C/W

θjma Thermal impedance, junction to ambient with air ﬂow

Plastic θjc Considerations

θ

The data listed for plastic heat-ﬂow paths in plastic-encapsulated devices are complex, making the age surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, perature. Therefore, the measurements can only be used in a similar environment.

θ

jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant tem-

jc are for reference only and are not recommended for use in calculating junction temperatures. The

400 lfpm air 65 52 °C/W 600 lfpm air 60 47 °C/W 800 lfpm air 55 45 °C/W

θ

jc measurement relative to a speciﬁc location on the pack-

Typ

UnitSKINNY DIP PLCC

NEW DESIGNS

USE GAL DEVICES FOR

PALLV22V10 and PALLV22V10Z Families 17

CONNECTION DIAGRAMS

Top View

SKINNY DIP

CLK/I

GND

Note:

Pin 1 is marked for orientation.

1

0

I

2

1

I

3

2

I

4

3

I

5

4

I

6

5

I

7

6

I

8

7

I

9

8

I

10

9

I

11

10

12

PLCC

V

24 23 22 21 20 19 18 17 16 15 14 13

CC

I/O

9

I/O

8

I/O

7

I/O

6

I/O

5

I/O

4

I/O

3

I/O

2

I/O

1

I/O

0

I

11

18956D-002 18956D-003

NC

I

3

I

4

I

5

I

6

I

7

I

8

I2I1CLK/I0NC

4

3 2 1 28 27 26 5 6 7 8 9 10 11

12 13 14 15 16 17 18

9

I

10

I

GND

NC

VCCI/O9I/O

11

I

I/O0I/O

8

25

I/O

7

24

I/O

6

23

I/O

5

22

GND/NC

21

I/O

4

20

I/O

3

19

I/O

2

1

PIN DESIGNATIONS

CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect V

= Supply Voltage

CC

USE GAL DEVICES FOR

NEW DESIGNS

18 PALLV22V10 and PALLV22V10Z Families

ORDERING INFORMATION

L T

Commercial and Industrial Products

attice/Vantis programmable logic products for commercial and industrial applications are available with several ordering options.

he order number (Valid Combination) is formed by a combination of these elements:

LV

PAL

V10 -7JC

22

FAMILY TYPE

PAL = Programmable Array Logic

TECHNOLOGY

LV = Low-Voltage

NUMBER OF ARRAY INPUTS

OUTPUT TYPE

V = Versatile

NUMBER OF OUTPUTS SPEED

Z = Zero Power

(30 µA I

PALLV22V10-7 JC PALLV22V10-10 PC, JC PALLV22V10-15 PC, JC, JI PALLV22V10Z-25 PI, JI

Standby)

CC

Valid Combinations

The V alid Combinations list conﬁgurations planned to be supported in volume for this device. Consult the local Lattice/Vantis sales ofﬁce to conﬁrm availability of speciﬁc valid combinations and to check on newly released combinations.

OPERATING CONDITIONS

C = Commercial (0°C to +75°C) I = Industrial (-40°C to +85°C)

PACKAGE TYPE

P = 24-Pin 300 mil Plastic

SKINNYDIP (PD3024)

J = 28-Pin Plastic Leaded

Chip

-7 = 7.5 ns t

-10 = 10 ns t

-15 = 15 ns t

-25 = 25 ns t

Valid Combinations

PD PD PD PD

NEW DESIGNS

USE GAL DEVICES FOR

PALLV22V10 and PALLV22V10Z Families 19