Datasheet PACNLT101Q Datasheet (California Micro Devices)

Page 1
Non-Linear High Speed Termination IC
n
n
r
PACNLT101
Features
• 16 channel, dual rail clamping action in a single package
• Provides bus termination independent of line impedance or loading conditions
• Uses CAMD’s patented EZterm™ technology
• 24-pin QSOP package saves board space and eases layout in space critical areas.
• One IC replaces and outperforms up to 32 discrete components.
• Enable pin included
Product Description
CAMD’s non-linear termination IC is specifically de­signed to minimize overshoot/undershoot disturbances caused by impedance mismatch reflections and noise on high-speed transmission lines.
Reflections on high-speed data lines lead to voltage overshoot and undershoot disturbances, which may result in data loss or improper system operation. Resis­tive terminations, when used to terminate these high­speed data lines, increase power consumption and degrade output levels, resulting in reduced noise immu­nity. Clamping-type termination is the best overall solution for applications in which these may be consider­ations.
This highly integrated non-linear termination IC provides very effective termination performance for high-speed data lines under variable loading conditions. The device supports up to 16 terminated lines per package – each of which are clamped to both ground and power supply rail. A typical application may use 4 devices to replace (and outperform) 64 conventional Schottky diode pairs; thus providing significant reductions in component and assembly costs, improvements in manufacturing effi­ciency and reliability, and savings in allocated board area for space-critical designs.
Application
• High speed, low voltage buses
Pin Configuratio
Top View
NLT#1
NLT#2
NLT#3
GND
1
2
3
4
5NLT#4 20 NLT#15
6NLT#5 19 NLT#14
7NLT#6 18 NLT#13
8NLT#7 17 NLT#12
9GND 16 GND
10NLT#8 15 NLT#11
11NLT#9 14 Enable
12NLT#10 13 V
PACNLT101
24-Pin QSOP
24
23
22
21
V
DD
V
DD
NLT#16
GND
DD
Standard Part Ordering Informatio
Package Ordering Part Numbe
24 QSOP PACNLT101Q PACNLT101Q
©2001 California Micro Devices Corp. All rights reserved. EZterm™ is a trademark of California Micro Devices
3/8/2001
215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
Style Tape & Reel Part Marking
C1601100
1
Page 2
PACNLT101
gs
g
t
6
3V
T
0
0V
T
5V
T
0
Absolute Maximum Ratin
Parameter Ratin
Maximum DC Voltage on any pin
Minimum DC Voltage on any pin –0.5 V
Continuous current per channel 72 mA
Operating Temperature (Ambient) –40 to 85
Storage Temperature (Ambient) 65 to 150
Power Dissipation @ T = 25
C 0.9 W
˚
.
Operating Characteristics - VDD = 3.3V, Enable = 3.3V, Temperature = –40°C to 85°C
Operating Characteristics
Parameter
Signal Voltage
below GND @ I = –50mA 510 750 mV
current all Channels floating 85 150 mA
V
DD
Enable pin (pin 14) current all Channels floating 10 15 mA
Input Capacitance* Signal voltage = V
Signal voltage = V
ESD protection MIL-STD-883, method 3015*
Response Time 400 ps
*These parameters are guaranteed by design and characterization.
ove V @ I = 50mA
onditions
3.4 pF
DD
3.0 pF
DD/2
ni
C
˚
C
˚
3.
1
kV
4
NI
Operating Characteristics - VDD = 2V, Enable = 2V, Temperature = –40°C to 85°C
Parameter
Signal Voltage
Operating Characteristics
onditions
ove V @ I = 20mA
2.
below GND @ I = –20mA 300 500 mV
current all Channels floating 25 42 mA
V
DD
Enable pin (pin 14) current all Channels floating 3.5 5.5 mA
Input Capacitance* Signal voltage = V
Signal voltage = V
3.5 pF
DD
3.2 pF
DD/2
ESD protection MIL-STD-883, method 3015* 4 kV
Response Time 400 ps
*These parameters are guaranteed by design and characterization.
Operating Characteristics - VDD = 2.5V, Enable = 2.5V, Temperature = 27°C
Parameter
Signal Voltage
Operating Characteristics
onditions
ove V @ I = 30mA 47
2.
below GND @ I = –30mA 375 mV
current all Channels floating 50 mA
V
DD
Enable pin current all Channels floating 6 mA
NI
NI
©2001 California Micro Devices Corp. All rights reserved. EZterm is a trademark of California Micro Devices
215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
2
3/8/2001
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50
45
40
35
30
25
20
Current (mA)
15
10
5
0
0 100 200 300 400 500 600
VDD = 3.3V
VDD = 2.0V
PACNLT101
Voltage above V
Figure 1. DC I-V Curves for VDD = 2V and VDD = 3.3V
Application Information
Figure 2 shows one method of configuring the printed circuit board such that all 16 terminated signals are easily accessible. The decoupling capacitor should be a high-frequency type, 0.1µF or larger, and placed as close to the IC as possible. This will minimize
GND GND
16
Terminated
Signals
GND
(mV)
DD
the positive overshoot voltage and also reduce EMI emissions. It should be noted that for optimum performance the PACNLT101 termination should be located as physically close to the receiving IC input as is possible.
V
1
2
3
4
520
619
PACNLT101
718
817
916
10 15
11 14
12 13
24
23
22
21
GND
via
0.1µF
DD
Figure 2. Printed Circuit Board with Accessible Configuration for 16 Terminated Signals
©2001 California Micro Devices Corp. All rights reserved. EZterm is a trademark of California Micro Devices
215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
3/8/2001
3
Page 4
V
CC
Non-Linear
Driver 7SZ04
Transmission
Line
Clamp Termination
Receiver 74AC244
GND
Figure 3. Example Circuit: Single-Driver/Single Receiver
PACNLT101
Tek 136 Acqs
5GS/s
1V
Ch1
Figure 4. 74AC244 Termination Only
Tek 44 Acqs
5GS/s
: 2.50V
@: 0V
C1 Rise
1.14ns
C1 Fall 1ns
C1 Max
3.30V
C1 Min –1.20V
1.24VM 10ns
: 2.50V
@: 0V
C1 Rise
1.18ns
1V
Figure 5. With PACNLT101 Termination
©2001 California Micro Devices Corp. All rights reserved. EZterm is a trademark of California Micro Devices
215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
4
Ch1
C1 Fall 1ns
C1 Max
2.82V
C1 Min –500mV
1.24 VM 10ns
3/8/2001
Page 5
Enable pin
PACNLT101
In normal use the Enable pin is connected to VDD.
If the Enable pin is set to 0V or disconnected (high impedance), then the PACNLT101 will be disabled. The supply current will drop to almost zero and the clamping performance will be worsened.
The Enable pin can also be used to vary the supply current and clamping voltage. As the current into the Enable pin is increased the supply current will increase and the clamping voltage will be reduced. The minimum clamping voltage will occur when the Enable pin voltage equals the supply voltage. (The Enable pin voltage
PACNLT101
Enable
Figure 6. Resistor In Series with the Enable Pin
100
90
80
70
60
50
(mA)
40
DD
I
30
20
10
0
0 100 220 470 1000 2200
Value of External Resistor R1 ()
cannot exceed the supply voltage.)
Users who cannot tolerate the supply current quoted in the Operating Characteristics can connect a resistor in series with the Enable pin to reduce the supply current, at the cost of increasing the clamping voltage. See Figure 6.
The controller IC sets the powerdown pin to 0V to powerdown the PACNLT101, and sets the powerdown pin to V
to power up the PACNLT101. The system
DD
designer can vary the value of R1 to optimize the trade­off between power consumption and clamping voltage. See Figure 7, 8, 9, and 10.
R1
Controller
Powerdown
800
750
700
650
for 50mA (mV)
DD
600
Clamping Voltage
550
above V
500
0 100 220 470 1000 2200
Value of External Resistor R1 ()
Figure 7. IDD vs R1 @ VDD = 3.3V
30
25
20
15
(mA)
DD
I
10
5
0
0 100 220 470 1000 2200 4700 10000 100000
Value of External Resistor R1 ()
Figure 9. I
©2001 California Micro Devices Corp. All rights reserved. EZterm is a trademark of California Micro Devices
215 Topaz Street, Milpitas, California 95035  Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
3/8/2001
vs R1 @ VDD = 2V Figure 10. Clamping Voltage vs R1 @ VDD = 2V
DD
Figure 8. Clamping Voltage vs R1 @ VDD = 3.3V
650
600
550
500
for 20mA (mV)
450
DD
400
Clamping Voltage
above V
350
300
0 100 220 470 1000 2200 4700 10000 100000
Value of External Resistor R1 ()
5
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