• 16 channel, dual rail clamping action in
a single package
• Provides bus termination independent of line
impedance or loading conditions
• Uses CAMD’s patented EZterm™ technology
• 24-pin QSOP package saves board space and
eases layout in space critical areas.
• One IC replaces and outperforms up to 32 discrete
components.
• Enable pin included
Product Description
CAMD’s non-linear termination IC is specifically designed to minimize overshoot/undershoot disturbances
caused by impedance mismatch reflections and noise on
high-speed transmission lines.
Reflections on high-speed data lines lead to voltage
overshoot and undershoot disturbances, which may
result in data loss or improper system operation. Resistive terminations, when used to terminate these highspeed data lines, increase power consumption and
degrade output levels, resulting in reduced noise immunity. Clamping-type termination is the best overall
solution for applications in which these may be considerations.
This highly integrated non-linear termination IC provides
very effective termination performance for high-speed
data lines under variable loading conditions. The device
supports up to 16 terminated lines per package – each
of which are clamped to both ground and power supply
rail. A typical application may use 4 devices to replace
(and outperform) 64 conventional Schottky diode pairs;
thus providing significant reductions in component and
assembly costs, improvements in manufacturing efficiency and reliability, and savings in allocated board area
for space-critical designs.
Figure 1. DC I-V Curves for VDD = 2V and VDD = 3.3V
Application Information
Figure 2 shows one method of configuring the printed
circuit board such that all 16 terminated signals are
easily accessible. The decoupling capacitor should be a
high-frequency type, 0.1µF or larger, and placed as close
to the IC as possible. This will minimize
GNDGND
16
Terminated
Signals
GND
(mV)
DD
the positive overshoot voltage and also reduce
EMI emissions. It should be noted that for optimum
performance the PACNLT101 termination should be
located as physically close to the receiving IC input as is
possible.
V
1
2
3
4
520
619
PACNLT101
718
817
916
1015
1114
1213
24
23
22
21
GND
via
0.1µF
DD
Figure 2. Printed Circuit Board with Accessible Configuration for 16 Terminated Signals
If the Enable pin is set to 0V or disconnected (high
impedance), then the PACNLT101 will be disabled. The
supply current will drop to almost zero and the clamping
performance will be worsened.
The Enable pin can also be used to vary the supply
current and clamping voltage. As the current into the
Enable pin is increased the supply current will increase
and the clamping voltage will be reduced. The minimum
clamping voltage will occur when the Enable pin voltage
equals the supply voltage. (The Enable pin voltage
PACNLT101
Enable
Figure 6. Resistor In Series with the Enable Pin
100
90
80
70
60
50
(mA)
40
DD
I
30
20
10
0
010022047010002200
Value of External Resistor R1 (Ω)
cannot exceed the supply voltage.)
Users who cannot tolerate the supply current quoted in
the Operating Characteristics can connect a resistor in
series with the Enable pin to reduce the supply current,
at the cost of increasing the clamping voltage. See
Figure 6.
The controller IC sets the powerdown pin to 0V to
powerdown the PACNLT101, and sets the powerdown
pin to V
to power up the PACNLT101. The system
DD
designer can vary the value of R1 to optimize the tradeoff between power consumption and clamping voltage.
See Figure 7, 8, 9, and 10.