Datasheet P93U422-35DM, P93U422-35SC, P93U422-35PC, P93U422-35LMB, P93U422-35LM Datasheet (NCE RFORM)

P93U422
HIGH SPEED 256 x 4
STATIC CMOS RAM

FEATURES

P93U422

Universal 256 x 4 Static RAM

One part, the 93U422, replaces the following
bipolar and CMOS parts:
– 93422A
– 93422
– 93L422A
– 93L422

Fast Access Time
– 35 ns (Commercial)
– 35 ns (Military)

Standard 400 mil DIP and Chip carrier packages

DESCRIPTION

The P93U422 is a 1,024-bit high-speed Static RAM with
a 256 x 4 organization. The P93U422 is a universal
device designed to replace the entire 93 and 93L 256 x 4
static RAM families. The memory requires no clocks or
refreshing and has equal access and cycle times. Inputs
and outputs are fully TTL compatible. Operation is from a
single 5 Volt supply. Easy memory expansion is provided
by an active LOW chip select one (CS1) and active HIGH

CMOS for Low Power
– 440 mW (Commercial)
– 495 mW (Military)

5V Power Supply ±10% for both commercial
and military temperature ranges

Separate I/O

Fully static operation with equal access and
cycle times

Resistant to single event upset and latchup due
to advanced process and design improvements

chip select two (CS2) as well as 3-state outputs.
In addition to high performance, the device features

latch-up protection, single event and upset protection.
The P93U422 is offered in several packages: 22-pin 400
mil DIP (plastic and ceramic), 24-pin 300 mil SOIC, 24­pin LCC and 24-pin CERPACK. Devices are offered in
both commercial and military temperature ranges.

FUNCTIONAL BLOCK DIAGRAM

CS

2

CS

1

WE
D
D
D
D

A
A
A
A
A

A
A
A

0
1

2
3

0
1

2
3
4

5
6
7

CONTROL

DATA INPUT

ROW

DECODER

COLUMN

DECODER

32 X 32
ARRAY

SENSE AMPS

OE

O
O
O
O

0
1
2

3

PIN CONFIGURATIONS

1

A
A
A
A
A
A
A

GND

D
O
D

3
2
1
0
5
6
7

0
0
1

2
3
4
5
6
7
8
9
10
11
12

SOIC (S4)

TOP VIEW

24
23

22
21

20
19
18
17
16
15
14
13

7

V
A

WE
CS
OE

CS
O
D
O
D
O

NCNC

CC
4

3
3
2
2
1

A
A
A
A

1

A
A

2

A

GND

D
O
D

1

3

2

2

3

1

4

0

5

5

6

6

7

7

8
9

0

10

0

11

1

DIP (P3-1, D3-1)

TOP VIEW

22

V

CC

INDEX

GND

A

0

A

5

NC

A

6

A

7

A

4
5
6
7
8
9

D0D1D2O

21

A

4

20

WE

19

CS

1

18

OE

17

CS

2

16

O

3

15

D

3

14

O

2

13

D

2

12

O

1

V

WE

1A2A3A4

312 242322

CC

151413121110

O

0

O

1

LCC (L4)

TOP VIEW

Means Quality, Service and Speed

CS

21

1

OE

20

CS

19

2

NC

18

O

17

3

D

16

3

2

1Q97

P93U422

MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

V

CC

Power Supply Pin with –0.5 to +7 V
Respect to GND

Terminal Voltage with –0.5 to

V

TERM

Respect to GND VCC +0.5 V
(up to 7.0V)

T

A

Operating Temperature –55 to +125 °C

RECOMMENDED OPERATING CONDITIONS

(2)

Grade

Commercial
Military

Ambient Temp

0˚C to 70˚C

–55˚C to 125˚C

Gnd

0V
0V

Vcc

5.0V ±10%

5.0V ±10%

DC ELECTRICAL CHARACTERISTICS

Over recommended operating temperature and supply voltage

Symbol

V

OH

V

OL

V

IH

V

IL

I

IL

I

IH

I

SC

I

CC

V

CL

I

CEX

Parameter

Output High Voltage
Output Low Voltage
Input High Level
Input Low Level
Input Low Current
Input High Current
Output Short Circuit Current

Power Supply Current

Input Clamp Voltage

Output Leakage Current

VCC = Min., VIN = VIH or VIL, IOH = –5.2 mA

VCC = Min., VIN = VIH or VIL, IOL = 8.0 mA

VIN = 0.40 V
VCC = Max, VIN = 4.5V

(3)

V

= Max., V

CC

All Inputs = GND
VCC = Max.

IIN = –10mA
V

= 2.4V, VCC = Max.

OUT

V

OUT

Test Conditions

= 0.0V

OUT

= 0.5V, VCC = Max.

Symbol Parameter Value Unit

T

BIAS

Temperature Under –55 to +125 °C
Bias

T

STG

I

OUT

CAPACITANCES

Storage Temperature –65 to +150 °C
DC Output Current 20 mA

(4)

(VCC = 5.0V, TA = 25°C, f = 1.0MHz)

Symbol Parameter Conditions Typ. Unit

C

IN

C

OUT

(2)

Input Capacitance VIN = 0V 5 pF

Output Capacitance V

= 0V 7 pF

OUT

P93U422

Min.

Max.

Unit

2.4

0.45

2.1

0.8

–300

40

TA = 125˚C
TA = 75˚C

TA = 0˚C
TA = –55˚C

–70

70
70
80
90

mA

mA

–1.5

50

–50

V
V
V
V

µA
µA

V

µA

Notes:

1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability

2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.

3. For test purposes, not more than one output at a time should be shorted.
Short circuit test duration should not exceed 30 seconds.

4. This parameter is sampled and not 100% tested.

8

FUNCTIONAL DESCRIPTION

P93U422

An active LOW write enable (WE) controls the writing/
reading operation of the memory. When chip select one
(CS1) and write enable (WE) are LOW and chip select
two (CS2) is HIGH, the information on data inputs (D
through D3) is written into the addressed memory word
and preconditions the output circuitry so that true data is
present at the outputs when the write cycle is complete.
This preconditioning operation insures minimum write

TRUTH TABLE

CSCS

WEWE

Mode CS

CS

CSCS

2

1

OEOE

WE

OE Output

WEWE

OEOE

Standby L X X X High Z
Standby X H X X High Z
D

Disabled H L X H High Z

OUT

Read H L H L D

OUT

Write H L L X High Z

SWITCHING CHARACTERISTICS (5,6)

Over Operating Range (Commercial and Military)

Parameters

(7)

t

PLH(A)

(7)

t

PLH(A)

t

(CS1, CS2)

PZH

t

(CS1, CS2)

PZL

(WE)

(WE)

(OE)

(OE)

(8)

(8)

(8)

(8)

t
t

t
t

PZH
PZL

PZH
PZL

tS(A)
th(A)

tS(DI)
th(DI)

tS (CS1, CS2)
th (CS1, CS2)

tpw(WE)

t

(CS1, CS2)

PHZ

t

(CS1, CS2)

PLZ

(WE)

(WE)

(OE)

(OE)

(8)
(8)

(8)

(8)

t
t

t
t

PHZ
PLZ

PHZ

PLZ

Delay from Address to Output (Address Access Time) (See Fig. 2)

(8)

Delay from Chip Select to Active Output and Correct Data (See Fig. 2)

(8)

Delay from Write Enable to Active Output and Correct Data (Write Recovery)
(See Fig. 1)

Delay from Output Enable to Active Output and Correct Data (See Fig. 2)
Setup Time Address (Prior to Initiation of Write) (See Fig. 1)

Hold Time Address (After Termination of Write) (See Fig. 1)
Setup Time Data Input (Prior to Initiation of Write) (See Fig. 1)

Hold Time Data Input (After Termination of Write) (See Fig. 1)
Setup Time Chip Select (Prior to Initiation of Write) (See Fig. 1)

Hold Time Chip Select (After Termination of Write) (See Fig. 1)
Minimum Write Enable Pulse Width (to Insure Write) (See Fig. 1)

(8)

Delay from Chip Select to Inactive Output (HIGH Z) (See Fig. 2)

(8)

Delay from Write Enable to Inactive Output (HIGH Z) (See Fig. 1)

Delay from Output Enable to Inactive Output (HIGH Z) (See Fig. 2)

Description

recovery times by eliminating the “write recovery glitch.”
Reading is performed with chip selct one (CS1) LOW, chip
select two (CS2) HIGH, write enable (WE) HIGH and
output enable (OE) LOW. The information stored in the

0

addressed word is read out on the noninverting outputs
(O0 through O3). The outputs of the memory go to an
inactive high impedance state whenever chip select one
(CS1) is HIGH, or during the write operation when write
enable (WE) is LOW.

Notes: H = HIGH

L = Low
X = Don't Care

HIGH Z = Implies outputs are disabled or off. This

condition is defined as high impedance state
for the P93U422.

P93U422

Min.

5
5
5
5
5

5

20

Max.

35

25

25

25

30

30

30

Unit

ns

ns

ns

ns
ns

ns
ns

ns
ns

ns
ns

ns

ns

ns

9

P93U422

Notes:

5) Test conditions assume signal transition times of 10 ns or less.

6) Extended temperature operation guaranteed with 400 linear feet per minute of air flow.

(A)

7) t

8) t
referenced to 1.5V. t

PLH

(WE), t

PZH

and t

output timing referenced to 1.5V.
t

(WE), t

PHZ

on the input to the VOH -500mV level on the output.
t

(WE), t

PLZ

on the input to the VOL +500mV level on the output.

(A)

are tested with S1 closed and CL = 15 pF with both input and output timing referenced to 1.5V

PHL

(CS1, CS2) and t

PZH

PZL

(CS1, CS2) and t

PHZ

(CS1, CS2) and t

PLZ

(WE), t

(OE) are measured with S1 open, CL = 15 pF and with both the input and output timing

PZH

(CS1, CS2) and t

PZL

(OE) are measured with S1 open, CL < 5pF and are measured between the 1.5V level

PHZ

(OE) are measured with S1 closed, CL < 5pF and are measured between the 1.5V level

PLZ

(OE) are measured with S1 closed, CL = 15pF and with both the input and

PZL

10

P93U422

CHIP
SELECT

11

P93U422

ORDERING INFORMATION

P93U422 xxxx

Device Type Package Processing

Speed

C 0°C to +70°C
M –55°C to +125°C
MB MIL-STD-883, Class B

F CERPACK
D CERDIP (400 mil)
L Ceramic LCC (400 mil square)
P Plastic DIP (4 00 mil)
S Plastic SOIC (300 mil)

35 ns Commercial

35 ns Military

256 x 4 SRAM

SELECTION GUIDE

The P93U422 is available in the following temperature range, speed, and package options.

Temperature
Range

Package

Speed (ns)

35

Commercial
Temperature

Military
Temperature

Military Pro­cessed*

Plastic DIP
Plastic SOIC

CERDIP
LCC

CERDIP
LCC

-35PC

-35SC

-35DM

-35LM

-35DMB

-35LMB

*Military temperature range with MIL-STD-883, Class B processing.

12