Datasheet P87C750EFPN, P87C750EFAA, P87C750EBPN, P87C750EBDDB, P87C750EBAA Datasheet (Philips)
...Page 1
INTEGRATED CIRCUITS
83C750/87C750
80C51 8-bit microcontroller family
1K/64 OTP ROM, low pin count
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Page 2
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
1K/64 OTP/ROM, low pin count
DESCRIPTION
The Philips 8XC750 offers the advantages of the 80C51 architecture
in a small package and at low cost.
The 8XC750 Microcontroller is fabricated with Philips high-density
CMOS technology. Philips epitaxial substrate minimizes CMOS
latch-up sensitivity.
The 87C750 contains a 1k × 8 EPROM, a 64 × 8 RAM, 19 I/O lines,
a 16-bit auto-reload counter/timer, a five-source, fixed-priority level
interrupt structure and an on-chip oscillator.
FEA TURES
•80C51 based architecture
•Oscillator frequency range—up to 16MHz
•Small package sizes
– 24-pin DIP (300 mil “skinny DIP”)
– 24-pin Shrink Small Outline Package
– 28-pin PLCC
•87C750 available in one-time programmable plastic packages
•Low power consumption:
– Normal operation: less than 11mA @ 5V, 12MHz
– Idle mode
– Power-down mode
•1k × 8 EPROM (87C750)
•64 × 8 RAM
•16-bit auto reloadable counter/timer
•Boolean processor
•CMOS and TTL compatible
•Well suited for logic replacement, consumer and industrial
applications
•LED drive outputs
PIN CONFIGURATIONS
P3.4/A4
1
P3.3/A3
2
PP
RST
V
X2
X1
SS
5
11
SS
3
4
5
6
7
8
9
10
11
12
4126
12 18
PP
P3.2/A2/A10
P3.1/A1/A9
P3.0/A0/A8
P0.2/V
P0.1/OE–PGM
P0.0/ASEL
Pin Function
1 P3.4/A4
2 P3.3/A3
3 P3.2/A2/A10
4 P3.1/A1/A9
5 NC*
6 P3.0/A0/A8
7 P0.2/V
8 P0.1/OE-PGM
9 P0.0/ASEL
10 NC*
11 RST
12 X2
13 X1
* NO INTERNAL CONNECTION
14 V
83C750/87C750
24
V
CC
P3.5/A5
23
22
P3.6/A6
21
PLASTIC
DUAL
IN-LINE
AND
SHRINK
SMALL
OUTLINE
PACKAGE
PLASTIC
LEADED
CHIP
CARRIER
P3.7/A7
20
P1.7/T0/D7
P1.6/INT1/D6
19
18
P1.5/INT0/D5
17
P1.4/D4
16
P1.3/D3
15
P1.2/D2
14
P1.1/D1
13
P1.0/D0
25
19
Pin Function
15 P1.0/D0
16 P1.1/D1
17 P1.2/D2
18 P1.3/D3
19 P1.4/D4
20 P1.5/INT0
21 NC*
22 NC*
23 P1.6/INT1/D6
24 P1.7/T0/D7
25 P3.7/A7
26 P3.6/A6
27 P3.5/A5
28 V
CC
/D5
SU00295A
ORDERING INFORMATION
ROM EPROM
1
TEMPERATURE RANGE °C AND PACKAGE FREQUENCY
P83C750EBP N P87C750EBP N OTP 0 to +70, Plastic Dual In-line Package 3.5 to 16MHz SOT222-1
P83C750EFP N P87C750EFP N OTP –40 to +85, Plastic Dual In-line Package 3.5 to 16MHz SOT222-1
P83C750EBA A P87C750EBA A OTP 0 to +70, Plastic Lead Chip Carrier 3.5 to 16MHz SOT261-3
P83C750EFA A P87C750EFA A OTP –40 to +85, Plastic Lead Chip Carrier 3.5 to 16MHz SOT261-3
P83C750EBD DB P87C750EBD DB OTP 0 to +70, Shrink Small Outline Package 3.5 to 16MHz SOT340-1
NOTE:
1. OTP = One Time Programmable EPROM.
1998 May 01 853–1683 19331
2
DRAWING
NUMBER
Page 3
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
1K/64 OTP/ROM, low pin count
BLOCK DIAGRAM
V
CC
V
SS
RAM ADDR
REGISTER
B
REGISTER
RAM
ACC
TMP2
PSW
ALU
P0.0–P0.2
PORT 0
DRIVERS
PORT 0
LATCH
TMP1
PCON TCON
TH0 TL0
RTH RTL
INTERRUPT AND
TIMER BLOCKS
STACK
POINTER
IE
EPROM
83C750/87C750
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCRE-
MENTER
RST
TIMING
AND
CONTROL
OSCILLATOR
X1
INSTRUCTION
PD
REGISTER
X2
PORT 1
LATCH
PORT 1
DRIVERS
P1.0–P1.7
PORT 3
LATCH
PORT 3
DRIVERS
P3.0–P3.7
PROGRAM
COUNTER
DPTR
SU00312
1998 May 01
3
Page 4
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
83C750/87C750
1K/64 OTP/ROM, low pin count
PIN DESCRIPTIONS
PIN NO.
MNEMONIC DIP/
V
SS
V
CC
P0.0-P0.2 8-6 9-7 I/O Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,
P1.0-P1.7 13-20 15-20,
P3.0-P3.7 5-1,
RST 9 11 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
X1 11 13 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X2 10 12 O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
1. When P0.2 is at or close to 0 Volt, it may affect the internal ROM operation. We recommend that P0.2 be tied to V
2kΩ).
SSOP
23-21
LCC TYPE NAME AND FUNCTION
12 14 I Circuit Ground Potential
24 28 I Supply voltage during normal, idle, and power-down operation.
and in that state can be used as high-impedance inputs. These pins are driven low if the port register
bit is written with a 0. The state of the pin can always be read from the port register by the program.
P0.0, P0.1, and P0.2 are open drain bidirectional I/O pins with the electrical characteristics listed in
the tables that follow. While these differ from “standard TTL” characteristics, they are close enough
for the pins to still be used as general-purpose I/O. Port 0 also provides alternate functions for
programming the EPROM memory as follows:
6 7 N/A VPP (P0.2) – Programming voltage input. (See Note 1.)
7 8 I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
8 9 I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
23, 24
18 20 I INT0 (P1.5): External interrupt.
19 23 I INT1 (P1.6): External interrupt.
20 24 I T0 (P1.7): Timer 0 external input.
6, 4-1,
27-25
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins
that are externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I
mode and accepts as inputs the value to program into the selected address during the program
mode. Port 1 also serves the special function features of the 80C51 family as listed below:
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins
that are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I
be programmed (or verified). The 10-bit address is multiplexed into this port as specified by
P0.0/ASEL.
An internal diffused resistor to V
. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places
V
CC
the device in the programming state allowing programming address, data and V
programming or verification purposes. The RESET serial sequence must be synchronized with the
X1 input.
X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
). Port 3 also functions as the address input for the EPROM memory location to
IL
). Port 1 serves to output the addressed EPROM contents in the verify
IL
permits a power-on RESET using only an external capacitor to
SS
to be applied for
PP
via a small pull-up (e.g.,
CC
OSCILLA T OR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
1998 May 01
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-up, the voltage on
V
and RST must come up at the same time for a proper start-up.
CC
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
4
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Philips Semiconductors Product specification
80C51 8-bit microcontroller family
1K/64 OTP/ROM, low pin count
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. the control
bits for the reduced power modes are in the special function register
PCON.
Table 1. External Pin Status During Idle and
Power-Down Modes
MODE Port 0 Port 1 Port 2
Idle Data Data Data
Power-down Data Data Data
DIFFERENCES BETWEEN THE 8XC750 AND THE 80C51
Program Memory
On the 8XC750, program memory is 1024 bytes long and is not
externally expandable, so the 80C51 instructions MOVX, LJMP, and
LCALL are not implemented. The only fixed locations in program
memory are the addresses at which execution is taken up in
response to reset and interrupts, which are as follows:
Event Address
Reset 000
External INT0
Counter/timer 0 00B
External INT1
Counter/Timer Subsystem
Timer/Counter
The 8XC750 has one timers: a 16-bit timer/counter. The 16-bit
timer/counter’s operation is similar to mode 2 operation on the
80C51, but is extended to 16 bits. The timer/counter is clocked by
either 1/12 the oscillator frequency or by transitions on the T0 pin.
The C/T pin in special function register TCON selects between
these two modes. When the TCON TR bit is set, the timer/counter is
enabled. Register pair TH and TL are incremented by the clock
source. When the register pair overflows, the register pair is
reloaded with the values in registers RTH and RTL. The value in the
reload registers is left unchanged. See the 83C750 counter/timer
block diagram in Figure 1. The TF bit in special function register
Program Memory
003
013
83C750/87C750
TCON is set on counter overflow and, if the interrupt is enabled, will
generate an interrupt.
TCON Register
MSB LSB
GATE
GATE 1 – Timer/counter is enabled only when INT0 pin is high,
C/T 1 – Counter/timer operation from T0 pin.
TF 1 – Set on overflow of TH.
TR 1 – Timer/counter enabled.
IE0 1 – Edge detected in INT0
IT0 1 – INT0
IE1 1 – Edge detected on INT1
IT1 1 – INT1
These flags are functionally identical to the corresponding 80C51
flags, except that there is only one timer on the 83C750 and the
flags are therefore combined into one register.
Note that the positions of the IE0/IT0 and IE1/IT1 bits are
transposed from the positions used in the standard 80C51 TCON
register.
Interrupt Subsystem – Fixed Priority
The IP register and the 2-level interrupt system of the 80C51 are
eliminated. Simultaneous interrupt conditions are resolved by a
single-level, fixed priority as follows:
Highest priority: Pin INT0
Special Function Register Addresses
Special function registers for the 8XC750 are identical to those of
the 80C51, except for the changes listed below:
80C51 special function registers not present in the 8XC750 are
TMOD (89), P2 (A0) and IP (B8). The 80C51 registers TH1 and TL1
are replaced with the 87C750 registers RTH and RTL respectively
(refer to Table 2).
C/T TF TR IE0 IT0 IE1 IT1
and TR is 1.
0 – Timer/counter is enabled when TR is 1.
0 – Timer operation from internal clock.
0 – Cleared when processor vectors to interrupt routine
and by reset.
0 – Timer/counter disabled.
.
is edge triggered.
0 – INT0
0 – INT1
is level sensitive.
.
is edge triggered.
is level sensitive.
Counter/timer flag 0
Pin INT1
1998 May 01
INT0
OSC
T0 Pin
Gate
Pin
÷ 12
C/T = 0
C/T = 1
TR
Figure 1. 83C751 Counter/Timer Block Diagram
5
TL TH TF
Reload
RTL RTH
Int.
SU00300
Page 6
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
83C750/87C750
1K/64 OTP/ROM, low pin count
Table 2. 87C750 Special Function Registers
SYMBOL DESCRIPTION
ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H
B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H
DPTR:
DPH
DPL
IE*# Interrupt enable A8H EA – – – – EX1 ET0 EX0 00H
P0*# Port 0 80H – – – – – – – – xxxxx111B
P1* Port 1 90H T0 INT1 INT0 – – – – – FFH
P3* Port 3 B0H B7 B6 B5 B4 B3 B2 B1 B0 FFH
Data pointer
(2 bytes)
High byte
Low byte
DIRECT
ADDRESS
83H
82H
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB LSB
AF AE AD AC AB AA A9 A8
82 81 80
97 96 95 94 93 92 91 90
RESET
VALUE
00H
00H
PCON# Power control 87H – – – – – – PD IDL xxxxxx00B
D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program status word D0H CY AC F0 RS1 RS0 OV – P 00H
SP Stack pointer 81H 07H
8F 8E 8D 8C 8B 8A 89 88
TCON*# Timer/counter control 88H GATE C/T TF TR IE0 IT0 IE1 IT1 00H
TL# Timer low byte 8AH 00H
TH# Timer high byte 8CH 00H
RTL# Timer low reload 8BH 00H
RTH# Timer high reload 8DH 00H
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
ABSOLUTE MAXIMUM RATINGS
Storage temperature range –65 to +150 °C
Voltage from V
Voltage from any pin to V
Power dissipation 1.0 W
Voltage on VPP pin to V
Maximum IOL per I/O pin 10 mA
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
CC
to V
SS
(except VPP) –0.5 to VCC + 0.5 V
SS
SS
1, 2
PARAMETER
RATING UNIT
–0.5 to +6.5 V
0 to +13.0 V
1998 May 01
6
Page 7
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
83C750/87C750
1K/64 OTP/ROM, low pin count
DC ELECTRICAL CHARACTERISTICS
T
= 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V
amb
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
V
IL
V
IH
V
IH1
V
OL
V
OL1
V
OH
C Capacitance 10 pF
I
IL
I
TL
I
LI
R
RST
C
IO
I
PD
V
PP
I
PP
I
CC
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
noted.
2. Under steady state (non-transient) conditions, I
If I
OL
test conditions.
3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
4. Power-down I
5. Active I
RST = port 0 = V
6. Idle I
port 0 = V
Input low voltage –0.5 0.2VDD–0.1 V
Input high voltage, except X1, RST 0.2VCC+0.9 VCC+0.5 V
Input high voltage, X1, RST 0.7V
Output low voltage, ports 1 and 3 IOL = 1.6mA
Output low voltage, port 0 IOL = 3.2mA
Output high voltage, ports 1 and 3 IOH = –60µA 2.4 V
Logical 0 input current, ports 1 and 3 VIN = 0.45V –50 µA
Logical 1 to 0 transition current, ports 1 and 3
Input leakage current, port 0 0.45 < VIN < V
Internal pull-down resistor 25 175 kΩ
Pin capacitance
Power-down current
4
VPP program voltage
Program current VPP = 13.0V 50 mA
Supply current (see Figure 3)
Maximum I
Maximum I
Maximum total I
exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
CC
is measured with all output pins disconnected; X1 driven with t
CC
is measured with all output pins disconnected; X1 driven with t
CC
; RST = VSS.
CC
per port pin: 10mA (NOTE: This is 85°C spec.)
OL
per 8-bit port: 26mA
OL
for all outputs: 67mA
OL
is approximately 2V .
IN
is measured with all output pins disconnected; port 0 = VCC; X2, X1 n.c.; RST = VSS.
. ICC will be slightly higher if a crystal oscillator is used.
CC
5, 6
must be externally limited as follows:
OL
1
TEST LIMITS
CC
2
2
IOH = –25µA 0.75V
IOH = –10µA 0.9V
3
VIN = 2V (0 to +70°C)
V
= 2V (–40 to +85°C)
IN
CC
CC
CC
Test freq = 1MHz,
T
= 25°C
amb
VCC+0.5 V
0.45 V
0.45 V
–650
–750
±10 µA
10 pF
VCC = 2 to VCC max 50 µA
VSS = 0V
V
CC
= 21°C to 27°C
T
amb
CLCH
, t
CLCH
CHCL
= 5V±10%
, t
= 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;
CHCL
= 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;
12.5 13.0 V
unless otherwise
SS
V
V
µA
µA
AC ELECTRICAL CHARACTERISTICS
T
= 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V
amb
SYMBOL PARAMETER MIN MAX MIN MAX UNIT
1/t
CLCL
Oscillator frequency: 3.5 16 3.5 40 MHz
External Clock (Figure 2)
t
CHCX
t
CLCX
t
CLCH
t
CHCL
High time 20 10 ns
Low time 20 10 ns
Rise time 20 20 ns
Fall time 20 20 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
noted.
2. Load capacitance for ports = 80pF.
1998 May 01
1, 2
VARIABLE CLOCK
unless otherwise
SS
7
Page 8
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
1K/64 OTP/ROM, low pin count
EXPLANATION OF THE AC SYMBOLS
In defining the clock waveform, care must be taken not to exceed
the MIN or MAX limits of the AC electrical characteristics table.
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
C – Clock
D – Input data
VCC –0.5
0.45V
0.2 V
0.2 V
+ 0.9
CC
– 0.1
CC
Figure 2. External Clock Drive
H – Logic level high
L – Logic level low
Q – Output data
T – Time
V – Valid
X – No longer a valid logic level
Z – Float
t
CLCX
t
CHCX
t
CLCL
t
CLCH
t
CHCL
83C750/87C750
SU00297
(mA)
CC
I
60
CC
CC
CC
CC
6
5
50
40
5
6
(mA)
30
CC
I
20
10
0
16 20 24 28 32 36 40
MAX ACTIVE I
TYP ACTIVE I
MAX IDLE I
TYP IDLE I
Frequency (MHz)
22
20
18
16
14
12
10
8
6
4
2
4 8 12 16
MAX ACTIVE I
TYP ACTIVE I
MAX IDLE I
TYP IDLE I
Frequency (MHz)
CC
CC
6
CC
6
CC
SU00313
5
5
Figure 3. ICC vs. Frequency
Maximum I
values taken at VCC max and worst case temperature.
CC
Typical I
values taken at VCC = 5.0V and 25°C.
CC
Notes 5 and 6 refer to DC Electrical Characteristics.
ROM CODE SUBMISSION
When submitting ROM code for the 80C750, the following must be specified:
1. 1k byte user ROM data
ADDRESS CONTENT BIT(S) COMMENT
0000H to 03FFH DATA 7:0 User ROM Data
1998 May 01
8
Page 9
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
1K/64 OTP/ROM, low pin count
87C750 PROGRAMMING CONSIDERA TIONS EPROM Characteristics
The 87C750 is programmed by using a modified Quick-Pulse
Programming algorithm similar to that used for devices such as the
87C451 and 87C51. It differs from these devices in that a serial data
stream is used to place the 87C750 in the programming mode.
Figure 4 shows a block diagram of the programming configuration
for the 87C750. Port pin P0.2 is used as the programming voltage
supply input (V
(PGM/) signal. This pin is used for the 25 programming pulses.
Port 3 is used as the address input for the byte to be programmed
and accepts both the high and low components of the eleven bit
address. Multiplexing of these address components is performed
using the ASEL input. The user should drive the ASEL input high
and then drive port 3 with the high order bits of the address. ASEL
should remain high for at least 13 clock cycles. ASEL may then be
driven low which latches the high order bits of the address internally.
the high address should remain on port 3 for at least two clock
cycles after ASEL is driven low. Port 3 may then be driven with the
low byte of the address. The low address will be internally stable 13
clock cycles later. The address will remain stable provided that the
low byte placed on port 3 is held stable and ASEL is kept low. Note:
ASEL needs to be pulsed high only to change the high byte of the
address.
Port 1 is used as a bidirectional data bus during programming and
verify operations. During programming mode, it accepts the byte to
be programmed. During verify mode, it provides the contents of the
EPROM location specified by the address which has been supplied
to Port 3.
The XTAL1 pin is the oscillator input and receives the master system
clock. This clock should be between 1.2 and 6MHz.
The RESET pin is used to accept the serial data stream that places
the 87C750 into various programming modes. This pattern consists
of a 10-bit code with the LSB sent first. Each bit is synchronized to
the clock input, X1.
Programming Operation
Figures 5 and 6 show the timing diagrams for the program/verify
cycle. RESET should initially be held high for at least two machine
cycles. P0.1 (PGM/) and P0.2 (VPP) will be at VOH as a result of the
RESET operation. At this point, these pins function as normal
quasi-bidirectional I/O ports and the programming equipment may
pull these lines low. However, prior to sending the 10-bit code on the
RESET pin, the programming equipment should drive these pins
high (V
IH
for the data stream which places the 87C750 in the programming
mode. Data bits are sampled during the clock high time and thus
should only change during the time that the clock is low. Following
transmission of the last data bit, the RESET pin should be held low.
Next the address information for the location to be programmed is
placed on port 3 and ASEL is used to perform the address
multiplexing, as previously described. At this time, port 1 functions
as an output.
A high voltage V
(This sets Port 1 as an input port). The data to be programmed into
the EPROM array is then placed on Port 1. This is followed by a
series of programming pulses applied to the PGM/ pin (P0.1). These
pulses are created by driving P0.1 low and then high. This pulse is
signal). Port pin P0.1 is used as the program
PP
). The RESET pin may now be used as the serial data input
level is then applied to the VPP input (P0.2).
PP
83C750/87C750
repeated until a total of 25 programming pulses have occurred. At
the conclusion of the last pulse, the PGM/ signal should remain high.
The V
signal may now be driven to the VOH level, placing the
PP
87C750 in the verify mode. (Port 1 is now used as an output port).
After four machine cycles (48 clock periods), the contents of the
addressed location in the EPROM array will appear on Port 1.
The next programming cycle may now be initiated by placing the
address information at the inputs of the multiplexed buffers, driving
the V
pin to the VPP voltage level, providing the byte to be
PP
programmed to Port1 and issuing the 26 programming pulses on the
PGM/ pin, bringing V
byte.
Programming Modes
The 87C750 has four programming features incorporated within its
EPROM array. These include the USER EPROM for storage of the
application’s code, a 16-byte encryption key array and two security
bits. Programming and verification of these four elements are
selected by a combination of the serial data stream applied to the
RESET pin and the voltage levels applied to port pins P0.1 and
P0.2. The various combinations are shown in Table 3.
Encryption Key Table
The 87C750 includes a 16-byte EPROM array that is programmable
by the end user. The contents of this array can then be used to
encrypt the program memory contents during a program memory
verify operation. When a program memory verify operation is
performed, the contents of the program memory location is
XNOR’ed with one of the bytes in the 16-byte encryption table. The
resulting data pattern is then provided to port 1 as the verify data.
The encryption mechanism can be disable, in essence, by leaving
the bytes in the encryption table in their erased state (FFH) since
the XNOR product of a bit with a logical one will result in the original
bit. The encryption bytes are mapped with the code memory in
16-byte groups. the first byte in code memory will be encrypted with
the first byte in the encryption table; the second byte in code
memory will be encrypted with the second byte in the encryption
table and so forth up to and including the 16the byte. The encryption
repeats in 16-byte groups; the 17th byte in the code memory will be
encrypted with the first byte in the encryption table, and so forth.
Security Bits
Two security bits, security bit 1 and security bit 2, are provided to
limit access to the USER EPROM and encryption key arrays.
Security bit 1 is the program inhibit bit, and once programmed
performs the following functions:
1. Additional programming of the USER EPROM is inhibited.
2. Additional programming of the encryption key is inhibited.
3. Verification of the encryption key is inhibited.
4. Verification of the USER EPROM and the security bit levels may
still be performed.
(If the encryption key array is being used, this security bit should be
programmed by the user to prevent unauthorized parties from
reprogramming the encryption key to all logical zero bits. Such
programming would provide data during a verify cycle that is the
logical complement of the USER EPROM contents).
Security bit 2, the verify inhibit bit, prevents verification of both the
USER EPROM array and the encryption key arrays. The security bit
levels may still be verified.
back down to the VC level and verifying the
PP
1998 May 01
9
Page 10
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
1K/64 OTP/ROM, low pin count
Programming and Verifying Security Bits
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 3. When
programming either security bit, it is not necessary to provide
address or data information to the 87C750 on ports 1 and 3.
Table 3. Implementing Program/Verify Modes
OPERATION SERIAL CODE P0.1 (PGM/) P0.2 (VPP)
Program user EPROM 296H –
Verify user EPROM 296H V
Program key EPROM 292H –
Verify key EPROM 292H V
Program security bit 1 29AH –
Program security bit 2 298H –
Verify security bits 29AH V
NOTE:
1. Pulsed from V
to VIL and returned to VIH.
IH
EPROM PROGRAMMING AND VERIFICATION
T
= 21°C to +27°C, VCC = 5V ±10%, VSS = 0V
amb
SYMBOL
1/t
CLCL
t
AVGL
t
GHAX
t
DVGL
t
DVGL
t
GHDX
t
SHGL
t
GHSL
t
GLGH
t
AVQV
t
GHGL
t
SYNL
t
SYNH
t
MASEL
t
MAHLD
t
HASET
t
ADSTA
1
2
Oscillator/clock frequency 1.2 6 MHz
Address setup to P0.1 (PROG–) low 10µs + 24t
Address hold after P0.1 (PROG–) high 48t
Data setup to P0.1 (PROG–) low 38t
Data setup to P0.1 (PROG–) low 38t
Data hold after P0.1 (PROG–) high 36t
VPP setup to P0.1 (PROG–) low 10 µs
VPP hold after P0.1 (PROG–) 10 µs
P0.1 (PROG–) width 90 110 µs
VPP low (VCC) to data valid 48t
P0.1 (PROG–) high to P0.1 (PROG–) low 10 µs
P0.0 (sync pulse) low 4t
P0.0 (sync pulse) high 8t
ASEL high time 13t
Address hold time 2t
Address setup to ASEL 13t
Low address to valid data 48t
NOTES:
1. Address should be valid at least 24t
2. For a pure verify mode, i.e., no program mode in between, t
PARAMETER MIN MAX UNIT
before the rising edge of P0.2 (VPP).
CLCL
AVQV
Verification occurs in a similar manner using the RESET serial
stream shown in Table 3. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if not programmed. Likewise, P1.6
contains the security bit 2 data and is a logical one if programmed
and a logical zero if not programmed.
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
is 14t
CLCL
maximum.
83C750/87C750
1
IH
1
IH
1
1
IH
CLCL
CLCL
V
PP
V
IH
V
PP
V
IH
V
PP
V
PP
V
IH
1998 May 01
10
Page 11
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
1K/64 OTP/ROM, low pin count
A0–A9
ADDRESS STROBE
PROGRAMMING
PULSES
VOLTAGE
V
PP/VIH
SOURCE
CLK SOURCE
RESET
CONTROL
LOGIC
Figure 4. Programming Configuration
XTAL1
MIN 2 MACHINE
CYCLES
RESET
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9
87C750
P3.0–P3.7
P0.0/ASEL
P0.1
P0.2
XTAL1
RESET
TEN BIT SERIAL CODE
V
CC
V
SS
P1.0–P1.7
83C750/87C750
+5V
DATA BUS
SU00314
UNDEFINED
P0.2
UNDEFINED
P0.1
SU00302
Figure 5. Entry into Program/Verify Modes
12.75V
)
P0.2 (V
P0.1 (PGM
P0.0 (ASEL)
PORT 3
PORT 1 INVALID DATA VALID DATA DATA TO BE PROGRAMMED INVALID DATA VALID DATA
PP
5V
t
SHGL
25 PULSES
)
t
t
MASEL
t
HASET
HIGH ADDRESS LOW ADDRESS
t
HAHLD
t
ADSTA
GLGH
98µs MIN 10µs MIN
t
DVGLtGHDX
t
GHGL
5V
t
GHSL
t
AVQV
1998 May 01
VERIFY MODE PROGRAM MODE VERIFY MODE
SU00310
Figure 6. Program/Verify Cycle
11
Page 12
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
83C750/87C750
1K/64 OTP/ROM low pin count
DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1
1998 May 01
12
Page 13
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
83C750/87C750
1K/64 OTP/ROM low pin count
PLCC28: plastic leaded chip carrer; 28 leads; pedestal SOT261-3
1998 May 01
13
Page 14
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
83C750/87C750
1K/64 OTP/ROM low pin count
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
1998 May 01
14
Page 15
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
1K/64 OTP/ROM low pin count
83C750/87C750
NOTES
1998 May 01
15
Page 16
Philips Semiconductors Product specification
80C51 8-bit microcontroller family
1K/64 OTP/ROM low pin count
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
83C750/87C750
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Date of release: 05-98
Document order number: 9397 750 03844
1998 May 01
16
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