Datasheet P83C654FHA, P83C654FBB, P83C654IFB, P80C652FHP, P80C652FBP Datasheet (Philips)

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87C654

CMOS single-chip 8-bit microcontroller

Product specification 1996 Aug 16

INTEGRATED CIRCUITS

IC20 Data Handbook

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

2

1996 Aug 16 853–1689 17192

DESCRIPTION

The 87C654 Single-Chip 8-Bit Microcontroller
is manufactured in an advanced CMOS
process and is a derivative of the 80C51
microcontroller family. The 87C654 has the
same instruction set as the 80C51. Two
versions of the derivative exist:

83C654—16k bytes mask programmable

ROM
87C654—EPROM version
This device provides architectural

enhancements that make it applicable in a
variety of applications for general control
systems. The 87C654 contains a non-volatile
16k × 8 EPROM, a volatile 256 × 8 read/write
data memory, four 8-bit I/O ports, two 16-bit
timer/event counters (identical to the timers of
the 80C51), a multi-source, two-priority-level,
nested interrupt structure, an I

2

C interface,
UART and on-chip oscillator and timing
circuits. For systems that require extra
capability, the 87C654 can be expanded
using standard TTL compatible memories
and logic.

The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 16MHz crystal, 58% of the
instructions are executed in 0.75µs and 40%
in 1.5µs. Multiply and divide instructions
require 3µs.

FEATURES

•80C51 central processing unit

•16k × 8 EPROM expandable externally to

64k bytes

•256 × 8 RAM, expandable externally to

64k bytes

•Two standard 16-bit timer/counters

•Four 8-bit I/O ports

•I

2

C-bus serial I/O port with byte oriented

master and slave functions

•Full-duplex UART facilities

•Power control modes

– Idle mode
– Power-down mode

•Five package styles

•Extended temperature range

•OTP package available

•Two speed ranges

– 16MHz
– 20MHz

PIN CONFIGURATIONS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5

SCL/P1.6

RST
RxD/P3.0
TxD/P3.1

INT0

/P3.2

INT1

/P3.3
T0/P3.4
T1/P3.5

SDA/P1.7

WR/P3.6

RD

/P3.7

XTAL2
XTAL1

V

SS

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

EA/V

PP

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

V

CC

CERAMIC

AND

PLASTIC

DUAL

IN-LINE

PACKAGE

CERAMIC

AND PLASTIC

LEADED

CHIP

CARRIER

6 1 40

7

17

39

29

18 28

PLASTIC

QUAD

FLAT
PACK

44

34

1

11

33

23

12 22

SU00259

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

3

CERAMIC AND PLASTIC LEADED
CHIP CARRIER PIN FUNCTIONS

LCC

6 1 40

7

17

39

29

18 28

Pin Function

1 NC*
2 P1.0
3 P1.1
4 P1.2
5 P1.3
6 P1.4
7 P1.5
8 P1.6/SCL

9 P1.7/SDA
10 RST
11 P3.0/RxD
12 NC8
13 P3.1/TxD
14 P3.2/INT0
15 P3.3/INT1
16 P3.4/T0
17 P3.5/T1
18 P3.6/WR
19 P3.7/RD
20 XTAL2
21 XTAL1
22 V

SS

Pin Function

23 NC8
24 P2.0/A8
25 P2.1/A9
26 P2.2/A10
27 P2.3/A11
28 P2.4/A12
29 P2.5/A13
30 P2.6/A14
31 P2.7/A15
32 PSEN
33 ALE/PROG
34 NC8
35 EA

/V

PP

36 P0.7/AD7
37 P0.6/AD6
38 P0.5/AD5
39 P0.4/AD4
40 P0.3/AD3
41 P0.2/AD2
42 P0.1/AD1
43 P0.0/AD0
44 V

CC

SU00260

* DO NOT CONNECT

PLASTIC QUAD FLAT PACK
PIN FUNCTIONS

Pin Function

1 P1.5
2 P1.6/SCL
3 P1.7/SDA
4 RST
5 P3.0/RxD
6 NC*
7 P3.1/TxD
8 P3.2/INT0

9 P3.3/INT1
10 P3.4/T0
11 P3.5/T1
12 P3.6/WR
13 P3.7/RD
14 XTAL2
15 XTAL1
16 V

SS

17 NC*
18 P2.0/A8
19 P2.1/A9
20 P2.2/A10
21 P2.3/A11
22 P2.4/A12

Pin Function

23 P2.5/A13
24 P2.6/A14
25 P2.7/A15
26 PSEN
27 ALE/PROG
28 NC*
29 EA

/V

PP

30 P0.7/AD7
31 P0.6/AD6
32 P0.5/AD5
33 P0.4/AD4
34 P0.3/AD3
35 P0.2/AD2
36 P0.1/AD1
37 P0.0/AD0
38 V

CC

39 NC*
40 P1.0
41 P1.1
42 P1.2
43 P.13
44 P1.4

PQFP

44 34

1

11

33

23

12 22

SU00261

* DO NOT CONNECT

LOGIC SYMBOL

PORT 0

PORT 1PORT 2

PORT 3

ADDRESS AND

DATA BUS

ADDRESS BUS

VSSV

CC

ALTERNATE

FUNCTIONS

RST
XTAL1
XTAL2

VPP/EA

PROG/ALE

PSEN

RxD

TxD

INT0
INT1

T0
T1

WR

RD

SCL
SDA

SU00262

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

4

ORDERING INFORMATION

PHILIPS PART

ORDER NUMBER

PART MARKING

PHILIPS NORTH AMERICA

PART ORDER NUMBER

TEMPERATURE

RANGE °C

ROMless ROM ROMless ROM Drawing

Number

AND PACKAGE FREQ

MHz

P80C652FBP P83C654FBP/xxx S80C652FBPN S83C654FBPN SOT129-1 0 to +70, Plastic Dual In-line Package 16

0 to +70, Ceramic Dual In-line Package

w/Window

16

P80C652FBA P83C654FBA/xxx S80C652FBAA S83C654FBAA SOT187-2 0 to +70, Plastic Leaded Chip Carrier 16

P80C652FBB P83C654FBB/xxx S80C652FBBB S83C654FBBB SOT307-2

4

0 to +70, Plastic Quad Flat Pack 16

P80C652FFP P83C654FFP/xxx S80C652FFPN S83C654FFPN SOT129-1 –40 to +85, Plastic Dual In-line Package 16

P80C652FFA P83C654FFA/xxx S80C652FFAA S83C654FFAA SOT187-2 –40 to +85, Plastic Leaded Chip Carrier 16
P80C652FFB P83C654FFB/xxx S80C652FFBB S83C654FFBB SOT307-2

4

–40 to +85, Plastic Quad Flat Pack 16
P80C652FHP P83C654FHP/xxx S80C652FHPN S83C654FHPN SOT129-1 –40 to +125, Plastic Dual In-line Package 16
P80C652FHA P83C654FHA/xxx S80C652FHAA S83C654FHAA SOT187-2 –40 to +125, Plastic Leaded Chip Carrier 16
P80C652FHB P83C654FHB/xxx S80C652FHBB S83C654FHBB SOT307-2

4

–40 to +125, Plastic Quad Flat Pack 16

P80C652IBP P83C654IBP/xxx S80C652IBPN S83C654IBPN SOT129-1 0 to +70, Plastic Dual In-line Package 24
P80C652IBA P83C654IBA/xxx S80C652IBAA S83C654IBAA SOT187-2 0 to +70, Plastic Leaded Chip Carrier 24
P80C652IBB P83C654IBB/xxx S80C652IBBB S83C654IBBB SOT307-2

4

0 to +70, Plastic Quad Flat Pack 24
P80C652IFP P83C654IFP/xxx S80C652IFPN S83C654IFPN SOT129-1 –40 to +85, Plastic Dual In-line Package 24
P80C652IFA P83C654IFA/xxx S80C652IFAA S83C654IFAA SOT187-2 –40 to +85, Plastic Leaded Chip Carrier 24
P80C652IFB P83C654IFB/xxx S80C652IFBB S83C654IFBB SOT307-2

4

–40 to +85, Plastic Quad Flat Pack 24

NOTES:

1. For full specification, see the 87C652 data sheet.

2. 87C654 frequency range is 3.5MHz – 16MHz or 3.5MHz – 24MHz.

3. xxx denotes the ROM code number.

4. SOT311 replaced by SOT307-2.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

5

TEMPERATURE

RANGE °C

EPROM Drawing

Number

AND PACKAGE FREQ

MHz

S87C654-4N40 SOT129-1 0 to +70, Plastic Dual In-line Package 16

S87C654-4F40 0590B 0 to +70, Ceramic Dual In-line Package

w/Window

16

S87C654-4A44 SOT187-2 0 to +70, Plastic Leaded Chip Carrier 16
S87C654-4K44 1472A 0 to +70, Ceramic Leaded Chip Carrier

w/Window

16

S87C654–4B44 SOT307-2 0 to +70, Plastic Quad Flat Pack 16

S87C654-5N40 SOT129-1 –40 to +85, Plastic Dual In-line Package 16

S87C654-5F40 0590B –40 to +85, Ceramic Dual In-line Package

w/Window

16

S87C654-5A44 SOT187-2 –40 to +85, Plastic Leaded Chip Carrier 16
S87C654-5B44 SOT307-2 –40 to +85, Plastic Quad Flat Pack 16

S87C654–7N40 SOT129-1 0 to +70, Plastic Dual In-line Package 20

S87C654–7F40 0590B 0 to +70, Ceramic Dual In-line Package

w/Window

20

S87C654–7A44 SOT187-2 0 to +70, Plastic Leaded Chip Carrier 20
S87C654–7K44 1472A 0 to +70, Ceramic Leaded Chip Carrier

w/Window

20

S87C654–8N40 SOT129-1 –40 to +85, Plastic Dual In-line Package 20

S87C654–8F40 0590B –40 to +85, Ceramic Dual In-line Package

w/Window

20

S87C654–8A44 SOT187-2 –40 to +85, Plastic Leaded Chip Carrier 20

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

6

BLOCK DIAGRAM

64K BYTE BUS

EXPANSION

CONTRTOL

PROG SERIAL PORT
FULL DUPLEX UART

SYNCHRONOUS SHIFT

PROGRAMMABLE I/O

CPU

OSCILLATOR

AND

TIMING

PROGRAM

MEMORY

DATA

MEMORY

(256 x 8 RAM)

TWO 16-BIT

TIMER/EVENT

COUNTERS

I

2

C SERIAL I/O

SDA

SCL

SHARED

WITH

PORT 1

T0 T1

COUNTERS

XTAL2 XTAL1

FREQUENCY
REFERENCE

INTERNAL

INTERRUPTS

INT0

INT1

EXTERNAL

INTERRUPTS

CONTROL

PARALLEL PORTS,

ADDRESS/DATA BUS

AND I/O PINS

SERIAL IN SERIAL OUT

SHARED WITH

PORT 3

(16K x 8

EPROM)

SU00271

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

7

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

DIP LCC QFP TYPE NAME AND FUNCTION

V

SS

20 22 16 I Ground: 0V reference.

V

CC

40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down

operation.

P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them

float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code
bytes during program verification in the 87C654. External pull-ups are required during
program verification.

P1.0–P1.7 1–8 2–9 40–44,

1–3

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7

which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics: I

IL

).
Port 1 also receives the low-order address byte during program memory verification.
Alternate functions include:

P1.6 7 8 2 I/O SCL: I2C-bus serial port clock line.
P1.7 8 9 3 I/O SDA: I2C-bus serial port data line.

P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I

IL

). Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.

P3.0–P3.7 10–17 11,

13–195,7–13

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: I

IL

). Port 3 also serves the special features of the 80C51

family, as listed below:

10 11 5 I RxD (P3.0): Serial input port
11 13 7 O TxD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): External interrupt
13 15 9 I INT1 (P3.3): External interrupt
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External data memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe

RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

device. An internal diffused resistor to V

SS

permits a power-on reset using only an external

capacitor to V

CC

.

ALE/PROG 30 33 27 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
also the program pulse input (PROG

) during EPROM programming.

PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the 87C654 is

executing code from the external program memory, PSEN

is activated twice each machine

cycle, except that two PSEN

activations are skipped during each access to external data

memory. PSEN

is not activated during fetches from internal program memory.

EA/V

PP

31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to

enable the device to fetch code from external program memory locations 0000H and 3FFFH.
If EA

is held high, the device executes from internal program memory unless the program
counter contains an address greater than 3FFFH. This pin also receives the 12.75V
programming supply voltage (V

PP

) during EPROM programming.

XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

circuits.

XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V

CC

+ 0.5V or VSS – 0.5V, respectively.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

8

Table 1. 8XC652/654 Special Function Registers

SYMBOL DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB LSB

RESET
VALUE

ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H
B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H
DPTR:

DPH
DPL

Data pointer
(2 bytes)
Data pointer high
Data pointer low

83H
82H

00H
00H

AF AE AD AC AB AA A9 A8

IE*# Interrupt enable A8H EA ES1 ES0 ET1 EX1 ET0 EX0 0x000000B

BF BE BD BC BB BA B9 B8

IP*# Interrupt priority B8H – PS1 PS0 PT1 PX1 PT0 PX0 xx000000B

87 86 85 84 83 82 81 80

P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH

97 96 95 94 93 92 91 90

P1*# Port 1 90H SDA SCL FFH

A7 A6 A5 A4 A3 A2 A1 A0

P2* Port 2 A0H A15 A14 A13 A12 A11 A10 A9 A8 FFH

B7 B6 B5 B4 B3 B2 B1 B0
P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TXD RXD FFH
PCON# Power control 87H SMOD – – – GF1 GF0 PD IDL 0xxx0000B

9F 9E 9D 9C 9B 9A 99 98
S0CON*# Serial 0 port control 98H SM0 SM1 SM2 REN TB8 RB8 TI RI 00H
S0BUF# Serial 0 data buffer 99H xxxxxxxxB

D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00H
S1DAT# Serial 1 data DAH 00H
SP Stack pointer 81H 07H
S1ADR# Serial 1 address DBH

 SLAVE ADDRESS 

GC 00H

S1STA# Serial 1 status D9H SC4 SC3 SC2 SC1 SC0 0 0 0 F8H

DF DE DD DC DB DA D9 D8
S1CON*# Serial 1 control D8H CR2 ENS1 STA STO SI AA CR1 CR0 00000000B

8F 8E 8D 8C 8B 8A 89 88
TCON* Timer control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
TH1 Timer high 1 8DH 00H
TH0 Timer high 0 8CH 00H
TL1 Timer low 1 8BH 00H
TL0 Timer low 0 8AH 00H
TMOD Timer mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H

* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

9

OSCILLATOR
CHARACTERISTICS

XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol.

To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.

Reset

A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few

milliseconds) plus two machine cycles. At
power-on, the voltage on V

CC

and RST must
come up at the same time for a proper
start-up.

Idle Mode

In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.

Power-Down Mode

In the power-down mode, the oscillator is
stopped and the instruction to invoke

power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 2
shows the state of the I/O ports during low
current operating modes.

I2C SERIAL
COMMUNICATION—SIO1

The I2C serial port is identical to the I2C
serial port on the 8XC552. The operation of
this subsystem is described in detail in the
8XC552 section of this manual.

Note that in both the 8XC652/4 and the
8XC552 the I

2

C pins are alternate functions
to port pins P1.6 and P1.7. Because of this,
P1.6 and P1.7 on these parts do not have a
pull-up structure as found on the 80C51.
Therefore P1.6 and P1.7 have open drain
outputs on the 8XC652/4.

Table 2. External Pin Status During Idle and Power-Down Mode

MODE

PROGRAM

MEMORY

ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3

Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data

Serial Control Register (S1CON) – See Table 3

S1CON (D8H)

CR2 ENS1 STA STO SI AA CR1 CR0

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

Table 3. Serial Clock Rates

BIT FREQUENCY (kHz) AT f

OSC

CR2 CR1 CR0

6MHz 12MHz 16MHz 20MHz f

OSC

DIVIDED BY

0 0 0 23 47 62.5 78 256
0 0 1 27 54 71 89

1

224

0 1 0 31.25 62.5 83.3 104

1

192

0 1 1 37 75 100 125

1

160
1 0 0 6.25 12.5 17 21 960
1 0 1 50 100 133

1

166

1

120
1 1 0 100 200

1

267

1

334

1

60

1 1 1 0.25 < 62.5

0 to 255

0.5 < 62.5
0 to 254

0.65 < 55.6
0 to 253

0.81 < 69.4
0 to 253

96 × (256 – (reload value Timer 1))

(Reload value range: 0 – 254 in mode 2)

NOTES:

1. These frequencies exceed the upper limit of 100kHz of the I

2

C-bus specification and cannot be used in an I2C-bus application.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

10

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER RATING UNIT

Storage temperature range –65 to +150 °C
Voltage on EA/VPP to V

SS

–0.5 to + 13 V

Voltage on any other pin to V

SS

–0.5 to + 6.5 V
Input, output current on any single pin ±5 mA
Power dissipation (based on package heat transfer

limitations, not device power consumption)

1 W

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any conditions other than those described in the AC and DC Electrical
Characteristics section of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices
from the damaging effects of excessive static charge. Nonetheless, it is suggested that
conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All
voltages are with respect to V

SS

unless otherwise noted.

DEVICE SPECIFICATIONS

SUPPLY VOLTAGE

(V)

FREQUENCY

(MHz)

TEMPERATURE

RANGE

TYPE MIN. MAX. MIN. MAX. (°C)

S87C654–4 4.5 5.5 3.5 16 0 to +70
S87C654–5 4.5 5.5 3.5 16 –40 to +85
S87C654–7 4.5 5.5 3.5 20 0 to +70
S87C654–8 4.5 5.5 3.5 20 –40 to +85

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

11

DC ELECTRICAL CHARACTERISTICS

VSS = 0V

TEST LIMITS

SYMBOL PARAMETER PART TYPE CONDITIONS MIN. MAX. UNIT

V

IL

Input low voltage,
except EA

, P1.6/SCL, P1.7/SDA

0 to +70°C

–40 to +85°C

–0.5
–0.5

0.2VCC–0.1

0.2V

CC

–0.15

V
V

V

IL1

Input low voltage to EA 0 to +70°C

–40 to +85°C

–0.5
–0.5

0.2VCC–0.3

0.2V

CC

–0.35

V
V

V

IL2

Input low voltage to P1.6/SCL, P1.7/SDA

1

–0.5 0.3V

CC

V

V

IH

Input high voltage,
except XTAL1, RST, P1.6/SCL, P1.7/SDA

0 to +70°C

–40 to +85°C

0.2VCC+0.9

0.2V

CC

+1.0

VCC+0.5
V

CC

+0.5

V
V

V

IH1

Input high voltage, XTAL1, RST 0 to +70°C

–40 to +85°C

0.7V

CC

0.7VCC+0.1

VCC+0.5
V

CC

+0.5

V
V

V

IH2

Input high voltage, P1.6/SCL, P1.7/SDA

1

0.7V

CC

6.0 V

V

OL

Output low voltage, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA

IOL = 1.6mA

2, 3

0.45 V

V

OL1

Output low voltage, port 0, ALE, PSEN IOL = 3.2mA

2, 3

0.45 V

V

OL2

Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA 0.4 V

V

OH

Output high voltage, ports 1, 2, 3 0 to +70°C

–40 to +85°C

IOH = –60µA
I

OH

= –25µA

2.4

0.75V

CC

V
V

V

OH1

Output high voltage; port 0 in external bus mode,
ALE, PSEN, RST

4

0 to +70°C

–40 to +85°C

IOH = –400µA
IOH = –150µA

2.4

0.75V

CC

V
V

I

IL

Logical 0 input current, ports 1, 2, 3, 4,
except P1.6/SCL, P1.7/SDA

0 to +70°C

–40 to +85°C

VIN = 0.45V –50

–75

µA
µA

I

TL

Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA

0 to +70°C

–40 to +85°C

See note 5 –650

–750

µA
µA

I

L1

Input leakage current, port 0 0.45V < V

I

< V

CC

±10 µA

I

L2

Input leakage current, P1.6/SCL, P1.7/SDA 0V < V

I

< 6.0V

0V < V

CC

< 6.0V

±10 µA

µA

I

CC

Power supply current: See note 6

VCC=6.0V

Active mode @ 16MHz

7

25 mA

Idle mode @ 16MHz

8

6 mA

Power down mode

9, 10

0 to +70°C 50 µA

Power down mode

9, 10

–40 to +85°C 135 µA

R

RST

Internal reset pull-down resistor 50 150 kΩ

C

IO

Pin capacitance Freq.=1MHz 10 pF

NOTES: See Next Page.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

12

NOTES FOR DC ELECTRICAL CHARACTERISTICS:

1. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I

2

C specification, so an input voltage below 0.3VCC will be recognized as a

logic 0 while an input voltage above 0.7V

CC

will be recognized as a logic 1.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

OL

s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V . In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I

OL

can exceed these conditions provided that no

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Under steady state (non-transient) conditions, I

OL

must be externally limited as follows: Maximum IOL = 10mA per port pin; Maximum

I

OL

= 26mA total for Port 0; Maximum IOL = 15mA total for Ports 1, 2, and 3; Maximum IOL = 71mA total for all output pins. If IOL exceeds the

test conditions, V

OL

may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

4. Capacitive loading on ports 0 and 2 may cause the V

OH

on ALE and PSEN to momentarily fall below the 0.9VCC specification when the

address bits are stabilizing.

5. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V

IN

is approximately 2V.

6. See Figures 9 through 11 for I

CC

test conditions.

7. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns;
V

IL

= VSS + 0.5V; VIH = V

CC

–0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VCC; f

CLK

= 16MHz. See Figure 9.

8. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

r

= tf = 10ns; VIL = VSS + 0.5V;

V

IH

= V

CC

–0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VCC; EA = RST = VSS; f

CLK

= 16MHz. See Figure 10.

9. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V

CC

;

EA

= RST = VSS. See Figure 11.

10.2V ≤ V

PD

≤ VCCmax.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

13

AC ELECTRICAL CHARACTERISTICS

1, 2

16MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT

1/t

CLCL

2 Oscillator frequency Speed Versions

87C654 –4, –5

3.5 16 MHz

t

LHLL

2 ALE pulse width 85 2t

CLCL

–40 ns

t

AVLL

2 Address valid to ALE low 8 t

CLCL

–55 ns

t

LLAX

2 Address hold after ALE low 28 t

CLCL

–35 ns

t

LLIV

2 ALE low to valid instruction in 150 4t

CLCL

–100 ns

t

LLPL

2 ALE low to PSEN low 23 t

CLCL

–40 ns

t

PLPH

2 PSEN pulse width 143 3t

CLCL

–45 ns

t

PLIV

2 PSEN low to valid instruction in 83 3t

CLCL

–105 ns

t

PXIX

2 Input instruction hold after PSEN 0 0 ns

t

PXIZ

2 Input instruction float after PSEN 38 t

CLCL

–25 ns

t

AVIV

2 Address to valid instruction in 208 5t

CLCL

–105 ns

t

PLAZ

2 PSEN low to address float 10 10 ns

Data Memory

t

AVLL

3, 4 Address valid to ALE low 28 t

CLCL

–35 ns

t

RLRH

3, 4 RD pulse width 275 6t

CLCL

–100 ns

t

WLWH

3, 4 WR pulse width 275 6t

CLCL

–100 ns

t

RLDV

3, 4 RD low to valid data in 148 5t

CLCL

–165 ns

t

RHDX

3, 4 Data hold after RD 0 0 ns

t

RHDZ

3, 4 Data float after RD 55 2t

CLCL

–70 ns

t

LLDV

3, 4 ALE low to valid data in 350 8t

CLCL

–150 ns

t

AVDV

3, 4 Address to valid data in 398 9t

CLCL

–165 ns

t

LLWL

3, 4 ALE low to RD or WR low 138 238 3t

CLCL

–50 3t

CLCL

+50 ns

t

AVWL

3, 4 Address valid to WR low or RD low 120 4t

CLCL

–130 ns

t

QVWX

3, 4 Data valid to WR transition 3 t

CLCL

–60 ns

t

DW

3, 4 Data setup time before WR 288 7t

CLCL

–150 ns

t

WHQX

3, 4 Data hold after WR 13 t

CLCL

–50 ns

t

RLAZ

3, 4 RD low to address float 0 0 ns

t

WHLH

3, 4 RD or WR high to ALE high 23 103 t

CLCL

–40 t

CLCL

+40 ns

Shift Register

t

XLXL

5 Serial port clock cycle time

3

0.75 12t

CLCL

µs

t

QVXH

5 Output data setup to clock rising edge

3

492 10t

CLCL

–133 ns

t

XHQX

5 Output data hold after clock rising edge

3

80 2t

CLCL

–117 ns

t

XHDX

5 Input data hold after clock rising edge

3

0 0 ns

t

XHDV

5 Clock rising edge to input data valid

3

492 10t

CLCL

–133 ns

External Clock

t

CHCX

6 High time

3

20 20 t

CLCL –

t

LOW

ns

t

CLCX

6 Low time

3

20 20 t

CLCL –

t

HIGH

ns

t

CLCH

6 Rise time

3

20 20 ns

t

CHCL

6 Fall time

3

20 20 ns

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100pF, load capacitance for all other outputs = 80pF.

3. These values are characterized but not 100% production tested.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

14

AC ELECTRICAL CHARACTERISTICS

1, 2

20MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT

1/t

CLCL

2 Oscillator frequency: Speed Versions

87C654 –7, –8

3.5 20 MHz

t

LHLL

2 ALE pulse width 60 2t

CLCL

–40 ns

t

AVLL

2 Address valid to ALE low 25 t

CLCL

–25 ns

t

LLAX

2 Address hold after ALE low 25 t

CLCL

–25 ns

t

LLIV

2 ALE low to valid instruction in 135 4t

CLCL

–65 ns

t

LLPL

2 ALE low to PSEN low 25 t

CLCL

–25 ns

t

PLPH

2 PSEN pulse width 105 3t

CLCL

–45 ns

t

PLIV

2 PSEN low to valid instruction in 90 3t

CLCL

–60 ns

t

PXIX

2 Input instruction hold after PSEN 0 0 ns

t

PXIZ

2 Input instruction float after PSEN 25 t

CLCL

–25 ns

t

AVIV

2 Address to valid instruction in 170 5t

CLCL

–80 ns

t

PLAZ

2 PSEN low to address float 10 10 ns

Data Memory

t

AVLL

3, 4 Address valid to ALE low 25 t

CLCL

–25 ns

t

RLRH

3, 4 RD pulse width 200 6t

CLCL

–100 ns

t

WLWH

3, 4 WR pulse width 200 6t

CLCL

–100 ns

t

RLDV

3, 4 RD low to valid data in 160 5t

CLCL

–90 ns

t

RHDX

3, 4 Data hold after RD 0 0 ns

t

RHDZ

3, 4 Data float after RD 72 2t

CLCL

–28 ns

t

LLDV

3, 4 ALE low to valid data in 250 8t

CLCL

–150 ns

t

AVDV

3, 4 Address to valid data in 285 9t

CLCL

–165 ns

t

LLWL

3, 4 ALE low to RD or WR low 100 200 3t

CLCL

–50 3t

CLCL

+50 ns

t

AVWL

3, 4 Address valid to WR low or RD low 125 4t

CLCL

–75 ns

t

QVWX

3, 4 Data valid to WR transition 20 t

CLCL

–30 ns

t

DW

3, 4 Data setup time before WR 220 7t

CLCL

–130 ns

t

WHQX

3, 4 Data hold after WR 25 t

CLCL

–25 ns

t

RLAZ

3, 4 RD low to address float 0 0 ns

t

WHLH

3, 4 RD or WR high to ALE high 25 75 t

CLCL

–25 t

CLCL

+25 ns

Shift Register

t

XLXL

5 Serial port clock cycle time

3

0.6 12t

CLCL

µs

t

QVXH

5 Output data setup to clock rising edge

3

367 10t

CLCL

–133 ns

t

XHQX

5 Output data hold after clock rising edge

3

40 2t

CLCL

–60 ns

t

XHDX

5 Input data hold after clock rising edge

3

0 0 ns

t

XHDV

5 Clock rising edge to input data valid

3

367 10t

CLCL

–133 ns

External Clock

t

CHCX

6 High time

3

17 17 t

CLCL –

t

LOW

ns

t

CLCX

6 Low time

3

17 17 t

CLCL –

t

HIGH

ns

t

CLCH

6 Rise time

3

20 20 ns

t

CHCL

6 Fall time

3

20 20 ns

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100pF, load capacitance for all other outputs = 80pF.

3. These values are characterized but not 100% production tested.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

15

AC ELECTRICAL CHARACTERISTICS – I2C INTERFACE

SYMBOL PARAMETER INPUT OUTPUT

SCL TIMING CHARACTERISTICS

tHD; STA START condition hold time ≥ 14 t

CLCL

> 4.0µs

1

t

LOW

SCL LOW time ≥ 16 t

CLCL

> 4.7µs

1

t

HIGH

SCL HIGH time ≥ 14 t

CLCL

> 4.0µs

1

t

RC

SCL rise time ≤ 1µs –

2

t

FC

SCL fall time ≤ 0.3µs < 0.3µs

3

SDA TIMING CHARACTERISTICS

tSU; DAT1 Data set-up time ≥ 250ns > 20 t

CLCL

– t

RD

tSU; DAT2 SDA set-up time (before rep. START cond.) ≥ 250ns > 1µs

1

tSU; DAT3 SDA set-up time (before STOP cond.) ≥ 250ns > 8 t

CLCL

tHD; DAT Data hold time ≥ 0ns > 8 t

CLCL

– t

FC

tSU; STA Repeated START set-up time ≥ 14 t

CLCL

> 4.7µs

1

tSU; STO STOP condition set-up time ≥ 14 t

CLCL

> 4.0µs

1

t

BUF

Bus free time ≥ 14 t

CLCL

> 4.7µs

1

t

RD

SDA rise time ≤ 1µs –

2

t

FD

SDA fall time ≤ 0.3µs < 0.3µs

3

NOTES:

1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs.

3. Spikes on the SDA and SCL lines with a duration of less than 3 t

CLCL

will be filtered out. Maximum capacitance on bus-lines SDA and

SCL = 400pF.

4. t

CLCL

= 1/f

OSC

= one oscillator clock period at pin XTAL1. For 62ns < t

CLCL

< 285ns (16MHz) > f

OSC

> 3.5MHz) the SI01 interface meets the

I

2

C-bus specification for bit-rates up to 100 kbit/s.

TIMING SIO1 (I2C) INTERFACE

t

RD

t

SU;STA

t

BUF

t

SU;STO

0.7 V

CC

0.3 V

CC

0.7 V

CC

0.3 V

CC

t

FDtRC

t

FC

t

HIGH

t

LOW

t

HD;STA

t

SU;DAT1

t

HD;DAT

t

SU;DAT2

t

SU;DAT3

START condition

repeated START condition

SDA

(INPUT/OUTPUT)

SCL

(INPUT/OUTPUT)

STOP condition

START or repeated START condition

SU00107A

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

16

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The
first character is always ‘t’ (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN

Q – Output data
R – RD

signal
t – Time
V – Valid
W – WR

signal
X – No longer a valid logic level
Z – Float
Examples: t

AVLL

= Time for address valid

to ALE low.

t

LLPL

= Time for ALE low

to PSEN

low.

t

PXIZ

ALE

PSEN

PORT 0

PORT 2

A0–A15 A8–A15

A0–A7 A0–A7

t

AVLL

t

PXIX

t

LLAX

INSTR IN

t

LHLL

t

PLPH

t

LLIV

t

PLAZ

t

LLPL

t

AVIV

SU00006

t

PLIV

Figure 1. External Program Memory Read Cycle

t

LLAX

ALE

PSEN

PORT 0

PORT 2

RD

A0–A7

FROM RI OR DPL

DATA IN A0–A7 FROM PCL INSTR IN

P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH

t

WHLH

t

LLDV

t

LLWL

t

RLRH

t

RLAZ

t

AVLL

t

RHDX

t

RHDZ

t

AVWL

t

AVDV

t

RLDV

SU00177

Figure 2. External Data Memory Read Cycle

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

17

t

LLAX

ALE

PSEN

PORT 0

PORT 2

WR

A0–A7

FROM RI OR DPL

DATA OUT A0–A7 FROM PCL INSTR IN

P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH

t

WHLH

t

LLWL

t

WLWH

t

AVLL

t

AVWL

t

QVWX

t

WHQX

t

DW

SU00213

Figure 3. External Data Memory Write Cycle

0 1 2 3 4 5 6 7 8

INSTRUCTION

ALE

CLOCK

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI

VALID VALID VALID VALID VALID VALID VALID VALID

SET TI

SET RI

t

XLXL

t

QVXH

t

XHQX

t

XHDX

t

XHDV

SU00027

1 2 30 4 5 6 7

Figure 4. Shift Register Mode Timing

VCC–0.5

0.45V

0.7V

CC

0.2VCC–0.1

t

CHCL

t

CLCL

t

CLCH

t

CLCX

t

CHCX

SU00009

Figure 5. External Clock Drive

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

18

VCC–0.5

0.45V

0.2V

CC

+0.9

0.2V

CC

–0.1

NOTE:
AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at V

IH

min for a logic ‘1’ and VIL max for a logic ‘0’.

SU00010

Figure 6. AC Testing Input/Output

V

LOAD

V

LOAD

+0.1V

V

LOAD

–0.1V

V

OH

–0.1V

V

OL

+0.1V

NOTE:

TIMING

REFERENCE

POINTS

For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded V

OH/VOL

level occurs. IOH/IOL ≥ ±20mA.

SU00011

Figure 7. Float Waveform

V

CC

P0

EA

RST

XTAL1

XTAL2

V

SS

V

CC

V

CC

V

CC

I

CC

(NC)

CLOCK SIGNAL

P1.6
P1.7

*
*

87C654

SU00272

Figure 8. ICC Test Condition, Active Mode

All other pins are disconnected

NOTE:

* Ports 1.6 and 1.7 should be connected to V

CC

through resistors of sufficiently high value such that the sink current into these pins does not

exceed the I

OL1

specification.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

19

V

CC

P0

RST

XTAL1

XTAL2

V

SS

V

CC

V

CC

I

CC

(NC)

CLOCK SIGNAL

P1.6
P1.7

EA

*
*

87C654

SU00273

Figure 9. ICC Test Condition, Idle Mode

All other pins are disconnected

VCC–0.5

0.45V

0.7V

CC

0.2VCC–0.1

t

CHCL

t

CLCL

t

CLCH

t

CLCX

t

CHCX

SU00009

Figure 10. Clock Signal Waveform for ICC Tests in Active and Idle Modes

t

CLCH

= t

CHCL

= 10ns

V

CC

P0

RST

XTAL1

XTAL2

V

SS

V

CC

V

CC

I

CC

(NC)

P1.6
P1.7

EA

*
*

87C654

SU00274

Figure 11. ICC Test Condition, Power Down Mode
All other pins are disconnected. V

CC

= 2V to 5.5V

NOTE:

* Ports 1.6 and 1.7 should be connected to V

CC

through resistors of sufficiently high value such that the sink current into these pins does not

exceed the I

OL1

specification.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

20

EPROM CHARACTERISTICS

The 87C654 is programmed by using a
modified Quick-Pulse Programming
algorithm. It differs from older methods in the
value used for V

PP

(programming supply
voltage) and in the width and number of the
ALE/PROG

pulses.

The 87C654 contains two signature bytes
that can be read and used by an EPROM
programming system to identify the device.
The signature bytes identify the device as an
87C654 manufactured by Philips
Components.

Table 4 shows the logic levels for reading the
signature byte, and for programming the
program memory, the encryption table, and
the lock bits. The circuit configuration and
waveforms for quick-pulse programming are
shown in Figures 12 and 13. Figure 14 shows
the circuit configuration for normal program
memory verification.

Quick-Pulse Programming

The setup for microcontroller quick-pulse
programming is shown in Figure 12. Note that
the 87C654 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to
be running is that the device is executing
internal address and program data transfers.

The address of the EPROM location to be
programmed is applied to ports 1 and 2, as
shown in Figure 12. The code byte to be
programmed into that location is applied to
port 0. RST, PSEN

and pins of ports 2 and 3
specified in Table 4 are held at the ‘Program
Code Data’ levels indicated in Table 4. The
ALE/PROG

is pulsed low 25 times as shown

in Figure 13.

To program the encryption table, repeat the
25 pulse programming sequence for
addresses 0 through 1FH, using the ‘Pgm
Encryption Table’ levels. Do not forget that
after the encryption table is programmed,
verification cycles will produce only encrypted
data.

To program the lock bits, repeat the 25 pulse
programming sequence using the ‘Pgm Lock
Bit’ levels. After one lock bit is programmed,
further programming of the code memory and
encryption table is disabled. However, the
other lock bit can still be programmed.

Note that the EA

/VPP pin must not be allowed

to go above the maximum specified V

PP

level
for any amount of time. Even a narrow glitch
above that voltage can cause permanent
damage to the device. The V

PP

source
should be well regulated and free of glitches
and overshoot.

Program Verification

If lock bit 2 has not been programmed, the
on-chip program memory can be read out for
program verification. The address of the
program memory locations to be read is
applied to ports 1 and 2 as shown in
Figure 14. The other pins are held at the
‘Verify Code Data’ levels indicated in Table 4.
The contents of the address location will be
emitted on port 0. External pull-ups are
required on port 0 for this operation.

If the encryption table has been programmed,
the data presented at port 0 will be the
exclusive NOR of the program byte with one
of the encryption bytes. The user will have to
know the encryption table contents in order to
correctly decode the verification data. The
encryption table itself cannot be read out.

Reading the Signature Bytes

The signature bytes are read by the same
procedure as a normal verification of
locations 030H and 031H, except that P3.6
and P3.7 need to be pulled to a logic low. The
values are:
(030H) = 15H indicates manufactured by

Philips

(031H) = 99H indicates 87C654

Program/Verify Algorithms

Any algorithm in agreement with the
conditions listed in Table 4, and which
satisfies the timing specifications, is suitable.

Erasure Characteristics

Erasure of the EPROM begins to occur when
the chip is exposed to light with wavelengths
shorter than approximately 4,000 angstroms.
Since sunlight and fluorescent lighting have
wavelengths in this range, exposure to these
light sources over an extended time (about 1
week in sunlight, or 3 years in room level
fluorescent lighting) could cause inadvertent
erasure. For this and secondary effects, it

is recommended that an opaque label be
placed over the window. For elevated

temperature or environments where solvents
are being used, apply Kapton tape Fluorglas
part number 2345–5, or equivalent.

The recommended erasure procedure is
exposure to ultraviolet light (at 2537
angstroms) to an integrated dose of at least
15W-sec/cm

2

. Exposing the EPROM to an

ultraviolet lamp of 12,000µW/cm

2

rating for
20 to 39 minutes, at a distance of about 1
inch, should be sufficient. Erasure leaves the
array in an all 1s state.

Table 4. EPROM Programming Modes

MODE RST PSEN ALE/PROG EA/V

PP

P2.7 P2.6 P3.7 P3.6

Read signature 1 0 1 1 0 0 0 0
Program code data 1 0 0* V

PP

1 0 1 1
Verify code data 1 0 1 1 0 0 1 1
Pgm encryption table 1 0 0* V

PP

1 0 1 0
Pgm lock bit 1 1 0 0* V

PP

1 1 1 1
Pgm lock bit 2 1 0 0* V

PP

1 1 0 0

NOTES:

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.

2. V

PP

= 12.75V ±0.25V.

3. V

CC

= 5V±10% during programming and verification.

* ALE/PROG

receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a

minimum of 10µs.

Trademark phrase of Intel Corporation.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

21

A0–A7

1
1
1

4–6MHz

+5V

PGM DATA

+12.75V
25 100µs PULSES TO GROUND
0
1

0

A8–A13

P1

RST
P3.6

P3.7
XTAL2

XTAL1

V

SS

V

CC

P0

EA

/V

PP

ALE/PROG

PSEN

P2.7

P2.6

P2.0–P2.5

87C654

SU00275

Figure 12. Programming Configuration

ALE/PROG:

ALE/PROG:

1
0

1
0

25 PULSES

100µs+1010µs MIN

SU00018

Figure 13. PROG

Waveform

A0–A7

1
1
1

4–6MHz

+5V

PGM DATA

1
1
0
0 ENABLE

0

A8–A13

P1

RST
P3.6

P3.7
XTAL2

XTAL1

V

SS

V

CC

P0

EA

/V

PP

ALE/PROG

PSEN

P2.7

P2.6

P2.0–P2.5

87C654

SU00276

Figure 14. Program Verification

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

22

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

T

amb

= 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 15)

SYMBOL

PARAMETER MIN MAX UNIT

V

PP

Programming supply voltage 12.5 13.0 V

I

PP

Programming supply current 50 mA

1/t

CLCL

Oscillator frequency 4 6 MHz

t

AVGL

Address setup to PROG low 48t

CLCL

t

GHAX

Address hold after PROG 48t

CLCL

t

DVGL

Data setup to PROG low 48t

CLCL

t

GHDX

Data hold after PROG 48t

CLCL

t

EHSH

P2.7 (ENABLE) high to V

PP

48t

CLCL

t

SHGL

VPP setup to PROG low 10 µs

t

GHSL

VPP hold after PROG 10 µs

t

GLGH

PROG width 90 110 µs

t

AVQV

Address to data valid 48t

CLCL

t

ELQZ

ENABLE low to data valid 48t

CLCL

t

EHQZ

Data float after ENABLE 0 48t

CLCL

t

GHGL

PROG high to PROG low 10 µs

PROGRAMMING* VERIFICATION*

ADDRESS ADDRESS

DATA IN DATA OUT

LOGIC 1 LOGIC 1

LOGIC 0

t

AVQV

t

EHQZ

t

ELQV

t

EHSH

t

SHGL

t

GHSL

t

GLGH

t

GHGL

t

AVGL

t

GHAX

t

DVGL

t

GHDX

P1.0–P1.7
P2.0–P2.3

PORT 0

ALE/PROG

EA/V

PP

P2.7
ENABLE

SU00270

* FOR PROGRAMMING VERIFICATION SEE FIGURE 12.

FOR VERIFICATION CONDITIONS SEE FIGURE 14.

Figure 15. EPROM Programming and Verification

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I

2

C system provided the system conforms to the

I

2

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

23

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

24

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

25

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

26

0590B 40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)

NOTES:

1. Controlling dimension: Inches. Millimeters are

2. Dimension and tolerancing per ANSI Y14. 5M-1982.

3. “T”, “D”, and “E” are reference datums on the body

4. These dimensions measured with the leads

5. Pin numbers start with Pin #1 and continue

6. Denotes window location for EPROM products.

and include allowance for glass overrun and meniscus

on the seal line, and lid to base mismatch.

constrained to be perpendicular to plane T.

counterclockwise to Pin #40 when viewed

shown in parentheses.

from the top.

– D –

PIN # 1

– E –

0.225 (5.72) MAX.

0.010 (0.254)T E D

0.023 (0.58)

0.015 (0.38)

0.165 (4.19)

0.125 (3.18)

0.070 (1.78)

0.050 (1.27)

– T –

SEATING

PLANE

0.620 (15.75)

0.590 (14.99)

(NOTE 4)

0.598 (15.19)

0.571 (14.50)

BSC

0.600 (15.24)

0.695 (17.65)

0.600 (15.24)

(NOTE 4)

0.015 (0.38)

0.010 (0.25)

0.175 (4.45)

0.145 (3.68)

0.055 (1.40)

0.020 (0.51)

0.100 (2.54) BSC

2.087 (53.01)

2.038 (51.77)

0.098 (2.49)

0.040 (1.02)

0.098 (2.49)

0.040 (1.02)

SEE NOTE 6

853–0590B 06688

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

1996 Aug 16

27

1472A 44-PIN CERQUAD J-BEND (K) PACKAGE

NOTES:

1. All dimensions and tolerances to conform

2. UV window is optional.

3. Dimensions do not include glass protrusion.

Glass protrusion to be 0.005 inches maximum

4. Controlling dimension millimeters.

5. All dimensions and tolerances include

lead trim offset and lead plating finish.

6. Backside solder relief is optional and

dimensions are for reference only.

1.02 (0.040) X 45°

16.89 (0.665)

16.00 (0.630)

17.65 (0.695)

17.40 (0.685)

CHAMFER

45

16.89 (0.665)

16.00 (0.630)

17.65 (0.695)

17.40 (0.685)

on each side.

to ANSI Y14.5–1982.

2

3

3 X 0.63 (0.025) R MIN.

3.05 (0.120)

2.29 (0.090)

4.83 (0.190)

3.94 (0.155)

SEATING

PLANE

0.38 (0.015)

0.51 (0.02) X 45°

6

6

17.65 (0.656)

17.40 (0.685)

1.27 (0.050)

12.7 (0.500)

8.13 (0.320)

7.37 (0.290)

40X

4.83 (0.190)

3.94 (0.155)

SEATING

PLANE

0.15 (0.006) MIN.

0.25 (0.010) R MIN.

0.508 (0.020) R MIN.

0.25 (0.010)

0.15 (0.006)

90 + 5

–10

° °

°

0.076 (0.003) MIN.

DETAIL B

mm/(inch)

SEE DETAIL B

SEE DETAIL A

DETAIL A

TYP. ALL SIDES

mm/(inch)

1.52 (0.060) REF.

0.482 (0.019 + 0.002)

SEATING

PLANE

1.02 + 0.25 (0.040 + 0.010)

BASE PLANE

45 TYP.

4 PLACES

°

0.73 + 0.08 (0.029 + 0.003)

1.27 (0.050) TYP.

NOMINAL

8.13 (0.320)

7.37 (0.290)

3

853-1472A 05854

Philips Semiconductors Product specification

87C654CMOS single-chip 8-bit microcontroller

yyyy mmm dd

28

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.

LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

DEFINITIONS

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation

register eligible circuits under the Semiconductor Chip Protection Act.

 Copyright Philips Electronics North America Corporation 1996

All rights reserved. Printed in U.S.A.

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