INTEGRATED CIRCUITS
82B715
2
C bus extender
I
Preliminary specification
Supesedes data of 1997 Apr 07
IC20 Data Handbook
1998 Jan 09
Philips Semiconductors Preliminary specification
82B715I2C bus extender
DESCRIPTION
The 82B715 is a bipolar integrated circuit intended for application in
2
I
C bus systems.
While retaining all the operating modes and features of the I2C
system it permits extension of the practical separation distance
between components on the I
(SDA) and the clock (SCL) lines.
2
The I
C bus capacitance limit of 400pF restricts practical
communication distances to a few meters. Using one 82B715 at
each end of longer cables reduces the cable loading capacitance on
2
the I
C bus by a factor of 10 times and may allow the use of low
2
C bus by buffering both the data
PIN CONFIGURATIONS
8-Pin Dual In-Line or SO
N.C.
1
L
2
X
3
S
X
4
GND
82B715
8
7
6
5
SU00290
V
L
Y
S
N.C.
CC
Y
cost general purpose wiring to extend bus lengths.
PINNING
FEA TURES
•Dual, bi-directional, unity voltage gain buffer
2
•I
C bus compatible
•Logic signal levels may include both supply and ground
•X10 impedance transformation
•Wide supply voltage range
PIN SYMBOL FUNCTION
1 N.C.
2 L
3 S
X
X
Buffered Bus, LDA or LCL
I2C Bus, SDA or SCL
4 GND Negative Supply
5 N.C.
6 S
7 L
8 V
Y
Y
CC
I2C Bus, SCL or SDA
Buffered Bus, LCL or LDA
Positive Supply
QUICK REFERENCE DATA
LIMITS
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
CC
I
CC
I
line
V
in
V
out
Zin/Z
T
amb
out
Supply voltage 4.5 12 V
Quiescent current 16 mA
Output sink capability 30 mA
Input voltage range 0 V
Output voltage range 0 V
CC
CC
Impedance transformation 8 10 13
T emperature range –40 +85 °C
V
V
ORDERING INFORMATION
DESCRIPTION ORDER CODE DRAWING NUMBER
8-pin plastic dual In-line package P82B715P N SOT97-1
8-pin plastic small outline package P82B715T D SOT96-1
NOTE:
1. For applications requiring, 3V operation and additional buffer performance, see P82B96 Data Sheet.
1998 Jan 09
2
Philips Semiconductors Preliminary specification
82B715I2C bus extender
V
CC
82B715
SDA
SCL
BUFFER
BUFFER
GND
Figure 1. Block Diagram: 82B715
LDA
LCL
SU00291
1998 Jan 09
3
Philips Semiconductors Preliminary specification
82B715I2C bus extender
FUNCTIONAL DESCRIPTION
The 82B715 bipolar integrated circuit contains two identical buffer
circuits which enable I
over long distances without degradation of system performance or
requiring the use of special cables.
The buffer has an effective current gain of ten from I
Buffered bus. Whatever current is flowing out of the I
ten times that current will be flowing into the Buffered bus side (see
Figure 2).
As a consequence of this amplification the system is able to drive
capacitive loads up to ten times the standard limit on the Buffered
bus side. This current based buffering approach preserves the
bi-directional, open-collector/open-drain characteristic of the I
SDA/SCL lines.
To minimize interference and ensure stability, current rise and fall
rates are internally controlled.
2
C and similar bus systems to be extended
V
CC
I2C BUS
S
X
2
C bus to
2
C bus side,
I
B
2
C
APPLICATION NOTES
By using two (or more) 82B715 ICs, a sub-system can be built which
retains the interface characteristics of an I
be included in, or optionally added to, any I
The sub-system features a low impedance or “Buffered” bus,
capable of driving large wiring capacities (see Figure 3).
2
C device so that it may
2
C or related system.
I2C Systems
As with the standard I2C system, pull-up resistors are required to
aprovide the logic HIGH levels on the Buffered bus. (Standard
open-collector configuration of the I
these pull-up resistors depends on the system.
If the buffer is to be permanently connected into the system, the
circuit should be configured with only one pull-up resistor on the
Buffered bus and none on the I
Alternatively a buffer may be connected to an existing I
this case the Buffered bus pull-up will act in parallel with the I
pull-up.
CURRENT
SENSE
2
C bus). The size and number of
2
C bus.
10 (IB)
BUFFERED BUS
L
X
2
C system. In
2
C bus
GND
STANDARD
INTERFACE
SDA
SCL
SU00292
Figure 2. Equivalent Circuit: One Half 82B715
82B715 82B715
1/2
1/2
2
I
C
V
CC
V
CC
BUFFERED
INTERFACE
LONG
CABLE
LDA
LCL
BUFFERED
INTERFACE
1/2
1/2
STANDARD
2
I
C
INTERFACE
SDA
SCL
I2C
DEVICE
SU00293
Figure 3. Minimum Sub-System with 82B715
1998 Jan 09
4
Philips Semiconductors Preliminary specification
82B715I2C bus extender
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
Voltages with respect to pin GND (DIL-8 pin 4).
LIMITS
SYMBOL PARAMETER MIN. MAX. UNIT
VCC to GND Supply voltage range V
V
bus
V
buff
Voltage range I2C Bus, SCL or SDA 0 V
Voltage range Buffered Bus 0 V
CC
I DC current (any pin) 60 mA
P
T
T
tot
stg
amb
Power dissipation 300 mW
Storage temperature range –55 +125 °C
Operating ambient temperature range –40 +85 °C
CHARACTERISTICS
At T
= +25°C and VCC = 5 Volts, unless otherwise specified.
amb
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
Power Supply
V
CC
I
CC
I
CC
I
CC
Drive Currents
ISx, I
Sy
ILx, I
Ly
Input Currents
ISx, I
Sy
ILx, I
Ly
ILx, I
Ly
Impedance Transformation
Zin/Z
out
Supply voltage (operating) 4.5 — 12 V
Supply current — 16 — mA
Supply current at VCC = 12V — 22 — mA
Supply current, both I2C inputs LOW,
— 28 — mA
both buffered outputs sinking 30mA.
Output sink on I2C bus
V
, VSy LOW = 0.4V
Sx
, VLy LOW on Buffered bus = 0.3V
V
Lx
Output sink on Buffered bus
V
, VLy LOW = 0.4V
Lx
, VSy LOW on I2C bus = 0.3V
V
Sx
Input current from I2C bus when
, ILy sink on Buffered bus = 30mA
I
Lx
Input current from Buffered bus when
, ISy sink on I2C bus = 3mA
I
Sx
Leakage current on Buffered bus
V
, VLy = VCC, and VSx, VSy = V
Lx
CC
3 — — mA
30 — — mA
— — 3 mA
— — 3 mA
— — 200 µA
Input/Output impedance 8 10 13
–0.3 +12 V
CC
CC
LIMITS
V
V
Pull-Up Resistance Calculation
In calculating the pull-up resistance values, the gain of the buffer
introduces scaling factors which must be applied to the system
components. Viewing the system from the Buffered bus, all I
capacitances have effectively 10 times their I
In practical systems the pull-up resistance is determined by the rise
time limit for I
2
C systems. As an approximation this limit will be
2
C bus value.
2
C bus
satisfied if the time constant (product of the net resistance and net
capacitance) of the total system is set to 1 microsecond.
The total time constant may either be set by considering each bus
node individually (i.e., the I
2
C nodes, and the Buffered bus node)
and choosing pull-up resistors to give time constants of 1
microsecond for each node; or by combining the capacitances into
an equivalent capacitive loading on the Buffered bus, and
1998 Jan 09
calculating the Buffered bus pull-up resistor required by this
equivalent capacitance.
For each separate bus the pull-up resistor may be calculated as
follows:
R
Where: C
1 sec
C
C
device
device
wiring
= sum of device capacitances connected to each
bus,
and C
= total wiring and stray capacitance on each bus.
wiring
If these capacitances are not known then a good approximation is to
assume that each device presents 10pF of load capacitance and
10pF of wiring capacitance.
5
Philips Semiconductors Preliminary specification
82B715I2C bus extender
2
The capacitance figures for one or more individual I
C bus nodes
should be multiplied by a factor of 10 times, and then added to the
Buffered bus capacitance. Calculation of a new Buffered bus pull-up
resistor will alllow this single pull-up resistor to act for both the
included I
2
C bus nodes and the Buffered bus. Thus it is possible to
combine some or all of these separate pull-up resistors into a single
resistor on the Buffered bus (the value of which is calculated from
the sum of the scaled capacitances on the Buffered bus). If the
buffer is to be permanently connected into the system then all the
separate pull-up resistors should be combined. But if it is to be
connected by adding it onto an existing system, then only those on
the additional I
2
C bus system can be combined onto the Buffered
bus if the original system is required to be able to still operate on a
stand-alone basis.
A further restriction is that the maximum pull-up current, with the bus
LOW, should not exceed the I
2
C bus specification maximum of 3mA,
or 30mA on the Buffered bus. The following formula applies:
V
* 0.4
30mA u
CC
R
P
Where: RP = scaled parallel combination of all pull-up resistors.
If this condition is met, the fall time specifications will also be met.
Figure 4 shows typical loading calculations for the expanded I
2
C
bus.
Sx, Sy, I2C Bus, SDA or SCL
Because the two buffer circuits in the 82B715 are identical either
input pin can be used as the I
clock line.
2
C Bus SDA data line, or the SCL
Lx, Ly, Buffered Bus, LDA or LCL
On the buffered low impedance line side, the corresponding output
becomes LDA and LCL.
VCC, GND — Positive and Negative Supply Pins
In normal use the power supply voltages at each end of the low
impedance line should be comparable. If these differ by a significant
amount, noise margin is sacrificed.
1998 Jan 09
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Philips Semiconductors Preliminary specification
82B715I2C bus extender
V
CC
GND
EFFECTIVE CAPACITANCE
NEAR I2C DEVICES
2 × I2C Devices 20pF
Strays 20pF
82B715 Buffer 10pF
–––––
I2C
I2C
EXISTING
SDA
SDA
R1
EFFECTIVE CAPACITANCE
TOTAL CAP . 3000pF
PROPOSED BUS EXPANSION
LDA SDA
3nF
BUFFERED LINE
Wiring Cap. 3000pF
–––––
5V
R3R2
I2C
0V
EFFECTIVE CAPACITANCE
REMOTE I2C DEVICES
1 × I
82B715 Buffer 10pF
TOTAL CAP . 50pF
2
C pull-up Buffered Bus pull-up I2C pull-up
I
R1 +
1m sec
+ 20KW R2 +
50pF
1m sec
+ 333W R3 +
3000pF
2
C Devices 10pF
Strays 10pF
–––––
TOTAL CAP . 30pF
1m sec
+ 33KW
30pF
AS AN ADDITION TO AN EXISTING SYSTEM * :
R1 = 20KΩ
R2Ȁ+
R2 0.1R3
R2 ) 0.1R3
+ 300W
R3 not required since
buffer always connected
FOR A PERMANENT SYSTEM * :
R1 not required since
buffer always connected
R2Ȁ+
1
0.1R1
)
1
1
0.1R2
)
1
0.1R3
+ 262W
R3 not required since
buffer always connected
* NOTE:
R1, R2 and R3 are calculated from the capacitive loading and a 1µsec time constant on each bus node. For an addition to an existing
system, R2’ (the new value for R2) is shown as being calculated from the parallel combination of R2 and the scaled value of R3;
while for a permanent system R2, and scaled values of R1 and R3 have been used. Note that this example has used scaled resistor
values and combined the node and cable capacitances.
CHECK FOR MAXIMUM PULL-UP CURRENT:
(5 * 0.4)V
260W
+ 17.6mA t 30mA
SU00294
Figure 4. Typical Loading Calculation: I2C Bus with 82B715
1998 Jan 09
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Philips Semiconductors Preliminary specification
82B715I2C bus extender
DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1
1998 Jan 09
8
Philips Semiconductors Preliminary specification
82B715I2C bus extender
SO8: plastic small outline package; 8 leads; body width 3.9mm SOT96-1
1998 Jan 09
9
Philips Semiconductors Preliminary specification
82B715I2C bus extender
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Date of release: 06-98
Document order number: 9397 750 04049
1998 Jan 09
10
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