
149
P4C1024 MILITARY
ADVANCE INFORMATION
HIGH SPEED 128K x 8
CMOS STATIC RAM
The P4C1024 device provides asynchronous operations with matching access and cycle times. Memory
locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and
CE2 high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or OE is HIGH or WE or CE2 is LOW.
The P4C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 20 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1024
is a member of a family of P ACE RAM™ products offering fast access times.
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—32-Pin 400 mil and 600 mil Ceramic DIP
—32-Pin CERPACK
—32-Pin LCC
High Speed (Equal Access and Cycle Times)
— 20/25/35/45/55/70 ns
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CECE
CECE
CE
1, CE2
and
OEOE
OEOE
OE Inputs
Common Data I/O
Three-State Outputs
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1Q97
Means Quality, Service and Speed
1024.1
INPUT
DATA
CONTROL
262,144-
BIT
MEMORY
ARRAY
COLUMN
I/O
I/O
1
I/O
2
COLUMN
SELECT
WE
CE
1
• • •
• • •
• • •
ROW SELECT
A
A
• • •
A
• • •
A
(8)
(9)
• • •
• • •
• • •
• • •
CE
2
OE
CONTROL
CIRCUIT
DESCRIPTION
FEATURES
A
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1024.2
GND
WE
A
11
OE
I/O
7
I/O
6
I/O
5
NC
A
13
V
CC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
15
16 17
18
I/O
3
I/O
4
CE1
A
9
A
8
CE
2
A
15
DIP, SOJ
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