Datasheet P4C1024-15J3C, P4C1024-15P3C, P4C1024-17J3C, P4C1024-17P3C, P4C1024-20P3C Datasheet (NCE RFORM)
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141
P4C1024
P4C1024
HIGH SPEED 128K x 8
CMOS STATIC RAM
The P4C1024 device provides asynchronous operations with matching access and cycle times. Memory
locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and
CE2 high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or OE is HIGH or WE or CE2 is LOW.
Package options for the P4C1024 include 32-pin 300
mil DIP and SOJ packages as well as 400 mil SOJ.
The P4C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 15 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1024
is a member of a family of P ACE RAM™ products offering fast access times.
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
High Speed (Equal Access and Cycle Times)
— 15/17/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CECE
CECE
CE
1, CE2
and
OEOE
OEOE
OE Inputs
Common Data I/O
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1Q97
Means Quality, Service and Speed
1024.1
INPUT
DATA
CONTROL
262,144-
BIT
MEMORY
ARRAY
COLUMN
I/O
I/O
1
I/O
2
COLUMN
SELECT
WE
CE
1
• • •
• • •
• • •
ROW SELECT
A
A
• • •
A
• • •
A
(8)
(9)
• • •
• • •
• • •
• • •
CE
2
OE
CONTROL
CIRCUIT
DESCRIPTION
FEATURES
A
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1024.2
GND
WE
A
11
OE
I/O
7
I/O
6
I/O
5
NC
A
13
V
CC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
15
16 17
18
I/O
3
I/O
4
CE1
A
9
A
8
CE
2
A
15
DIP (P300), SOJ (J300, J400)
TOP VIEW
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142
P4C1024
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
MAXIMUM RATINGS
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress
ratings only . Functional operation of the device is not implied at these or any other conditions in excess of those
given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can
adversely affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
Temperature Range (Ambient)
Supply Voltage
4.5V ≤ VCC ≤ 5.5V
Industrial (-40°C to 85°C)
4.5 ≤ VCC ≤ 5.5V
Commercial (0°C to 70°C)
Symbol
Parameter
Min
Max Unit
V
CC
Supply Voltage with Respect to GND -0.5 7.0 V
V
TERM
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
VCC + 0.5
V
T
A
Operating Ambient T emperature
-55 125
°C
S
TG
-65 150 °C
I
OUT
Output Current into Low Outputs
25
mA
I
LAT
Latch-up Current >200 mA
Storage Temperature
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
OS
I
SB1
Output High Voltage
(I/O0 - I/O7)
Output Low Voltage
(I/O0 - I/O7)
Input High Voltage
Input Low Voltage
VCC Current
CMOS Standby Current
(CMOS Input Levels)
Output Short-Circuit
Current
Output Leakage Current
Input Leakage Current
IOH = –4mA, VCC = 4.5V
IOL = 8 mA
IOL = 10 mA
VCC = 5.5V, I
OUT
= 0 mA
CE
1
≥ V
CC
-0.2V, CE2 ≤ 0.2V
V
OUT
= GND, VCC = Max (Single
output) not to exceed 30 second
duration
GND ≤ V
OUT
≤ V
CC
Ind'l.
CE
1
≥ VIH or CE2 ≤ V
IL
Com'l.
GND ≤ VIN ≤ V
CC
Ind'l.
Com'l.
Test Conditions
Min Max
Unit
2.4
2.2
-0.5
V
V
V
V
µA
µA
mA
mA
0.4
0.5
VCC + 0.3
0.8
-350
20
(Standard)
V
-10
-5
-10
-5
+10
+5
+10
+5
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143
P4C1024
Max
CAPACITANCES
(VCC = 5.0V, TA = 25°C, f = 1.0 MHz)
Symbol
Parameter
Test Conditions
Max
Unit
C
IN
C
OUT
Input Capacitance
Output Capacitance
VIN = 0V
V
OUT
= 0V
8
10
pF
pF
Symbol
Parameter
Min
Unit
t
RC
15
ns
t
AA
Address Access Time
t
AC
Chip Enable Access
Time
t
OH
Output Hold from
Address Change
ns
t
LZ
Chip Enable to
Output in Low Z
ns
t
HZ
Chip Disable to
Output in High Z
ns
t
OE
Output Enable Low
to Data Valid
ns
t
OLZ
Output Enable Low
to Low Z
ns
t
OHZ
Output Enable High
to High Z
t
PU
Chip Enable to
Power Up Time
ns
t
PD
Chip Disable to
Power Down Time
ns
Read Cycle Time
3
3
0
0
15
15
8
6
12
6
-15
Min
17
3
3
0
0
Max
-17
17
17
9
7
7
15
-20
Min
Max
3
3
0
0
20
20
9
9
9
20
-25
Min
25
3
3
0
0
Max
25
25
11
10
11
20
Min
-35
3
3
0
0
Max
35
35
15
15
15
20
Min
-45
45
3
3
0
0
Max
20
20
25
45
45
ns
ns
ns
20
20
35
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE
2
≥ VIH (min), CE1, and WE ≤ VIL (max). Switching inputs are 0V
and 3V.
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter
Unit
I
CC
Dynamic Operating Current
Commercial
Industrial
190
N/A
180
N/A
mA
mA
-15
-17
Temperature
Range
-20
160
175
-25
150
165
-35
145
160
-45
N/A
155
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144
P4C1024
READ CYCLE NO. 1 (
OEOE
OEOE
OE CONTROLLED)
(1)
NOTES:
1. WE is HIGH for READ cycle. 4. Transition is measured ± 200 mV from steady state voltage
2. CE1 and OE is LOW and CE2 is HIGH for read cycle. prior to change, with loading as specified in Figure1. This
3. ADDRESS must be valid prior to, or coincident with later of parameter is sampled and not 100% tested.
CE1 transition LOW or CE2 transition HIGH. 5. READ Cycle Time is measured from the last valid address to
the first transitioning address.
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
OLZ
ADDRESS
OE
t
RC
DATA OUT
(5)
t
OH
CE
t
LZ
t
AC
t
HZ
t
OHZ
t
t
AA
t
OE
CE
2
READ CYCLE NO. 3 (
CECE
CECE
CE
CONTROLLED)
t
ADDRESS
DATA OUT
AA
t
t
OH
DATA VALID
PREVIOUS DATA VALID
(5)
RC
t
AC
CE
1
DATA OUT
t
RC
t
LZ
DATA VALID
I
CC
I
SB
t
PU
HIGH IMPEDANCE
t
PD
t
HZ
CURRENT
V
CC
SUPPLY
CE
2
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145
P4C1024
Notes:
6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle.
7. OE is LOW for this WRITE cycle to show twz and tow.
8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
WRITE CYCLE NO. 1 (
WEWE
WEWE
WE CONTROLLED)
(6)
ADDRESS
CE
1
t
WC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT DATA UNDEFINED
(9)
(4)
t
CW
t
AW
t
WP
t
DW
t
AH
t
DH
t
OW
t
AS
t
WZ
(4,7)
(7)
CE
2
Symbol Parameter
Max
Min
t
WC
t
CW
t
AS
t
WP
t
AH
t
DH
t
WZ
t
OW
Write Cycle Time
Chip Enable Time
to End of Write
Address Valid to
End of Write
Address Set-up
Time
Write Pulse Width
Address Hold Time
Data Valid to End
of Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
ns
t
AW
t
DW
-15
15
12
12
0
12
0
7
0
3
8
-17
Min
17
13
13
0
12
0
7
0
3
Max
8
-20
20
15
15
0
15
0
8
0
3
Max
Min
10
-25
Min
25
18
20
0
18
0
10
0
3
Max
11
-35
Min
35
22
25
0
22
0
15
0
3
Max
15
-45
Min
45
30
35
0
25
0
20
0
3
Max
18
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
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146
P4C1024
1.5V
Write
Active
Read
TIMING WAVEFORM OF WRITE CYCLE NO.2 (
CECE
CECE
CE CONTROLLED)
(6)
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1024, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground.
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.73V (Thevenin Voltage) at the comparator input, and a
116Ω resistor must be used in series with D
OUT
to match 166Ω
(Thevenin Resistance).
t
WE
ADDRESS
CE
1
DATA OUT
DATA IN
t
WC
DATA VALID
HIGH IMPEDANCE
(9)
t
AS
t
CW
t
AW
t
WP
DW
AH
t
DH
t
(12)
CE
2
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
See Figures 1 and 2
Mode
Standby
Standby
D
OUT
Disabled
Standby
Power
I/OI/O
I/OI/O
I/O
WEWE
WEWE
WE
OEOE
OEOE
OECE
2
CECE
CECE
CE
1
High Z
High Z
D
OUT
High Z
X
X
H
H
L
X
X
H
L
X
X
L
H
H
H
H
X
L
L
L
Standby
Active
Active
High Z
Figure 2. Thevenin Equivalent
30pF* (5pF* for tHZ, t
LZ
t
WZ OW
and t
,
)
D
OUT
166.5 Ω
VTH= 1.73 V
=R
TH
, t
OHZ
,
t
OLZ
,
OLZ
D
OUT
255 Ω
480 Ω
+5V
30pF* (5pF* for t
HZ
, t
LZ
t
WZ OW
and t
,
)
t
OHZ
t
,
,
Figure 1. Output Load
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147
P4C1024
P3
J3
J4
Package
Suffix
Plastic DIP, 300 mil wide standard
Plastic SOJ, 300 mil wide standard
Plastic SOJ, 400 mil wide standard
Description
PACKAGE SUFFIX
TEMPERATURE RANGE SUFFIX
Temperature
Range Suffix
Description
C
I
Commercial Temperature Range,
0˚C to +70˚C
Industrial Temperature Range,
-40˚C to +85˚C
ORDERING INFORMATION
Performance Semiconductor's part numbering scheme is as follows:
SELECTION GUIDE
The P4C1024 is available in the following temperature, speed and package options.
N/A
N/A
N/A
Speed (ns)
-20P3C
-20J3C
-20J4C
-17
Temperature
Range
Package
Commercial
Temperature
Plastic DIP 300
Plastic SOJ 300
Plastic SOJ 400
Industrial
Temperature
Plastic DIP 300
Plastic SOJ 300
Plastic SOJ 400
-15
-15P3C
-15J3C
-15J4C
-17P3C
-17J3C
-17J4C
N/A
N/A
N/A
-20
-20P3I
-20J3I
-20J4I
-25
-25P3I
-25J3I
-25J4I
-35
-35P3C
-35J3C
-35J4C
-35P3I
-35J3I
-35J4I
-25P3C
-25J3C
-25J4C
N/A = Not Available
1024P4C ss p t
Temperature Range: C, I
Package Code: P3, J3, J4
Speed (Access/Cycle Time): 15, 17, etc.
Device Number: 1024
Static RAM Prefix
Page 8
148
P4C1024
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