Datasheet P3C1256-12JC, P3C1256-12PC, P3C1256-15JC, P3C1256-15JI, P3C1256-20PC Datasheet (NCE RFORM)
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133
P3C1256
P3C1256
HIGH SPEED 32K x 8
3.3V STATIC CMOS RAM
3.3V Power Supply
High Speed (Equal Access and Cycle Times)
— 12/15/20/25 ns (Commercial)
— 15/20/25 ns (Industrial)
Low Power
— 360 mW Active
Single 3.3 Volts ±0.3Volts Power Supply
Easy Memory Expansion Using
CECE
CECE
CE and
OEOE
OEOE
OE
Inputs
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS
1519B
1Q97
Means Quality, Service and Speed
INPUT
DATA
CONTROL
262,144-BIT
MEMORY
ARRAY
COLUMN I/O
I/O
1
I/O
2
COLUMN
SELECT
WE
OE
CE
• • •
• • •
• • •
ROW SELECT
A
A
• • •
A
• • •
A
(7)
(8)
• • •
• • •
• • •
• • •
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 300 mil DIP and SOJ
FEATURES
DESCRIPTION
The P3C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 3.3V± 0.3V tolerance power
supply .
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P3C1256 is a member of a family of P ACE RAM™ products offering fast access times.
The P3C1256 device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output enabling
(OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the
addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z
state when either CE or OE is HIGH or WE is LOW.
Package options for the P3C1256 include 28-pin 300 mil
DIP and SOJ packages.
A
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CE
WE
A
11
OE
I/0
2
I/0
3
I/0
8
I/0
7
I/0
6
I/0
5
I/0
4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/0
1
A14
A13
A12
VCC
DIP (P5), SOJ (J5)
TOP VIEW
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134
P3C1256
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient) Supply Voltage
3.0V ≤ VCC ≤ 3.6V
Industrial (-40°C to 85°C) 3.0 ≤ VCC ≤ 3.6V
Commercial (0°C to 70°C)
VCC = 3.6V, I
OUT
= 0 mA
CE = V
CC
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
SB
I
SB1
Output High Voltage
(I/O0 - I/O7)
Output Low Voltage
(I/O0 - I/O8)
Input High Voltage
Input Low Voltage
VCC Current
CMOS Standby Current
VCC Current
TTL Standby Current
Output Leakage Current
Input Leakage Current
IOH = –4mA, VCC = 3.0V
IOL = 8 mA
IOL = 10 mA
VCC = 3.6V, I
OUT
= 0 mA
CE = V
CC
GND ≤ V
OUT
≤ V
CC
CE = V
CC
GND ≤ VIN ≤ V
CC
Test Conditions Min
Max
Unit
2.4
2.2
-0.5
V
V
V
V
V
µA
µA
mA
mA
0.4
0.5
VCC + 0.3
0.8
20
3
-5
-5
+5
+5
MAXIMUM RATINGS
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress
ratings only . Functional operation of the device is not implied at these or any other conditions in excess of those
given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can
adversely affect device reliability.
Symbol Parameter
Min Max
Unit
V
CC
Supply Voltage with Respect to GND -0.5 7.0 V
V
TERM
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
VCC + 0.5 V
T
A
Operating Ambient T emperature -40 85 °C
S
TG
-55 125 °C
I
OUT
Output Current into Low Outputs 25 mA
I
LAT
Latch-up Current
>200
mA
Storage Temperature
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135
P3C1256
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
CAPACITANCES
(VCC = 5.0V, TA = 25°C, f = 1.0 MHz)
Symbol
Parameter Test Conditions Max Unit
C
IN
C
OUT
Input Capacitance
Output Capacitance
VIN = 0V
V
OUT
= 0V
10
10
pF
pF
Symbol Parameter
Min
Unit
t
RC
ns
t
AA
Address Access Time
t
AC
Chip Enable Access
Time
t
OH
Output Hold from
Address Change
ns
t
LZ
Chip Enable to
Output in Low Z
ns
t
HZ
Chip Disable to
Output in High Z
ns
t
OE
Output Enable Low
to Data Valid
ns
t
OLZ
Output Enable Low
to Low Z
ns
t
OHZ
Output Enable High
to High Z
t
PU
Chip Enable to
Power Up Time
ns
t
PD
Chip Disable to
Power Down Time
ns
Read Cycle Time
2
2
0
-12
ns
ns
ns
-25-20-15
MaxMinMax
25
25
25
2
2
10
12
0
10
0
20
Min
20
20
20
2
2
9
11
0
9
0
20
MaxMinMax
15
15
15
2
2
8
9
0
7
0
15
12
12
12
7
7
0
6
12
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE, and WE ≤ V
IL
(max), OE is high. Switching inputs are 0V
and 3V.
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter Unit
I
CC
Dynamic Operating Current
Commercial
Industrial
mA
mA
Temperature
Range
-12
110
N/A
-15
100
115
-20
95
110
-25
90
105
Test
Conditions
*
*
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136
P3C1256
Notes:
1. WE is HIGH for READ cycle.
2. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with CE
1
transition
LOW .
4. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
READ CYCLE NO. 1 (
OEOE
OEOE
OE CONTROLLED)
(1)
OLZ
ADDRESS
OE
t
RC
DATA OUT
(5)
t
OH
CE
t
t
HZ
t
OHZ
t
(4)
(4)
(4)
(4)
t
OE
t
AA
AC
t
AC
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (
CECE
CECE
CE CONTROLLED)
t
ADDRESS
DATA OUT
AA
t
t
OH
DATA VALIDPREVIOUS DATA VALID
(5)
RC
t
AC
CE
DATA OUT
t
RC
t
LZ
(8)
DATA VALID
I
CC
I
SB
t
PU
HIGH IMPEDANCE
t
PD
t
HZ
VCC SUPPLY
CURRENT
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137
P3C1256
AC CHARACTERISTICS—WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Notes:
6. CE1 and WE must be LOW for WRITE cycle.
7. OE is LOW for this WRITE cycle to show tWZ and tOW.
8. If CE1 goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first
transitioning address.
ADDRESS
CE
t
WC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT DATA UNDEFINED
(9)
(4)
t
CW
t
AW
t
WP
t
DW
t
AH
t
DH
t
OW
t
AS
t
WZ
(4,7)
(7)
Symbol Parameter
Min
Unit
t
WC
ns
t
CW
Chip Enable Time to
End of Write
t
AW
Address Valid to
End of Write
t
AS
Address Set-up
Time
ns
t
WP
Write Pulse Width ns
t
AH
Address Hold Time
Data Valid to End of
Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
Write Cycle Time
0
9
-12
ns
ns
-25-20-15
MaxMinMax
25
0
18
Min
20
0
15
MaxMinMax
15
0
11
12
ns
t
DW
ns
t
DH
00 00ns
t
WZ
781011ns
t
OW
33 33ns
WRITE CYCLE NO. 1 (
WEWE
WEWE
WE CONTROLLED)
(6)
10
10
0
8
12 15 18
12
15
18
0
10
0
12
0
15
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138
P3C1256
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CECE
CECE
CE CONTROLLED)
(6)
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns
Input Timing Reference Level 1.5V
Output Timing Reference Level 1.5V
Output Load See Figures 1 and 2
TRUTH TABLE
Figure 1. Output Load Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P3C1256, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with D
OUT
to match 166Ω (Thevenin Resistance).
t
DW
WE
ADDRESS
CE
DATA OUT
(6)
DATA IN
t
WC
DATA VALID
HIGH IMPEDANCE
(9)
t
AS
t
CW
t
AW
t
WP
t
DH
t
AH
Mode
Standby
Standby
D
OUT
Disabled
Read
Write
CECE
CECE
CE
H
X
L
L
L
OEOE
OEOE
OE
X
X
H
L
X
WEWE
WEWE
WE
X
X
H
H
L
I/OI/O
I/OI/O
I/O
High Z
High Z
High Z
High Z
D
OUT
Power
Standby
Standby
Active
Active
Active
D
OUT
350Ω
320Ω
+3.3V
30pF* (5pF* for tHZ, tLZ, t
OHZ
,
t
OLZ
, tWZ and tOW)
30pF* (5pF* for tHZ, tLZ, t
OHZ
,
t
OLZ
, tWZ and TOW)
D
OUT
167.2 Ω=R
TH
VTH = 1.72V
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139
P3C1256
DATA RETENTION
LOW VCC DATA RETENTION WAVEFORM (1) (
CECE
CECE
CE
1
CONTROLLED)
Symbol Parameter Test Conditions
Unit
MaxMin
V
DR
I
CCDR
(1)
VCC for Data Retention
Data Retention Current
CE ≥ VCC -0.2V, CE2 ≤ 0.2V
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
2.0 3.6
V
VDR = 2.0V 600
µA
t
R
Operating Recovery Time
Chip Deselect to Data
Retention Time
See Retention Waveform
t
RC
(2)
0
ns
ns
t
CDR
1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 ≤ 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V
2. tRC = Read Cycle Time
CE
2
4.5V
t
CDR
Data Retention Mode
V
DR
CE2 ≤ 0.2V
2.2V
V
CC
4.5V
t
R
V
IL
V
IL
CE
4.5V
t
CDR
Data Retention Mode
V
DR
CE ≥ VDR -0.2V2.2V
V
CC
4.5V
t
R
2.2V
LOW VCC DATA RETENTION WAVEFORM (2) (CE2 CONTROLLED)
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140
P3C1256
SELECTION GUIDE
The P3C1256 is available in the following temperature, speed and package options.
Temperature
Range
Commercial
Industrial
25
-25PC
-25JC
-25PI
-25JI
20
-20PC
-20JC
-20PI
-20JI
15
-15PC
-15JC
-15PI
-15JI
12
-12PC
-12JC
N/A
N/A
Speed
Package
Plastic DIP
Plastic SOJ
Plastic DIP
Plastic SOJ
N/A = Not Available
ORDERING INFORMATION
Performance Semiconductor's part numbering scheme is as follows:
TEMPERATURE RANGE SUFFIX
Temperature
Range Suffix
C Commercial Temperature Range,
0°C to +70°C.
I Industrial Temperature Range,
–40˚C to +85˚C.
PACKAGE SUFFIX
Package
Suffix
P Plastic DIP, 300 mil wide standard
J Plastic SOJ, 300 mil wide standard
Description
Description
1256P3C ss p
t
Temperature Range
Package Code
Static RAM Prefix (3.3 Volts)
Speed (Access/Cycle Time)
Device Number
ss = Speed (access/cycle time in ns), e.g., 12, 15.
p = Package code, i.e., P, J.
t = Temperature range, i.e. C, I.
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