Page 1
NIKO-SEM
P-Channel Logic Level Enhancement
Mode Field Effect Transistor
P2003EVG
SOP-8
Lead-Free
D
PRODUCT SUMMARY
V
(BR)DSS
-30
R
DS(ON)
20mΩ
I
D
-9A
G
4 :GATE
5,6,7,8 :DRAIN
1,2,3 :SOURCE
S
ABSOLUTE MAXIMUM RATINGS (T
PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS
Drain-Source Voltage VDS -30 V
Gate-Source Voltage VGS ±20 V
= 25 °C Unless Otherwise Noted)
C
Continuous Drain Current
T
= 70 °C
C
Pulsed Drain Current1 I
I
D
-50
DM
-8
A
TC = 25 °C 2.5
TC = 25 °C -9
Power Dissipation
T
= 70 °C
C
Operating Junction & Storage Temperature Range Tj, T
P
D
-55 to 150
stg
1.3
W
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS
Junction-to-Case
Junction-to-Ambient R
1
Pulse width limited by maximum junction temperature.
2
Duty cycle ≤ 1%
ELECTRICAL CHARACTERISTICS (T
= 25 °C, Unless Otherwise Noted)
C
R
θJ
θJA
PARAMETER SYMBOL TEST CONDITIONS
c
25 °C / W
50 °C / W
LIMITS
MIN TYP MAX
UNIT
STATIC
Drain-Source Breakdown Voltage V
Gate Threshold Voltage V
Gate-Body Leakage I
(BR)DSS
GS(th)
V
GSS
V
GS
V
DS
DS
= 0V, ID = -250µA
= VGS, ID = -250µA
-30
-1 -1.5 -3
= 0V, VGS = ±20V ±100 nA
V
VDS = -24V, VGS = 0V -1
Zero Gate Voltage Drain Current I
DSS
µA
VDS = -20V, VGS = 0V, TJ = 125 °C -10
On-State Drain Current1 I
Drain-Source On-State
Resistance
1
Forward Transconductance1 g
V
D(ON)
R
DS(ON)
V
fs
= -5V, VGS = -10V -50 A
DS
VGS = -4.5V, ID = -7A 25 35
V
= -10V, ID = -9A 15 20
GS
= -10V, ID = -9A 24 S
DS
OCT-20-2004
1
mΩ
Page 2
NIKO-SEM
P-Channel Logic Level Enhancement
Mode Field Effect Transistor
DYNAMIC
P2003EVG
SOP-8
Lead-Free
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge2 Q
Gate-Source Charge2 Q
Gate-Drain Charge2 Q
Turn-On Delay Time2 t
Rise Time2 t
Turn-Off Delay Time2 t
Fall Time2 t
1610
iss
V
410
oss
rss
17 24
g
5
gs
gd
5.7
d(on)
r
d(off)
5
f
= 0V, VDS = -15V, f = 1MHz
GS
VDS = 0.5V
V
DS
≅ -1A, VGS = -10V, RGS = 6Ω
I
D
, VGS = -10V,
(BR)DSS
I
= -9A
D
= -15V, RL = 1Ω
200
6
10
18
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current IS -2.1
Pulsed Current3 I
Forward Voltage1 V
1
Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％.
2
Independent of operating temperature.
3
Pulse width limited by maximum junction temperature.
-4
SM
I
SD
= -1A, VGS = 0V -1.2 V
F
REMARK: THE PRODUCT MARKED WITH “P2003EVG”, DATE CODE or LOT #
pF
nC
nS
A
Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.
OCT-20-2004
2
Page 3
NIKO-SEM
P-Channel Logic Level Enhancement
Mode Field Effect Transistor
P2003EVG
SOP-8
Lead-Free
Body Diode Forward Voltage Variation with Source Current and Temperature
100
V = 0V
GS
10
T = 125° C
A
25° C
-55° C
-V - Body Diode Forward Voltage(V)
SD
0.6
0.8 1.0
1.2
-Is - Reverse Drain Current(A)
0.1
0.01
0.001
0.0001
1
0.2 0.4
0
OCT-20-2004
3
Page 4
NIKO-SEM
P-Channel Logic Level Enhancement
Mode Field Effect Transistor
P2003EVG
SOP-8
Lead-Free
4
OCT-20-2004
Page 5
NIKO-SEM
Dimension
A 4.8 4.9 5.0 H 0.5 0.715 0.83
P-Channel Logic Level Enhancement
Mode Field Effect Transistor
SOIC-8(D) MECHANICAL DATA
mm mm
Dimension
Min. Typ. Max.
P2003EVG
SOP-8
Lead-Free
Min. Typ. Max.
B
C
D
E
F
G
3.8 3.9 4.0 I 0.18 0.254 0.25
5.8 6.0 6.2 J 0.22
0.38 0.445 0.51 K 0° 4° 8°
1.27 L
1.35 1.55 1.75 M
0.1
0.175 0.25 N
5
OCT-20-2004
Page 6
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