Datasheet OP97FS-REEL7, OP97FS-REEL, OP97FS, OP97EP, OP97ARC-883 Datasheet (Analog Devices)

Low-Power, High-Precision

a

FEATURES
Low Supply Current: 600 ␮A Max
OP07 Type Performance

Offset Voltage: 20 ␮V Max
Offset Voltage Drift: 0.6 ␮V/ⴗ C Max

Very Low Bias Current

25ⴗC: 100 pA Max

–55ⴗC to +125ⴗC: 250 pA Max
High Common-Mode Rejection: 114 dB Min
Extended Industrial Temperature Range: –40ⴗC to +85ⴗC
Available In Die Form

GENERAL DESCRIPTION

The OP97 is a low power alternative to the industry-standard
OP07 precision amplifier. The OP97 maintains the standards of
performance set by the OP07 while utilizing only 600 µA supply
current, less than 1/6 that of an OP07. Offset voltage is an
ultralow 25 µV, and drift over temperature is below 0.6 µV/°C.
External offset trimming is not required in the majority of circuits.

Improvements have been made over OP07 specifications in
several areas. Notable is bias current, which remains below
250 pA over the full military temperature range. The OP97 is
ideal for use in precision long-term integrators or sample-and­hold circuits that must operate at elevated temperatures.

Common-mode rejection and power supply rejection are also
improved with the OP97, at 114 dB minimum over wider
ranges of common-mode or supply voltage. Outstanding
PSR, a supply range specified from ±2.25 V to ±20 V and the
OP97’s minimal power requirements combine to make the
OP97 a preferred device for portable and battery-powered
instruments.

The OP97 conforms to the OP07 pinout, with the null potenti­ometer connected between Pins 1 and 8 with the wiper to V+.
The OP97 will upgrade circuit designs using 725, OP05, OP07,
OP12, and 1012 type amplifiers. It may replace 741-type ampli­fiers in circuits without nulling or where the nulling circuitry has
been removed.

Operational Amplifier

OP97

PIN CONNECTIONS

Epoxy Mini-DIP (P Suffix)

8-Pin Cerdip

(Z Suffix)

8-Pin SO (S Suffix)

NULL

–IN

+IN

1

OP97

2

3

V–

4

8

7

6

5

NULL

V+

OUT

OVER
COMP

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

OP97–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Min Typ Max Unit

Input Offset Voltage V

OS

(@ VS = ⴞ15 V, V

= 0 V, TA = 25ⴗC, unless otherwise noted.)

CM

OP97A/E OP97F

10 25 30 75 µV

Long-Term Offset

Voltage Stability ∆V

Input Offset Current I
Input Bias Current I
Input Noise Voltage e
Input Noise Voltage Density e

Input Noise Current Density i
Large-Signal Voltage Gain A
Common-Mode Rejection CMR V
Power-Supply Rejection PSR V

/Time 0.3 0.3 µV/Month

OS

OS

B

p-p 0.1 Hz to 10 Hz 0.5 0.5 µV p-p

n

n

n

VO

fO = 10 Hz

= 1000 Hz

f

O

fO = 10 Hz 20 20 fA/√Hz
VO = ±10 V; RL = 2 kΩ 300 2000 200 2000 V/mV

CM

= ±2 V to ±20 V 114 132 110 132 dB

S

2

3

= ±13.5 V 114 132 110 132 dB

30 100 30 150 pA
±30 ± 100 ±30 ± 150 pA

17 30 17 30 nV/√Hz
14 22 14 22 nV/√Hz

Input Voltage Range IVR (Note 1) ±13.5 ±14.0 ±13.5 ±14.0 V
Output Voltage Swing V

O

RL = 10 kΩ±13 ± 14 ± 13 ±14 V

Slew Rate SR 0.1 0.2 0.1 0.2 V/µs
Differential Input Resistance R

IN

Closed-Loop Bandwidth BW A
Supply Current I
Supply Voltage V

NOTES

1

Guaranteed by CMR test.

2

10 Hz noise voltage density is sample tested. Devices 100% tested for noise are available on request.

3

Sample tested.

4

Guaranteed by design.

Specifications subject to change without notice.

SY

S

(Note 4) 30 30 MΩ

= 1 0.4 0.9 0.4 0.9 MHz

VCL

380 600 380 600 µA

Operating Range ±2 ±15 ± 20 ±2 ± 15 ± 20 V

(@ VS = ⴞ15 V, VCM = 0 V, –40ⴗC ≤ TA ≤ +85ⴗC for the OP97E/F and –55ⴗC ≤ TA ≤ +125ⴗC

ELECTRICAL CHARACTERISTICS

for the OP97A, unless otherwise noted.)

OP97A/E OP97F

Parameter Symbol Conditions Min Typ Max Min Typ Max Unit

Input Offset Voltage VOS 25 60 60 200 µV
Average Temperature TCV

Coefficient of V

Input Offset Current I

OS

OS

Average Temperature TCI

Coefficient of I

Input Bias Current I

OS

B

OS

OS

S-Package 0.2 0.6 0.3 2.0 µV/°C

0.3

60 250 80 750 pA

0.4 2.5 0.6 7.5 pA/°C

±60 ± 250 ± 80 ± 750 pA

Average Temperature

Coefficient of I

B

Large Signal Voltage Gain A

TCI

VO

B

Common-Mode Rejection CMR V
Power Supply Rejection PSR V

VO = 10 V; RL = 2 kΩ 200 1000 150 1000 V/mV

= ±13.5 V 108 128 108 128 dB

CM

= ±2.5 V to ±20 V 108 126 108 128 dB

S

0.4 2.5 0.6 7.5 pA/°C

Input Voltage Range IVR (Note 1) ±13.5 ±14.0 ±13.5 ± 14.0 V
Output Voltage Swing V

O

RL = 10 kΩ±13 ± 14 ±13 ± 14 V

Slew Rate SR 0.05 0.15 0.05 0.15 V/µs
Supply Current I
Supply Voltage V

NOTES

1

Guaranteed by CMR test.

Specifications subject to change without notice.

SY

S

Operating Range ±2.5 ±15 ± 20 ± 2.5 ±15 ± 20 V

400 800 400 800 µA

–2–

REV. D

OP97

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V

Input Voltage
Differential Input Voltage
Differential Input Current

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V

3

. . . . . . . . . . . . . . . . . . . . . . ±1 V

3

. . . . . . . . . . . . . . . . . . . . ±10 mA

1

Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Operating Temperature Range

OP97A (Z) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

OP97E, F (P, Z, S) . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . 300°C

Package Type ␪

4

JA

␪

JC

Unit

8-Lead Hermetic DIP (Z) 148 16 °C/W
8-Lead Plastic DIP (P) 103 43 °C/W
8-Lead SO (S) 158 43 °C/W

NOTES

1

Absolute maximum ratings apply to both DICE and packaged parts, unless

otherwise noted.

2

For supply voltages less than ± 20 V, the absolute maximum input voltage is equal

to the supply voltage.

3

The OP97’s inputs are protected by back-to-back diodes. Current-limiting resis-

tors are not used in order to achieve low noise. Differential input voltages greater
than 1 V will cause excessive current to flow through the input protection diodes
unless limiting resistance is used.

4

θJA is specified for worst case mounting conditions, i.e., θJA is specified for device

in socket for TO, cerdip, and P-DIP packages; θJA is specified for device soldered
to printed circuit board for SO package.

ORDERING GUIDE

Temperature Package

Model Range Option

OP97AZ
OP97ARC/883
OP97EJ
OP97EZ
OP97EP –40°C to +85°C 8-Lead Plastic DIP
OP97FZ

3

3

3

3

–55°C to +125°C 8-Lead Cerdip

2, 3

–55°C to +125°C 20-Contact LCC
–40°C to +85°C TO-99
–40°C to +85°C 8-Lead Cerdip

–40°C to +85°C 8-Lead Cerdip

1

OP97FP –40°C to +85°C 8-Lead Plastic DIP
OP97FS –40°C to +85°C 8-Lead SOIC
OP97FS-REEL –40°C to +85°C 8-Lead SOIC
OP97FS-REEL7 –40°C to +85°C 8-Lead SOIC

NOTES

1

For outline information see Package Information section.

2

For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for /883 data sheet.

3

Not for new designs; obsolete April 2002.

For Military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp

SMD Part Number ADI Equivalent

59628954401PA OP97AZMDA
59628954401GA

*

Not for new designs; obsolete April 2002.

*

OP97AJMDA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP97 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. D

–3–

OP97

–Typical Performance Characteristics

400

1894 UNITS

300

200

NUMBER OF UNITS

100

0

–40

–20 0 20 40

INPUT OFFSET VOLTAGE – ␮V

VS = 15V
T

= 25 C

A

V

= 0V

CM

TPC 1. Typical Distribution of Input
Offset Voltage

60

TA = 25 C
V

= 0V

CM

40

20

0

–20

INPUT CURRENT - pA

–40

–60

–75

–25 0 25 50–50 75

TEMPERATURE –

C

IB–

IB+

I

OS

100 125

400

1920 UNITS

300

200

NUMBER OF UNITS

100

0

–100

–50 0 50 100

INPUT BIAS CURRENT – pA

VS = 15V
T

= 25 C

A

V

= 0V

CM

TPC 2. Typical Distribution of Input
Bias Current

60

TA = 25 C
V

= 15V

S

40

20

0

–20

INPUT CURRENT - pA

–40

–60

–15

COMMON-MODE VOLTAGE – Volts

–50 510–10 15

IB–

IB+

I

OS

500

1894 UNITS

400

300

200

NUMBER OF UNITS

100

0

–60

–40 60

INPUT OFFSET CURRENT – pA

–20 0 20 40

VS = 15V
T

= 25 C

A

V

= 0V

CM

TPC 3. Typical Distribution of Input
Offset Current

ⴞ5

TA = 25 C
V

= 15V

S

V

= 0V

CM

ⴞ4

ⴞ3

ⴞ2

J PACKAGES

ⴞ1

DEVIATION FROM FINAL VALUE – ␮V

0

0

Z, P PACKAGES

234 5

1

TIME AFTER POWER APPLIED – Minutes

TPC 4. Input Bias, Offset Current
vs. Temperature

1000

BALANCED OR UNBALANCED
V

= 15V

S

V

= 0V

CM

100

–55 C TA +125 C

10

TA = 25 C

EFFECTIVE OFFSET VOLTAGE – ␮V

1

3k 10k 30k 100k 1M300k 3M 10M

1k

SOURCE RESISTANCE – ⍀

TPC 7. Effective Offset Voltage vs.
Source Resistance

TPC 5. Input Bias, Offset Current
vs. Common-Mode Voltage

100

BALANCED OR UNBALANCED
V

= 15V

S

V

= 0V

CM

10

1

0.1

EFFECTIVE OFFSET VOLTAGE DRIFT – ␮V/ C

10k 100k 1M 10M

1k

SOURCE RESISTANCE – ⍀

TPC 8. Effective TCVOS vs. Source
Resistance

100M

TPC 6. Input Offset Voltage
Warm-Up Drift

20

15

10

5

VS = 15V

0

OUTPUT SHORTED TO GROUND

–5

–10

SHORT CIRCUIT CURRENT - mA

–15

–20

0

TIME FROM OUTPUT SHORT – Minutes

TA = –55 C

TA = +25 C

TA = +125 C

TA = +125 C

TA = +25 C

TA = –55 C

123

TPC 9. Short Circuit Current vs.
Time, Temperature

–4–

REV. D

OP97

450

NO LOAD

425

400

375

350

SUPPLY CURRENT – ␮A

325

300

ⴞ5

0

SUPPLY VOLTAGE – V

TA = +125 C

TA = +25 C

TA = –55 C

ⴞ10 ⴞ15 ⴞ20

TPC 10. Supply Current vs. Supply
Voltage

10000

VS = 15V
V

= 10V

O

TA = –55 C

TA = +25 C

1000

OPEN-LOOP GAIN – V/mV

100

1

2 5 10 20

LOAD RESISTANCE – k⍀

TA = +125 C

COMMON-MODE REJECTION – dB

140

120

100

80

60

40

20

0

1

10 100 1k 10k

FREQUENCY – Hz

TA = 25 C
V

= 15V

S

V

= 10V

CM

100k 1M

TPC 11. Common-Mode Rejection
vs. Frequency

1000

TA = 25 C
V

= 2V TO 20V

S

100

CURRENT NOISE

VOLTAGE NOISE

10

1/f CORNER

2.5Hz

1/f CORNER

VOLTAGE NOISE DENSITY – nV/ Hz

1

1k

10k 100k 1M 10M 100M

FREQUENCY – Hz

120Hz

1000

100

10

1

POWER-SUPPLY REJECTION – dB

140

120

100

80

60

40

20

0.1

+PSR

1 100k

10 100 1k 10k

FREQUENCY – Hz

TA = 25 C
V

= 15V

S

⌬VS = 10V p–p

–PSR

TPC 12. Power-Supply Rejection
vs. Frequency

10

TA = 25 C
V

= 2V TO 20V

S

10Hz

1

R

R

R

= 2R

0.1

1kHz

TOTAL NOISE DENSITY – ␮V/ Hz

CURRENT NOISE DENSITY – fV/ Hz

0.01

2

10

10

S

10Hz

RESISTOR NOISE

3104105106107108

SOURCE RESISTANCE – ⍀

1M

1kHz

TPC 13. Open-Loop Gain vs. Load

Resistance

RL = 10k⍀
VS = 15V
V

= 0V

CM

T

= +125 C

A

TA = +25 C

DIFFERENTIAL INPUT VOLTAGE – 10␮V/DIV

–15 –50510

–10 15

OUTPUT VOLTAGE – V

TA = –55 C

Figure 16. Open-Loop Gain Linearity

TPC 14. Noise Density vs.
Frequency

35

TA = 25 C

= 15V

V

S

30

A

= +1

VCL

1% THD

25

= 1kHz

f

O

20

15

10

OUTPUT SWING – V p-p

5

1

10

LOAD RESISTANCE – ⍀

TPC 17. Maximum Output Swing
vs. Load Resistance

TPC 15. Total Noise Density vs.
Source Resistance

35

30

25

20

15

10

OUTPUT SWING – V p-p

5

10k1k100

1

FREQUENCY – Hz

10k

TA = 25 C

= 15V

V

S

= 1

A

VCL

1% THD

= 10k⍀

R

l

100k1k100

TPC 18. Maximum Output Swing
vs. Frequency

REV. D

–5–

OP97

FREQUENCY – Hz

OUTPUT IMPEDANCE – ⍀

0.001
10 100 1k 10k

TA = 25 C
V

S

= 15V

1

A

VCL

= 1000

100k

A

VCL

= 1

0.01

0.1

1

10

100

1000

80

GAIN

60

PHASE

40

OPEN-LOOP GAIN – dB

20

–20

–40

–60

TA = +125 C

= –55 C

T

0

100

A

VS = 15V

VS = 15V

= 20pF

C

L

= 20pF

C

L

R

= 1M⍀

L

R

= 1M⍀

L

100pF OVERCOMPENSATION

100pF OVERCOMPENSATION

FREQUENCY – Hz

TA = –55 C

= +125 C

T

A

10k 1M

90

135

180

225

10M1k 100k

TPC 19. Open-Loop Gain, Phase vs.
Frequency (C

80

GAIN

60

PHASE

40

20

TA = –55 C
T

0

–20

OPEN-LOOP GAIN – dB

VS = 15V

= 20pF

C

L

–40

R

= 1M⍀

L

100pF OVERCOMPENSATION

–60

100

= 0 pF)

OC

= +125 C

A

10k 1M

FREQUENCY – Hz

TA = +125 C

= –55 C

T

A

90

135

180

225

10M1k 100k

10

TA = 25 C

= 15V

V

S

R

= 10k⍀

L

1

1% THD

= 3V RMS

V

OUT

0.1

A

= 100

VCL

A

= 10

VCL

10 10k1k100

FREQUENCY – Hz

A

VCL

PHASE SHIFT – Degrees

0.0001

THD + N – %

0.001

0.01

TPC 20. Total Harmonic Distortion
Plus Noise vs. Frequency

1

TA = +125 C

TA = –55 C

0.1

0.01

SLEW RATE – V/␮s

PHASE SHIFT – Degrees

0.001
1

10 100 10000

OVERCOMPENSATION CAPACITOR – pF

1000

= 1

Rl = 10k⍀
V

= 15V

S

C

= 100pF

L

70

TA = 25 C

= 15V

V

S

60

A

= +1

VCL

V

= 100mV p-p

OUT

50

= 0pF

C

OC

40

30

OVERSHOOT – %

20

10

0

10

LOAD CAPACITANCE – pF

+EDGE

–EDGE

1000100

10000

TPC 21. Small Signal Overshoot vs.
Capacitive Load

1000

TA = –55 C

TA = +125 C

100

10

VS = 15V

GAIN-BANDWIDTH – kHz

C

= 20pF

L

R

= 1M⍀

L

A

= 100

V

1

1

10 100 10000

OVERCOMPENSATION CAPACITOR – pF

1000

TPC 22. Open-Loop Gain, Phase vs.
Frequency (C

80

60

40

20

TA = –55 C

0

T

A

–20

OPEN-LOOP GAIN – dB

VS = 15V

= 20pF

C

L

–40

R

= 1M⍀

L

100pF OVERCOMPENSATION

–60

100

= 100 pF)

OC

GAIN

= +125 C

10k 1M

FREQUENCY – Hz

PHASE

TPC 25. Open-Loop Gain, Phase vs.
Frequency (C

= 1000 pF)

OC

TA = –55 C

= +25 C

T

A

= +125 C

T

A

TPC 23. Slew Rate vs. Over­compensation

80

60

90

135

180

225

10M1k 100k

OPEN-LOOP GAIN – dB

PHASE SHIFT – Degrees

40

20

GAIN

0

TA = +125 C

T

–20

VS = 15V

= 20pF

C

L

–40

R

= 1M⍀

L

100pF OVERCOMPENSATION

–60

100

= –55 C

A

FREQUENCY – Hz

PHASE

10k 1M

TA = +125 C

= +25 C

T

A

= +125 C

T

A

90

135

180

225

10M1k 100k

TPC 26. Open-Loop Gain, Phase vs.
Frequency (C

= 10,000 pF)

OC

–6–

TPC 24. Gain Bandwidth Product vs.
Overcompensation

PHASE SHIFT – Degrees

TPC 27. Closed-Loop Output Resis­tance vs. Frequency

REV. D

OP97

APPLICATIONS INFORMATION

The OP97 is a low power alternative to the industry standard
precision op amp, the OP07. The OP97 may be substituted
directly into OP07, OP77, 725, 112/312, and 1012 sockets with
improved performance and/or less power dissipation, and may
be inserted into sockets conforming to the 741 pinout if nulling
circuitry is not used. Generally, nulling circuitry used with earlier
generation amplifiers is rendered superfluous by the OP97’s
extremely low offset voltage, and may be removed without com­promising circuit performance.

Extremely low bias current over the full military temperature
range makes the OP97 attractive for use in sample-and-hold
amplifiers, peak detectors, and log amplifiers that must operate
over a wide temperature range. Balancing input resistances is
not necessary with the OP97. Offset voltage and TCV

OS

are
degraded only minimally by high source resistance, even when
unbalanced.

The input pins of the OP97 are protected against large differen­tial voltage by back-to-back diodes. Current-limiting resistors
are not used so that low noise performance is maintained. If
differential voltages above ±1 V are expected at the inputs,
series resistors must be used to limit the current flow to a
maximum of 10 mA. Common-mode voltages at the inputs are
not restricted, and may vary over the full range of the supply
voltages used.

The OP97 requires very little operating headroom about the
supply rails, and is specified for operation with supplies as low

as ±2 V. Typically, the common-mode range extends to within
one volt of either rail. The output typically swings to within one
volt of the rails when using a 10 kΩ load.

Offset nulling is achieved utilizing the same circuitry as an
OP07. A potentiometer between 5 kΩ and 100 kΩ is connected
between pins 1 and 8 with the wiper connected to the positive
supply. The trim range is between 300 µV and 850 µV, depend-
ing upon the internal trimming of the device.

AC PERFORMANCE

The OP97’s ac characteristics are highly stable over its full
operating temperature range. Unity-gain small-signal response
is shown in Figure 2. Extremely tolerant of capacitive loading
on the output, the OP97 displays excellent response even with
1000 pF loads (Figure 3). In large-signal applications, the
input protection diodes effectively short the input to the output
during the transients if the amplifier is connected in the usual
unity-gain configuration. The output enters short-circuit current
limit, with the flow going through the protection diodes. Improved
large-signal transient response is obtained by using a feedback
resistor between the output and the inverting input. Figure 4
shows the large-signal response of the OP97 in unity gain with a
10 kΩ feedback resistor. The unity gain follower circuit is shown
in Figure 5.

The overcompensation pin may be used to increase the phase
margin of the OP97, or to decrease gain-bandwidth product at
gains greater than 10.

+V

R

OP97

–V

POT

C

OC

= 5k⍀ TO 100k

⍀

Figure 1. Optional Input Offset Voltage Nulling
and Overcompensation Circuits

Figure 2. Small-Signal Transient Response
(C

LOAD

= 100 pF, A

VCL

= 1)

Figure 3. Small-Signal Transient Response
(C

LOAD

= 1000 pF, A

VCL

= 1)

Figure 4. Large-Signal Transient Response (A

VCL

= 1)

REV. D

–7–

OP97

V

10k⍀

2

OP97

V

3

IN

6

V

OUT

Figure 5. Unity-Gain Follower

Figure 6. Small-Signal Transient Response with Overcom­pensation (C

= 1000 pF, A

LOAD

= 1, COC = 220 pF)

VCL

GUARDING AND SHIELDING

To maintain the extremely high input impedances of the OP97,
care must be taken in circuit board layout and manufacturing.
Board surfaces must be kept scrupulously clean and free of moisture.
Conformal coating is recommended to provide a humidity barrier.
Even a clean PC board can have 100 pA of leakage currents between
adjacent traces, so that guard rings should be used around the
inputs. Guard traces are operated at a voltage close to that on the
inputs, so that leakage currents become minimal. In nonin­verting applications, the guard ring should be connected to the
common-mode voltage at the inverting input (Pin 2). In inverting
applications, both inputs remain at ground, so that the guard trace
should be grounded. Guard traces should be made on both sides
of the circuit board.

FB

PM7548

30pF

I

2

O

6

OP97

3

I

O

V

OUT

R

DIGITAL

INPUTS

Figure 7. DAC Output Amplifier

R1

10k⍀

1

R2

10k⍀R310k⍀

10k⍀

R5

10k⍀

+15V

2

3

R4

OP97

–15V

7

6

4

I

L

R

L

V

OUT

Figure 8. Current Monitor

High impedance circuitry is extremely susceptible to RF pickup,
line frequency hum, and radiated noise from switching power
supplies. Enclosing sensitive analog sections within grounded
shields is generally necessary to prevent excessive noise pickup.
Twisted-pair cable will aid in rejection of line frequency hum.

The OP97 is an excellent choice as an output amplifier for higher
resolution CMOS DACs. Its tightly trimmed offset voltage and
minimal bias current result in virtually no degradation of linear­ity, even over wide temperature ranges.

Figure 8 shows a versatile monitor circuit that can typically
sense current at any point between the ±15 V supplies. This
makes it ideal for sensing current in applications such as full
bridge drivers where bidirectional current is associated with large
common-mode voltage changes. The 114 dB CMRR of the OP97
makes the amplifier’s contribution to common-mode error
negligible, leaving only the error due to the resistor ratio
inequality. Ideally, R2/R4 = R3/R5. This is best trimmed via R4

UNITY-GAIN FOLLOWER

2

OP97

3

INVERTING AMPLIFIER

2

OP97

3

6

6

NONINVERTING AMPLIFIER

2

OP97

3

TO-99

BOTTOM VIEW

1

8

6

MINI-DIP

BOTTOM VIEW

18

Figure 9. Guard Ring Layout and Connections

–8–

REV. D

The digitally programmable gain amplifier shown in Figure 10

OP44

V

OUT

2

3

6

OP97

2

3

6

R2

20k⍀

5

10k⍀

1␮F

R1

2k⍀

V

IN

0.1␮F

10k⍀

5pF

R2
R1

AV =

has 12-bit gain resolution with 10-bit gain linearity over the
range of –1 to –1024. The low bias current of the OP97 main­tains this linearity, while C1 limits the noise voltage bandwidth
allowing accurate measurement down to microvolt levels.

DIGITAL IN GAIN (Av)

4095 –1.00024
2048 –2
1024 –4
512 –8
256 –16
128 –32
64 –64
32 –128
16 –256
8 –512
4 –1024
2 –2048
1 –4096
0 OPEN LOOP

Many high-speed amplifiers suffer from less-than-perfect low­frequency performance. A combination amplifier consisting of a
high precision, slow device like the OP97 and a faster device
such as the OP44 results in uniformly accurate performance
from dc to the high frequency limit of the OP44, which has a
gain-bandwidth product of 23 MHz. The circuit shown in Figure 11
accomplishes this, with the OP44 providing high frequency
amplification and the OP97 operating on low frequency signals
and providing offset correction. Offset voltage and drift of the
circuit are controlled by the OP97.

OP97

Figure 11. Combination High-Speed, Precision Amplifier

Figure 12. Combination Amplifier Transient Response

.

+15V

V

IN

ⴞ2.5mV TO ⴞ10V
RANGE DEPENDING
ON GAIN SETTING

Figure 10. Precision Programmable Gain Amplifier

REV. D

1

2

3

I

OUT 1

I

OUT 2

18

R

FB

PM7541

2

OP97

3

+15V

–15V

16

V

REF

6

0.1␮F

17

C1

220pF

0.1␮F

V

OUT

0.1␮F

–9–

OP97

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

PIN 1

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

8-Lead Plastic DIP

0.430 (10.92)

0.348 (8.84)

8

0.100 (2.54)

5

0.280 (7.11)

14

BSC

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

(N-8)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.1574 (4.00)

0.1497 (3.80)

0.195 (4.95)

0.115 (2.93)

0.1968 (5.00)

0.1890 (4.80)

85

41

8-Pin SOIC

(SO-8)

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

8-Pin Hermetic DIP

0.005 (0.13)
MIN

85

1

0.100 (2.54) BSC

0.405 (10.29) MAX

0.023 (0.58)

0.014 (0.36)

0.055 (1.4)
MAX

0.310 (7.87)

0.220 (5.59)

4

0.060 (1.52)

0.015 (0.38)

0.070 (1.78)

0.030 (0.76)

(Q-8)

0.150
(3.81)
MIN

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

15°

0°

0.015 (0.38)

0.008 (0.20)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

SEATING

PLANE

0.0500 (1.27)
BSC

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

8ⴗ

0.0500 (1.27)

0ⴗ

0.0160 (0.41)

ⴛ 45ⴗ

–10–

REV. D

OP97

Revision History

Location Page

Data Sheet changed from REV. C to REV. D.

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

REV. D

–11–

C00299–0–1/02(D)

–12–

PRINTED IN U.S.A.