Page 1
Next Generation OP07 Ultralow
V
V
FEATURES
Outstanding gain linearity
Ultrahigh gain, 5000 V/mV min
Low V
Excellent TCV
High PSRR, 3 μV/V max
Low power consumption, 60 mW max
Fits OP07, 725,108A/308A, 741 sockets
Available in die form
over temperature, 55 μV max
OS
, 0.3 μV/°C max
OS
Offset Voltage Operational Amplifier
OP77
PIN CONNECTIONS
1
OS
TRIM
–IN
+IN
V–
OP77
2
3
TOP VIEW
4
(Not to S cale)
NC = NO CONNECT
Figure 1. 8-Pin Hermetic
DIP_Q-8 (Z Suffix)
OS
TRIM V+
V
OS
1
OP77
–IN OUT
3
+IN NC
4V– (CASE)
TOP VIEW
(Not to Scale)
NC = NO CONNECT
Figure 2. TO-99
(J Suffix)
TRIM
8
4
8
7
6
5
7
5
VOS TRIM
V+
OUT
NC
62
00320-001
00320-002
GENERAL DESCRIPTION
The OP77 significantly advances the state-of-the-art in
precision op amps. The outstanding gain of 10,000,000 or more
for the OP77 is maintained over the full 10 V output range. This
exceptional gain-linearity eliminates incorrectable system
nonlinearities common in previous monolithic op amps and
provides superior performance in high closed-loop gain
applications. Low initial V
combined with only 50 mW of power consumption, are
significant improvements over previous designs. These
characteristics, plus the exceptional TCV
maximum and the low V
drift and rapid stabilization time,
OS
of 0.3 μV/°C
OS
of 25 μV maximum, eliminates the
OS
need for V
adjustment and increases system accuracy over
OS
temperature.
A PSRR of 3 μV/V (110 dB) and CMRR of 1.0 μV/V maximum
virtually eliminate errors caused by power supply drifts and
common-mode signals. This combination of outstanding
characteristics makes the OP77 ideally suited for high resolution
instrumentation and other tight error budget systems.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002–2010 Analog Devices, Inc. All rights reserved.
Page 2
OP77
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Connections ............................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Electrical Specifications ............................................................... 3
Wafer Test Limits .......................................................................... 4
Typical Electrical Characteristics ............................................... 5
Absolute Maximum Ratings ............................................................ 6
REVISION HISTORY
4/10—Rev. D to Rev. E
Removed Figure 33 and Two Subsequent Paragraphs ............... 12
6/09—Rev. C to Rev. D
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Table 1 ............................................................................ 3
Removed Endnote 1 and Endnote 2 in Table 3 ............................ 4
Changes to Figure 16 ........................................................................ 9
Changes to Figure 31 and Figure 32 ............................................. 12
Changes to Figure 38 ...................................................................... 14
Moved Figure 39 ............................................................................. 14
10/02—Rev. B to Rev. C
Edits to Specifications ...................................................................... 2
Figure 2 Caption Changed ............................................................ 10
Figure 3 Caption Changed ............................................................ 10
Edits to Figure 10 ............................................................................ 11
Updated Outline Dimensions ....................................................... 15
2/02—Rev. A to Rev. B
Remove 8-Lead SO PIN Connection Diagrams ........................... 1
Changes to Absolute Maximum Rating ......................................... 2
Remove OP77B column from Specifications ................................ 2
Remove OP77B column from Electrical Characteristics ........ 3, 5
Remove OP77G column from Wafer Test Limits ......................... 6
Remove OP77G column from Typical Electrical Characteristics6
Thermal Resistance .......................................................................6
ESD Caution...................................................................................6
Typical Performance Characteristics ..............................................7
Test Circuits ..................................................................................... 10
Applications ..................................................................................... 11
Precision Current Sinks ............................................................. 12
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
Rev. E | Page 2 of 16
Page 3
OP77
ELECTRICAL SPECIFICATIONS
@ VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
OP77E OP77F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE VOS 10 25 20 60 μV
LONG-TERM STABILITY1 V
INPUT OFFSET CURRENT IOS 0.3 1.5 0.3 2.8 nA
INPUT BIAS CURRENT IB −0.2 +1.2 +2.0 −0.2 +1.2 +2.8 nA
INPUT NOISE VOLTAGE2 e
INPUT NOISE VOLTAGE DENSITY en fO = 10 Hz 10.3 18.0 10.5 20.0 nV/√Hz
f
f
INPUT NOISE CURRENT2 i
INPUT NOISE CURRENT DENSITY in fO = 10 Hz 0.32 0.80 0.35 0.90 pA√Hz
f
f
INPUT RESISTANCE
Differential Mode3 R
Common Mode R
INPUT VOLTAGE RANGE IVR ±13 ±14 ±13 ±14 V
COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 0.1 1.0 0.1 1.6 μV/V
POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 0.7 3.0 0.7 3.0 μV/V
LARGE-SIGNAL VOLTAGE GAIN AVO RL ≥ 2 kΩ 5000 12,000 2000 6000 V/mV
V
OUTPUT VOLTAGE SWING VO RL ≥ 10 kΩ ±13.5 ±14.0 ±13.5 ±14.0 V
R
R
SLEW RATE2 SR RL ≥ 2 kΩ 0.1 0.3 0.1 0.3 V/μs
CLOSED-LOOP BANDWIDTH2 BW A
OPEN-LOOP OUTPUT RESISTANCE RO 60 60 Ω
POWER CONSUMPTION Pd VS = ±15 V, no load 50 60 50 60 mW
V
OFFSET ADJUSTMENT RANGE Rp = 20 kn ±3 ±3 mV
1
Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in V
2
Sample tested.
3
Guaranteed by design.
during the first 30 operating days are typically 2.5 μV.
OS
/time 0.3 0.4 μV/Mo
OS
0.1 Hz to 10 Hz 0.35 0.6 0.38 0.65 μV
np-p
= 100 Hz2 10.0 13.0 10.2 13.5
O
= 1000 Hz 9.6 11.0 9.8 11.5
O
0.1 Hz to 10 Hz 14 30 15 35 pA
np-p
= 100 Hz2 0.14 0.23 0.15 0.27
O
= 1000 Hz 0.12 0.17 0.13 0.18
O
26 45 18.5 45 MΩ
IN
200 200 GΩ
INCM
= ±10 V
O
≥ 2 kΩ ±12.5 ±13.0 ±12.5 ±13.0
L
≥ 1 kΩ ±12.0 ±12.5 ±12.0 ±12.5
L
+ 1 0.4 0.6 0.4 0.6 MHz
VCL
= ±3 V, no load 3.5 4.5 3.5 4.5
S
p-p
p-p
Rev. E | Page 3 of 16
Page 4
OP77
@ VS = ±15 V, −25°C ≤ TA ≤ +85°C for OP77FJ and OP77E/OP77F, unless otherwise noted.
Table 2.
OP77E OP77F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE VOS 10 45 20 100 μV
AVERAGE INPUT OFFSET VOLTAGE DRIFT1 TCVOS 0.1 0.3 0.2 0.6 μV/°C
INPUT OFFSET CURRENT IOS 0.5 2.2 0.5 4.5 nA
AVERAGE INPUT OFFSET CURRENT DRIFT2 TCI
INPUT BIAS CURRENT IB −0.2 +2.4 +4.0 −0.2 +2.4 +6.0 nA
AVERAGE INPUT BIAS CURRENT DRIFT2 TCIB 8 40 15 60 pA/°C
INPUT VOLTAGE RANGE IVR ±13.0 ±13.5 ±13.0 ±13.5 V
COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 0.1 1.0 0.1 3.0 pV/V
POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 1.0 3.0 1.0 5.0 μV/V
LARGE-SIGNAL VOLTAGE GAIN A
V
OUTPUT VOLTAGE SWING VO RL ≥ 2 kΩ ±12 ±13.0 ±12 ±13.0 V
POWER CONSUMPTION Pd VS = ±15 V, no load 60 75 60 75 mW
1
OP77E: TCVOS is 100% tested on J and Z packages.
2
Guaranteed by end-point limits.
1.5 4.0 1.5 85 pA/°C
OS
R
VO
≥ 2 kΩ 2000 6000 1000 4000 V/mV
L
= ±10 V
O
WAFER TEST LIMITS
@ VS = ±15 V, TA = 25°C, for OP77NBC devices, unless otherwise noted.
Table 3.
Parameter Symbol Conditions OP77NBC Limit Unit
INPUT OFFSET VOLTAGE V
INPUT OFFSET CURRENT I
INPUT BIAS CURRENT IB ±2 nA max
INPUT RESISTANCE
Differential Mode RIN 26 MΩ min
INPUT VOLTAGE RANGE IVR ±13 V min
COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 1 μV/V max
POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 3 μV/V max
OUTPUT VOLTAGE SWING VO RL = 10 kΩ ±13.5 V min
R
R
LARGE-SIGNAL VOLTAGE GAIN AVO RL = 2 kΩ 2000 V/mV min
V
DIFFERENTIAL INPUT VOLTAGE ±30 V max
POWER CONSUMPTION Pd VO = 0 V 60 mW max
40 μV max
OS
2.0 nA max
OS
= 2 kΩ ±12.5
L
= 1 kΩ ±12.0
L
= ±10 V
O
Rev. E | Page 4 of 16
Page 5
OP77
TYPICAL ELECTRICAL CHARACTERISTICS
@ VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions OP77NBC Limit Unit
AVERAGE INPUT OFFSET VOLTAGE DRIFT TCVOS RS = 50 Ω 0.1 μV/°C
NULLED INPUT OFFSET VOLTAGE DRIFT TCV
AVERAGE INPUT OFFSET CURRENT DRIFT TCIOS 0.5 pA/°C
SLEW RATE SR RL ≥ 2 kΩ 0.3 V/μs
BANDWIDTH BW A
RS = 50 Ω, RP = 20 kΩ 0.1 μV/°C
OSn
+ 1 0.6 MHz
VCL
Rev. E | Page 5 of 16
Page 6
OP77
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter1 Rating
Supply Voltage ±22 V
Differential Input Voltage ±30 V
Input Voltage2 ±22 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −25°C to +85°C
Junction Temperature (TJ) −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
1
Absolute Maximum Ratings apply to both dice and packaged parts, unless
otherwise noted.
2
For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 6.
Package Type θ
8-Pin TO-99 H-08 (J Suffix) 150 18 °C/W
8-Lead Hermetic CERDIP Q-8 (Z Suffix) 148 16 °C/W
1
θJA is specified for worst-case mounting conditions, i.e., θJA is specified for a
device in socket for the TO-99 and CERDIP packages.
1
θJC Unit
JA
ESD CAUTION
Rev. E | Page 6 of 16
Page 7
OP77
TYPICAL PERFORMANCE CHARACTERISTICS
2
VS = ±15V
= 25°C
T
A
= 10kΩ
R
L
1
= 0V)
OUT
0
INPUT VOLTAGE ( µ V)
–1
(NULLED TO 0µV @ V
–2
–10 –5 0 5 10
OUTPUT VOLTAGE (V)
Figure 3. Gain Linearity (Input Voltage vs. Output Voltage)
25
VS = ±15V
20
15
10
OPEN-LOOP GAIN (V/µV)
5
0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
Figure 4. Open-Loop Gain vs. Temperature
30
J, Z PACKAGES
20
10
0
–10
–20
CHANGE IN OFFSET VOLTAGE (µV )
–30
–55 –35 –15 5 25 45 65 85 105 125
00320-004
TEMPERATURE (°C)
+0.3µV/°C
–0.3µV/°C
S.D.
MEAN
00320-007
Figure 6. Untrimmed Offset Voltage vs. Temperature
4
3
2
1
0
–1
–2
–3
CHANGE IN INPUT OFFSET V OLTAGE ( µV)
–4
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
00320-005
TIME AFTER POWE R SUPPLY TURN-ON (Minutes)
VS = ±15V
= 25°C
T
A
00320-008
Figure 7. Warm-Up Drift
16
TA = 25°C
R
= 2kΩ
L
12
8
OPEN-LOOP GAIN (V/µV)
4
0
0 ±5 ±10 ±15 ±20
POWER SUPPLY VO L TAGE (V)
Figure 5. Open-Loop Gain vs. Power Supply Voltage
00320-006
Rev. E | Page 7 of 16
30
25
20
15
10
OFFSET VOLTAGE (µV)
ABSOLUTE CHANGE IN INPUT
5
0
–10 0 10203040506070
DEVICE IMMERSED IN
70°C OIL BATH (20 UNITS)
MAXIMUM
AVERAGE
MIMIMUM
TIME (Seconds)
VS = ±15V
Figure 8. Offset Voltage Change Due to Thermal Shock
00320-009
Page 8
OP77
100
80
60
40
20
CLOSED-LOOP GAIN (dB)
0
–20
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
VS = ±15V
T
= 25°C
A
Figure 9. Closed-Loop Response for Various Gain Configurations
160
140
120
100
80
60
OPEN-LOOP GAIN (dB)
40
20
VS = ±15V
T
= 25°C
A
0
45
90
135
130
120
110
100
90
PSRR (dB)
80
70
60
0.1 1 10 100 1k 10k
00320-010
FREQUENCY (Hz)
TA = 25°C
00320-013
Figure 12. PSRR vs. Frequency
4
VS = ±15V
3
2
PHASE (Degrees)
1
INPUT BIAS CURRENT (nA)
0
0.01 0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 10. Open-Loop Gain/Phase Response
150
140
130
120
110
CMMR (dB)
100
90
80
1 10 100 1k 10k 100k
FREQUENCY (Hz)
TA = 25°C
Figure 11. CMRR vs. Frequency
180
0
–75 –50 –25 0 25 50 75 100 125
00320-011
TEMPERATURE ( °C)
00320-014
Figure 13. Input Bias Current vs. Temperature
2.0
VS = ±15V
1.5
1.0
0.5
INPUT OFF SE T CURRENT (nA)
0
–75 –50 –25 0 25 50 75 100 125
00320-012
TEMPERATURE ( °C)
00320-015
Figure 14. Input Offset Current vs. Temperature
Rev. E | Page 8 of 16
Page 9
OP77
10
VS = ±15V
T
= 25°C
A
100
TA = 25°C
1
RMS NOISE (mV)
0.1
100 1k 10k 100k
FREQUENCY (Hz)
Figure 15. Input Wideband Noise vs. Bandwidth (0.1 Hz to Frequency
Indicated)
1k
RS1 = RS2 = 200kΩ
THERMAL NOI S E OF SOURCE
100
10
INPUT NOISE VOLTAGE (nV/ Hz)
VS = ±15V
T
= 25°C
A
1
1 10 100 1k
RS = 0
FREQUENCY (Hz)
RESISTORS
INCLUDED
EXCLUDED
Figure 16. Total Input Noise Voltage vs. Frequency
10
POWE R CONSUMP TION (mW)
1
010203040
00320-016
TOTAL SUPPLY VOLTAGE V+ TO V– (V)
00320-019
Figure 18. Power Consumption vs. Power Supply
20
VS = ±15V
T
= 25°C
A
V
= ±10mV
IN
15
10
MAXIMUM OUTPUT (V)
5
0
100 1k 10k
00320-017
LOAD RESIS T ANCE TO GROUND (Ω)
POSITIVE SWING
NEGATIVE SWING
00320-020
Figure 19. Maximum Output Voltage vs. Load Resistance
32
28
24
20
16
12
8
PEAK-TO-PE AK AMPLITUDE (V )
4
0
1k 10k 100k 1M
FREQUENCY (Hz)
VS = ±15V
T
A
Figure 17. Maximum Output Swing vs. Frequency
= 25°C
00320-018
40
35
30
25
20
OUTPUT SHO RT-CIRCUIT CURRENT (mA)
15
0123
TIME FROM OUTPUT BEING SHORTENED (Minutes)
Figure 20. Output Short-Circuit Current vs. Time
VS = ±15V
T
= 25°C
A
4
00320-021
Rev. E | Page 9 of 16
Page 10
OP77
Ω
Ω
A
2
3
TEST CIRCUITS
50Ω
Figure 21. Typical Offset Voltage Test Circuit
2.5M
100Ω
100Ω
2
OP77
3
INPUT REFERRED NOISE =
Figure 22. Typical Low-Frequency Noise Test Circuit
–
INPUT
+
Figure 23. Optional Offset Nulling Circuit
200k
10kΩ 100kΩ
V
OP77
V
OS
V+
7
3.3kΩ
6
4
V–
4.7µF
(≈10Hz FILTER)
25,000
O
V
O
=
4000
00320-022
OUTPUT
VIN = ±10V
NOTES
1. GAIN NOT CONSISTANT. CAUSES NONLI NE AR E RRO RS .
.AVO SPEC IS ONLYPART OF THE SOLUTION.
. CHECK SPECIFICATION TABLE 1AND TABLE 2 FOR P ERFORMANCE.
1MΩ
V
10Ω
X
R
L
–10V 0V +10V
Figure 25. Open-Loop Gain Linearity
Actual open-loop voltage gain can vary greatly at various output
V
O
00320-023
voltages. All automated testers use endpoint testing and therefore
only show the average gain. This causes errors in high closed-
LPRECISION
TYPIC
OP AMP
V
Y
AVO 650V/mV
R
= 2kΩ
L
V
X
00320-026
loop gain circuits. Because this is difficult for manufacturers to
test, users should make their own evaluations. This simple test
circuit makes it easy. An ideal op amp would show a horizontal
scope trace.
V
Y
–10V 0V +10V
V
X
2
3
1
OP77
V–
100kΩ
+18V
20kΩ
8
4
V+
7
6
OUTPUT
00320-024
+
*
10µF
10Ω
00320-027
Figure 26. Output Gain Linearity Trace
0.1µF
2
NOTES
*
1 PER BOARD
7
–18V
4
10Ω
6
0.1µF
00320-025
OP77
3
10kΩ10kΩ
*
10µF
+
This is the output gain linearity trace for the new OP77. The
output trace is virtually horizontal at all points, assuring
extremely high gain accuracy. The average open-loop gain is
truly impressive—approximately 10,000,000.
Figure 24. Burn-In Circuit
Rev. E | Page 10 of 16
Page 11
OP77
APPLICATIONS
R2
1MΩ
+15V
0.1µF
R1
1kΩ
2
7
–15V
4
0.1µF
6
00320-028
R3
1kΩ
3
R4
1MΩ
OP77E
Figure 27. Precision High-Gain Differential Amplifier
The high gain, gain linearity, CMRR, and low TCVOS of the
OP77 make it possible to obtain performance not previously
available in single-stage, very high-gain amplifier applications.
For best CMR,
1R
must equal
2R
3R
. In this example, with a
4R
10 mV differential signal, the maximum errors are as listed in
Tabl e 7.
Table 7. Maximum Errors
Type Amount
Common-Mode Voltage 0.01%/V
Gain Linearity, Worst Case 0.02%
TCVOS 0.003%/°C
TCIOS 0.008%/°C
R
F
10µF
+15V
0.1µF
R
S
2
3
OP77
7
4
0.1µF
100Ω
6
C
LOAD
OUTPUT
INPUT
R1
V
IN
2
R2
3
These current sources can supply both positive and negative
current into a grounded load.
Note that
⎛
5R
⎜
Z
⎝
O
+
2R
And that for Z
to be infinite
O
R3
+15V
6
OP77
R4
I
= V
OUT
IN
( )
GIVEN R3 = R4 + R5, R1 = R2
R1 – R5
2N2222
2N2907
–15V
R3
Figure 30. 100 mA Current Source
4R
⎞
+=1
⎟
2R
⎠
4R5R
3R
1R
4R5R +
must =
2R
R5
I
< 100mA
OUT
00320-031
3R
1R
–15V
00320-029
Figure 28. Isolating Large Capacitive Loads
This circuit reduces maximum slew rate but allows driving
capacitive loads of any size without instability. Because the boon
resistor is inside the feedback loop, its effect on output
impedance is reduced to insignificance by the high open-loop
gain of the OP77.
R3
1kΩ
R1
100kΩ
R2
100kΩ
2
3
OP77
R4
990Ω
6
Figure 29. Basic Current Source
I
OUT
R5
10Ω
< 15mA
00320-030
Rev. E | Page 11 of 16
V
IN
Page 12
OP77
V
V
V
V
PRECISION CURRENT SINKS
+
IN
OP77
200Ω
Figure 31. Positive Current Sink
V
IN
R
L
I
O
IRF520
R1
1Ω
1W
2
3
OP77E
V
IN
IO =
R1
> 0V
V
IN
FULL SCALE OF 1V.
= 1A/V
I
O
+15V
0.1µF
7
6
4
0.1µF
0320-032
1kΩ 1kΩ
C1
30pFD11N4148
2N4393
R1
OP77
IN
200Ω
V–
IRF520
I
O
R
L
IO =
V
IN
V
> 0V
Figure 32. Positive Current Source
The simple high-current sinks, shown Figure 31 and Figure 32,
require the load to float between the power supply and the sink.
In these circuits, the high gain, high CMRR, and low TCV
the OP77 ensure high accuracy.
The high gain and low TCV
ensure accurate operation with
OS
inputs from microvolts to volts. In Figure 33, the signal always
appears as a common-mode signal to the op amps. The
OP77EZ CMRR of 1 μV/V ensures errors of less than 2 ppm.
+15V
0.1µF
2
7
D2
R3
2kΩ
OP77E
3
6
4
0.1µF
V
OUT
0 < V
OUT
< 10V
IN
R1
00320-033
of
OS
–15V
–15V
00320-035
Figure 33. Precision Absolute Value Amplifier
15
+
10µF
2
REF-01
4
6
V
O
2
REF-01
4
6
V
O
Figure 34. Low Noise Precision Reference
2
REF-01
4
100Ω
6
V
O
100Ω
100Ω
OP77
0.1µF
V
OUT
00320-036
Rev. E | Page 12 of 16
Page 13
OP77
Ω
V
Figure 34 relies upon low TCVOS of the OP77 and noise
combined with very high CMRR to provide precision buffering
of the averaged REF-01 voltage outputs.
In Figure 35, CH must be of polystyrene, Teflon*, or
polyethylene to minimize dielectric absorption and leakage.
The droop rate is determined by the size of C
H
current of the AD820.
*Teflon is a registered trademark of the Dupont Company
1k
and the bias
+15V
0.1µF
2
7
6
OP77
1kΩ
IN
3
4
0.1µF
–15V
RESET
1N4148
2N930
C
1kΩ
H
2
3
+15V
AD820
–15V
0.1µF
7
4
0.1µF
6
V
OUT
00320-037
Figure 35. Precision Positive Peak Detector
Rev. E | Page 13 of 16
Page 14
OP77
V
V
R
S
1kΩ
R1
2kΩ
2
3
TH
V
IN
+15V
OP77
–15V
0.1µF
7
4
0.1µF
C
C
R
F
100kΩ
D1
1N4148
6
V
OUT
00320-038
Figure 36. Precision Threshold Detector/Amplifier
When VIN < VTH, amplifier output swings negative, reversing the
biasing diode D1. V
= VTH if RL= ∞ when VIN > VTH, the loop
O
closes,
⎛
()
TH
IN
O
C
is selected to smooth the response of the loop.
C
⎜
VVVV 1
TH
⎜
⎝
⎞
R
F
⎟
+−+=
⎟
R
S
⎠
7
V+
Q5
3
NONINVERTING
INPUT
INVERTING
INPUT
1
R2A AND R2B ARE ELECTRONICAL LY ADJUSTED ON CHIP AT FACTORY.
R3
2
Q21
R4
Q22
1
R2A
R1A
Q7
Q23
Q24
4
V–
(OPTIONAL
NULL)
18
Q8
Q6
Q1
R2B
R1B
Q4Q3
Q2
Figure 38. Simplified Schematic
1
+15
0.1µF
2
V
IN
TRIM
REF-02
TEMP
GND
4
V
O
R
50kΩ
1.5kΩ
a
R
b1
R
bp
6
5
3
OP77
–15V
R
0.1µF
c
V
OUT
Figure 37. Precision Temperature Sensor
Table 8. Resistor Values
TCV
Slope (S) 10 mV/°C 100 mV/°C 10 mV/°F
OUT
Temperature Range
Output Voltage
Range
−55°C to
+125°C
−0.55 V to
+1.25 V
−55°C to
+125°C
−5.5 V to
+12.5V
Zero-Scale 0 V @ 0°C 0 V @ 0°C 0 V @ 0°F
Ra (±1% Resistor) 9.09 kΩ 15 kΩ 7.5 kΩ
Rb1 (±1% Resistor) 1.5 kΩ 1.82 kΩ 1.21 kΩ
Rbp (Potentiometer) 200 Ω 500 Ω 200 Ω
Rc (±1% Resistor) 5.11 kΩ 84.5 kΩ 8.25 kΩ
Q27
Q26
Q25
C1
Q10Q9
Q11 Q12
C3
R5
C2
Q14
Q13
Q17
Q16
Q15
R7
Q19
R9
R10
Q20
Q18
R8R6
00320-039
6
OUTPUT
−67°F to
+257°C
−0.67 V to
+2.57V
00320-003
Rev. E | Page 14 of 16
Page 15
OP77
OUTLINE DIMENSIONS
0.005 (0.13)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 39. 8-Lead Ceramic Dual In-Line Package [CERDIP]
Dimensions shown in inches and (millimeters)
0.1850 (4.70)
0.1650 (4.19)
0.3700 (9.40)
0.3350 (8.51)
0.3350 (8.51)
0.3050 (7.75)
0.0400 (1.02) MAX
0.0400 (1.02)
0.0100 (0.25)
CONTROLL ING DIMENSIONS ARE IN INCHES; MILL IMETER DI M E NSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRIATE FOR USE I N DE S IGN.
0.5000 (12.70)
0.0190 (0.48)
0.0160 (0.41)
COMPLIANT TO JE DEC STANDARDS MO-002-AK
Dimensions shown in inches and (millimeters)
0.055 (1.40)
MIN
14
0.100 (2.54) BSC
0.405 (10.29) MAX
MAX
0.070 (1.78)
0.030 (0.76)
58
0.310 (7.87)
0.220 (5.59)
0.060 (1.52)
0.015 (0.38)
0.150 (3.81)
MIN
SEATING
PLANE
(Q-8)
REFERENCE PLANE
MIN
0.2500 (6.35) M IN
0.0500 (1.27) M AX
0.0210 (0.53)
0.0160 (0.41)
BASE & SEAT I NG PLANE
0.2000
(5.08)
BSC
0.1000
(2.54)
BSC
0.1000 (2.54)
BSC
4
3
2
Figure 40. 8-Pin Metal Header [TO-99]
(H-08)
0.320 (8.13)
0.290 (7.37)
15°
0°
5
6
8
1
0.0340 (0.86)
0.0280 (0.71)
45° BSC
0.015 (0.38)
0.008 (0.20)
0.1600 (4.06)
0.1400 (3.56)
7
0.0450 (1.14)
0.0270 (0.69)
022306-A
Rev. E | Page 15 of 16
Page 16
OP77
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
OP77FJ −25°C to +85°C 8-Pin Metal Header [TO-99] H-08 (J Suffix)
OP77FJZ −25°C to +85°C 8-Pin Metal Header [TO-99] H-08 (J Suffix)
OP77EZ −25°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 (Z Suffix)
OP77FZ −25°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 (Z Suffix)
OP77NBC Die
1
Z = RoHS Compliant Part.
©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00320-0-4/10(E)
Rev. E | Page 16 of 16
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