Datasheet OP491, OP291, OP191 Datasheet (Analog Devices)

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Page 1

Micropower Single-Supply

NC = NO CONNECT

1 2 3 4

8 7 6 5

OP191

OUTA

V+

NC –INA +INA

–V

1 2 3 4

8 7 6 5

OP191

1 2 3 4 5 6 7

14 13 12 11 10

9 8

OP491

OUTD –IND +IND –V +INC –INC OUTC

OUTA

–INA +INA

+V +INB –INB

OUTB

1 2 3 4 5 6 7

14 13 12 11 10

9 8

OP491

OUTD –IND +IND –V +INC –INC OUTC

OUTA

–INA +INA

+V +INB –INB

OUTB

1 2

5 6 7

3 4

14 13

9 8

12 11

OP491

Rail-to-Rail Input/Output Op Amps

FEATURES Single-Supply Operation: 2.7 V to 12 V Wide Input Voltage Range Rail-to-Rail Output Swing Low Supply Current: 300 µA/Amp Wide Bandwidth: 3 MHz Slew Rate: 0.5 V/µs Low Offset Voltage: 700 µV No Phase Reversal

APPLICATIONS Industrial Process Control Battery Powered Instrumentation Power Supply Control and Protection Telecom Remote Sensors Low Voltage Strain Gage Amplifiers DAC Output Amplifier

GENERAL DESCRIPTION

The OP191, OP291 and OP491 are single, dual and quad micropower, single-supply, 3 MHz bandwidth amplifiers featuring rail-to-rail inputs and outputs. All are guaranteed to operate from a 3 volt single supply as well as ± 5 volt dual supplies.

Fabricated on Analog Devices’ CBCMOS process, the OP191 family has a unique input stage that allows the input voltage to safely extend 10 volts beyond either supply without any phase inversion or latch-up. The output voltage swings to within millivolts of the supplies and continues to sink or source current all the way to the supplies.

Applications for these amplifiers include portable telecom equipment, power supply control and protection, and interface for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezo electric, and resistive transducers.

The ability to swing rail-to-rail at both the input and output enables designers to build multistage filters in single-supply systems and maintain high signal-to-noise ratios.

The OP191/OP291/OP491 are specified over the extended industrial (–40°C to +125°C) temperature range. The OP191 single and OP291 dual amplifiers are available in 8-pin plastic DIPs and SO surface mount packages. The OP491 quad is available in 14-pin DIPs and narrow 14-pin SO packages. Consult factory for OP491 TSSOP availability.

OP191/OP291/OP491

OP191/OP291/OP491 PIN CONFIGURATIONS

8-Lead Narrow-Body SO 8-Lead Epoxy DIP (S Suffix) (P Suffix)

8-Lead Narrow-Body SO 8-Lead Epoxy DIP

(S Suffix) (P Suffix)

1 2

OP291

3 4

14-Lead Epoxy DIP 14-Lead SO

(P Suffix) (S Suffix)

8 7 6 5

14-Lead

TSSOP

(RU Suffix)

OUTA

–INA +INA

OP291

2 3 4

–V

OUTB

–INB

+INB

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703

Page 2

OP191/OP291/OP491–SPECIFICA TIONS

ELECTRICAL SPECIFICATIONS

(@ VS = +3.0 V, VCM = 0.1 V, VO = 1.4 V, TA = +25°C unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage OP191G V

OP291/OP491G V Input Bias Current I Input Offset Current I

–40 ≤ T –40 ≤ T –40 ≤ T –40 ≤ T

≤ +125°C1mV

≤ +125°C 1.25 mV

≤ +125°C70nA

≤ +125°C16nA

80 500 µV 80 700 µV 30 50 nA

0.1 8 nA

Input Voltage Range 0 3 V Common-Mode Rejection Ratio CMRR V

Large Signal Voltage Gain A Offset Voltage Drift ∆V

Bias Current Drift ∆I

/∆T 1.1 µV/°C

/∆T 100 pA/°C

= 0 V to 2.9 V 70 90 dB

–40 ≤ T

≤ +125°C6587dB

RL = 10 kΩ , VO = 0.3 V to 2.7 V 25 70 V/mV –40 ≤ T

≤ +125°C 50 V/mV

Offset Current Drift ∆IOS/∆T 20 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage High V

RL = 100 kΩ to GND 2.95 2.99 V –40°C to +125°C 2.90 2.98 V R

= 2 kΩ to GND 2.8 2.9 V

–40°C to +125°C 2.70 2.8 V

Output Voltage Low V

RL = 100 kΩ to V+ 4.5 10 mV –40°C to +125°C35mV R

= 2 kΩ to V+ 40 75 mV

–40°C to +125°C 130 mV

Short Circuit Limit I

Sink/Source ± 8.75 ±13.5 mA –40°C to +125°C ±6.0 ±10.5 mA

Open Loop Impedance Z

OUT

f = 1 MHz, AV = 1 200 Ω

POWER SUPPLY

Power Supply Rejection Ratio PSRR V Supply Current/Amplifier I

= 2.7 V to 12 V 80 110 dB

–40°C ≤ T

≤ +125°C 75 110 dB

VO = 0 V 200 350 µA –40°C ≤ TA ≤ +125°C 330 480 µA

DYNAMIC PERFORMANCE

Slew Rate +SR R Slew Rate –SR R Full-Power Bandwidth BW Settling Time t

= 10 kΩ 0.4 V/µs

1% Distortion 1.2 kHz

To 0.01% 22 µs Gain Bandwidth Product GBP 3 MHz Phase Margin θ

45 Degrees

Channel Separation CS f = 1 kHz, RL = 10 kΩ 145 dB

NOISE PERFORMANCE

Voltage Noise e Voltage Noise Density e Current Noise Density i

Specifications subject to change without notice.

p-p 0.1 Hz to 10 Hz 2 µV p-p

n n

f = 1 kHz 35 nV/√Hz

0.8 pA/√Hz

–2–

REV. 0

Page 3

OP191/OP291/OP491

ELECTRICAL SPECIFICATIONS

(@ VS = +5.0 V, VCM = 0.1 V, VO = 1.4 V, TA = +25°C unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage OP191 V

OP291/OP491 V Input Bias Current I Input Offset Current I

–40 ≤ T –40 ≤ T –40 ≤ T –40 ≤ T

≤ +125°C 1.0 mV

≤ +125°C 1.25 mV

≤ +125°C60nA

≤ +125°C16nA

80 500 µV 80 700 µV 30 50 nA

0.1 8 nA

Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR V

Large Signal Voltage Gain A Offset Voltage Drift ∆V

Bias Current Drift ∆I

/∆T –40 ≤ TA ≤ +125°C 1.1 µV/°C

/∆T 100 pA/°C

= 0 V to 4.9 V 70 93 dB

–40 ≤ T

≤ +125°C6590dB

RL = 10 kΩ , VO = 0.3 V to 4.7 V 25 70 V/mV –40 ≤ T

≤ +125°C 50 V/mV

Offset Current Drift ∆IOS/∆T 20 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage High V

RL = 100 kΩ to GND 4.95 4.99 V –40°C to +125°C 4.90 4.98 V R

= 2 kΩ to GND 4.8 4.85 V

–40°C to +125°C 4.65 4.75 V

Output Voltage Low V

RL = 100 kΩ to V+ 4.5 10 mV –40°C to +125°C35mV R

= 2 kΩ to V+ 40 75 mV

–40°C to +125°C 155 mV

Short Circuit Limit I

Sink/Source ± 8.75 ±13.5 mA –40°C to +125°C ±6.0 ±10.5 mA

Open Loop Impedance Z

OUT

f = 1 MHz, AV = 1 200 Ω

POWER SUPPLY

Power Supply Rejection Ratio PSRR V Supply Current/Amplifier I

= 2.7 V to 12 V 80 110 dB

–40 ≤ T

≤ +125°C 75 110 dB

VO = 0 V 220 400 µA –40 ≤ TA ≤ +125°C 350 500 µA

DYNAMIC PERFORMANCE

Slew Rate +SR R Slew Rate –SR R Full-Power Bandwidth BW Settling Time t

= 10 kΩ 0.4 V/µs

1% Distortion 1.2 kHz

To 0.01% 22 µs Gain Bandwidth Product GBP 3 MHz Phase Margin θ

45 Degrees

Channel Separation CS f = 1 kHz, RL = 10 kΩ 145 dB

NOISE PERFORMANCE

Voltage Noise e Voltage Noise Density e Current Noise Density i

NOTES +5 V specifications are guaranteed by +3 V and ±5 V testing. Specifications subject to change without notice.

REV. 0

p-p 0.1 Hz to 10 Hz 2 µV p-p

n n

f = 1 kHz 35 nV/√Hz

0.8 pA/√Hz

–3–

Page 4

OP191/OP291/OP491

ELECTRICAL SPECIFICATIONS

(@ VO = ±5.0 V, –4.9 V ≤ VCM ≤ +4.9 V, TA = +25°C unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage OP191 V

OP291/OP491 V Input Bias Current I Input Offset Current I

–40 ≤ T –40 ≤ T –40 ≤ T –40 ≤ T

≤ +125°C1mV

≤ +125°C 1.25 mV

≤ +125°C70nA

≤ +125°C16nA

80 500 µV 80 700 µV 30 50 nA

0.1 8 nA

Input Voltage Range –5 +5 V Common-Mode Rejection CMR V

Large Signal Voltage Gain A Offset Voltage Drift ∆V

Bias Current Drift ∆I

/∆T 1.1 µV/°C

/∆T 100 pA/°C

= ±5 V 75 100 dB

–40 ≤ T

≤ +125°C6797dB

RL = 10 kΩ, VO = ±4.7 V, 25 70 –40 ≤ T

≤ +125°C 50 V/mV

Offset Current Drift ∆IOS/∆T 20 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage Swing V

RL = 100 kΩ to GND ±4.93 ±4.99 V –40°C to +125°C ±4.90 ±4.98 V R

= 2 kΩ to GND ±4.80 ±4.95 V

Short Circuit Limit I

–40 ≤ T Sink/Source ± 8.75 ±16 mA

≤ +125°C ±4.65 ±4.75 V

–40°C to +125°C ±6 ±13 mA

Open Loop Impedance Z

OUT

f = 1 MHz, AV = 1 200 Ω

POWER SUPPLY

Power Supply Rejection Ratio PSRR V Supply Current/Amplifier I

= ±5 V 80 110 dB

–40 ≤ T

≤ +125°C 70 100 dB

VO = 0 V 260 420 µA –40 ≤ TA ≤ +125°C 390 550 µA

DYNAMIC PERFORMANCE

Slew Rate ±SR R Full-Power Bandwidth BW Settling Time t

=10 kΩ 0.5 V/µs

1% Distortion 1.2 kHz

To 0.01% 22 µs Gain Bandwidth Product GBP 3 MHz Phase Margin θ

45 Degrees

Channel Separation CS f = 1 kHz 145 dB

NOISE PERFORMANCE

Voltage Noise e Voltage Noise Density e Current Noise Density i

Specifications subject to change without notice.

p-p 0.1 Hz to 10 Hz 2 µV p-p

n n

INPUT

OUTPUT

f = 1 kHz 35 nV/√Hz

0.8 pA/√Hz

100

10 0%

VS = ±5V R

= 2kΩ

= +1

= 20Vp-p

200µs

Figure 1. Input and Output with Inputs Overdriven by 5 V

–4–

REV. 0

Page 5

OP191/OP291/OP491

W AFER TEST LIMITS

(@ VS = +3.0 V, VCM = 0.1 V, TA = +25°C unless otherwise noted)

Parameter Symbol Conditions Limit Units

Offset Voltage V Input Bias Current I Input Offset Current I Input Voltage Range V

OS B OS

Common-Mode Rejection Ratio CMRR V

= 0 V to +2.9 V 70 dB min

±300 µV max 50 nA max 8nA V– to V+ V min

Power Supply Rejection Ratio PSRR V = 2.7 V to +12 V 80 dB min Large Signal Voltage Gain A Output Voltage High V Output Voltage Low V Supply Current/Amplifier I

NOTE Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS

OL SY

RL = 10 kΩ 50 V/mV min RL = 2 kΩ to GND 2.8 V min RL = 2 kΩ to V+ 75 mV max VO = 0 V, RL = ∞ 350 µA max

ORDERING GUIDE

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .GND to V

+ 10 V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .7 V

Output Short-Circuit Duration to GND . . . . . . . . . .Indefinite

Storage Temperature Range

P, S, RU Packages . . . . . . . . . . . . . . . . . . .–65°C to +150°C

Operating Temperature Range

OP191/OP291/OP491G . . . . . . . . . . . . . . .–40°C to +125°C

Junction Temperature Range

P, S, RU Packages . . . . . . . . . . . . . . . . . . .–65°C to +150°C

Lead Temperature Range (Soldering60sec) . . . . . . . . +300°C

Package Type θ

Units

Model Range Description Option

OP191GP –40°C to +125°C 8-Pin Plastic DIP N-8 OP191GS –40°C to +125°C 8-Pin SOIC SO-8 OP191GBC +25°C DICE OP291GP –40°C to +125°C 8-Pin Plastic DIP N-8 OP291GS –40°C to +125°C 8-Pin SOIC SO-8 OP291GBC +25°C DICE OP491GP –40°C to +125°C 14-Pin Plastic DIP N-14 OP491GS –40°C to +125°C 14-Pin SOIC SO-14 OP491HRU –40°C to +125°C 14-Pin TSSOP RU-14 OP491GBC +25°C DICE

Temperature Package Package

8-Pin Plastic DIP (P) 103 43 °C/W 8-Pin SOIC (S) 158 43 °C/W 14-Pin Plastic DIP (P) 76 33 °C/W 14-Pin SOIC (S) 120 36 °C/W 14-Pin TSSOP (RU) 180 35 °C/W

NOTES

Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted.

θJA is specified for the worst case conditions; i.e., θ

for P-DIP packages; θ and SOIC packages.

is specified for device soldered in circuit board for TSSOP

is specified for device in socket

14 13

DICE CHARACTERISTICS

OP191 Die Size 0.047 × 0.066 Inch, 3,102 Sq. Mils. Substrate (Die Backside) Is Connected to V+. Transistor Count, 74.

REV. 0

212

OP291 Die Size 0.070 × 0.070 Inch, 4,900 Sq. Mils. Substrate (Die Backside) Is Connected to V+. Transistor Count, 146

–5–

OP491 Die Size 0.070 × 0.110 Inch, 7,700 Sq. Mils. Substrate (Die Backside) Is Connected to V+. Transistor Count, 290.

Page 6

OP191/OP291/OP491–T ypical Performance Characteristics

–36

3.0

–18

–30

0.30

–24

–12

–6

30 24

2.72.42.11.81.51.20.900.60

INPUT COMMON MODE VOLTAGE – Volts

INPUT BIAS CURRENT – nA

VS = +3V

1200

1000

800

600

400

200

12525–40

TEMPERATURE – °C

OPEN-LOOP GAIN –V/mV

VS = 3V, VO = 0.3V / 2.7V

RL = 100kΩ, V

= 2.9V

RL = 100kΩ, V

= 0.1V

180

VS = +3V

160

= +25°C

BASED ON 1200

140

OP AMPS

120

100

UNITS

–0.18

INPUT OFFSET VOLTAGE – mV

0.14

0.06–0.02–0.10

0.22

Figure 2. OP291 Input Offset Voltage Distribution, V

40 30 20 10

0 –10 –20 –30

INPUT BIAS CURRENT – nA

–40 –50 –60

VS = +3V

TEMPERATURE – °C

= +3 V

= 3V

= 2.9V

= 0.1V

= 0V

12525–40 85

120

100

UNITS

1400

= +3V

–40°C < T

< +125°C

BASED ON 600 OP AMPS

INPUT OFFSET VOLTAGE – µV/ °C

64325

Figure 3. OP291 Input Offset Voltage Drift Distribution, V

–0.2

VS = +3V

–0.4 –0.6 –0.8 –1.0 –1.2 –1.4

INPUT OFFSET CURRENT – nA

–1.6 –1.8

VCM = 0.1V VCM = 2.9V

VCM = 3V

VCM = 0V

TEMPERATURE – °C

= +3 V

12525–40

VS = +3V

–0.02

–0.04

–0.06

–0.08

–0.1

INPUT OFFSET VOLTAGE – mV

–0.12

–0.14

VCM = 0.1V

VCM = 3V

TEMPERATURE – °C

VCM = 0V

VCM = 2.9V

Figure 4. Input Offset Voltage vs. Temperature, V

= +3 V

12525–40

Figure 5. Input Bias Current vs. Temperature, V

3.00

2.95

2.90

2.85

OUTPUT SWING – Volts

2.80

VS = +3V

2.75

–40

Figure 8. Output Voltage Swing vs. Temperature, V

= +3 V

+VO @ RL = 100k

+VO @ RL = 2k

TEMPERATURE – °C

= +3 V

125

Figure 6. Input Offset Current vs. Temperature, V

160 140 120 100

40 20

OPEN-LOOP GAIN – dB

0 –20 –40

100601k 10k 100k 1M 10M

FREQUENCY – Hz

= +3 V

VS = +3V T

= +25°C

0 45

90 135 180 225

270

Figure 9. Open-Loop Gain & Phase vs. Frequency, V

= +3 V

–6–

Figure 7. Input Bias Current vs. Common-Mode Voltage, V

PHASE SHIFT – Degrees

Figure 10. Open-Loop Gain vs. Temperature, VS = +3 V

= +3 V

REV. 0

Page 7

OP191/OP291/OP491

VS = +3V

TEMPERATURE – °C

125

–40

CMRR – dB

VS = +3V

TEMPERATURE – °C

1.6

125

0.4

0.2

25–40

0.8

0.6

1.0

1.2

1.4

SLEW RATE – V/µs

+SR

–SR

100

MKR: 36.2 nV/√Hz

MKR:

0 Hz 1000 Hz

BW:

2.5kHz

15.0 Hz

50 40

30 20 10

0 –10 –20

CLOSED-LOOP GAIN – dB

–30 –40 –50

10 100 10M1M100k10k1k

FREQUENCY – Hz

VS = +3V T

= +25°C

Figure 11. Closed-Loop Gain vs. Frequency, V

160 140 120 100

PSRR – dB

0 –20 –40

100601k 10k 100k 1M 10M

= +3 V

+PSRR

–PSRR

FREQUENCY – Hz

±PSRR V

= +3V

= +25°C

160 140 120 100

CMRR – dB

0 –20 –40

100601k 10k 100k 1M 10M

FREQUENCY – Hz

CMRR V

= +3V

= +25°C

Figure 12. CMRR vs. Frequency, V

= +3 V

113

112

111

110

PSRR – dB

109

108

107

–40

TEMPERATURE – °C

VS = +3V

125

Figure 13. CMRR vs. Temperature,

= +3 V

Figure 14. PSRR vs. Frequency,

= +3 V

0.35 VS = +3V

0.30

0.25

0.20

0.15

0.10

SUPPLY CURRENT/AMPLIFIER – mA

0.05

–40

Figure 17. Supply Current vs. Temperature, V

REV. 0

TEMPERATURE – °C

= +3 V, +5 V, ±5 V

Figure 15. PSRR vs. Temperature,

= +3 V

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

MAXIMUM OUTPUT SWING – Volts

1.2

1.0

125

0.50.1 FREQUENCY – kHz

VIN = +2.8Vp-p V

= +3V

= +1

= 100k

300

250200150100705030101.0

Figure 18. Maximum Output Swing vs. Frequency, V

= +3 V

Figure 16. Slew Rate vs. Temperature, V

= +3 V

Figure 19. Voltage Noise Density,

= +3 V to ±5 V, AVO = 1000

–7–

Page 8

– mV

VS = +5V

TEMPERATURE – °C

0.15

–0.1

125

0.05

–0.05

–40

0.10

VCM = 0V

= +5V

OP191/OP291/OP491–T ypical Performance Characteristics

VS = +5V T

= +25°C

BASED ON 600 OP AMPS

UNITS

0 –.50

INPUT OFFSET VOLTAGE – mV

.50

.30.10–.10–.30

Figure 20. OP291 Input Offset Voltage Distribution, V

VS = +5V

– nA

–10

–20

–30

–40

= +5 V

VCM = 5V

= 0V

25–40

TEMPERATURE – °C

–I

125

120

100

UNITS

1.0

INPUT OFFSET VOLTAGE – µV/ °C

VS = +5V –40°C < T BASED ON 600 OP AMPS

< +125°C

6.05.04.03.02.0

7.0

Figure 21. OP291 Input Offset Voltage Drift Distribution, V

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

INPUT OFFSET CURRENT – nA

–0.2

VCM = 0V

VCM = 5V

25–40

TEMPERATURE – °C

= +5 V

VS = +5V

125

Figure 22. Input Offset Voltage vs. Temperature, V

VS = +5V

30 24 18 12

6 0

–6 –12 –18

INPUT BIAS CURRENT – nA

–24 –30 –36

COMMON MODE INPUT VOLTAGE – Volts

= +5 V

4321

Figure 23. Input Bias Current vs. Temperature, V

5.00

4.95

4.90

4.85

4.80

OUTPUT SWING – Volts

4.75 VS = +5V

4.70

–40

Figure 26. Output Voltage Swing vs. Temperature, V

= +5 V

= 2k

TEMPERATURE – °C

= +5 V

Figure 24. Input Offset Current vs. Temperature, V

= +5 V

Figure 25. Input Bias Current vs. Common-Mode Voltage, VS = +5 V

= 100k

125

160 140 120 100

80 60 40 20

OPEN-LOOP GAIN – dB

0 –20 –40

100

1k 10k 100k 1M 10M

FREQUENCY – Hz

VS = +5V T

= +25°C

0 45 90 135 180 225 270

Figure 27. Open-Loop Gain & Phase vs. Frequency, V

= +5 V

140

120

RL = 100k, VCM = 5V

100

RL = 2k, VCM = 5V

OPEN-LOOP GAIN – V/mV

PHASE SHIFT – Degrees

RL = 2k, VCM = 0V

–40

TEMPERATURE – °C

Figure 28. Open-Loop Gain vs. Temperature, V

= +5 V

VS = +5V

RL = 100k, VCM = 0V

125

–8–

REV. 0

Page 9

OP191/OP291/OP491

TEMPERATURE – °C

VS = +5V

0.50

125

0.15

0.05

0.10

–40

0.30

0.20

0.25

0.35

0.40

0.45

+SR

–SR

SR – V/µs

50 40

30 20 10

0 –10 –20

CLOSED-LOOP GAIN – dB

–30 –40 –50

10 100 10M1M100k10k1k

FREQUENCY – Hz

VS = +5V T

= +25°C

Figure 29. Closed-Loop Gain vs. Frequency, V

160 140 120 100

PSRR – dB

–20 –40

100601k 10k 100k 1M 10M

= +5 V

–PSRR

FREQUENCY – Hz

±PSRR V

+PSRR

= +5V = +25°C

160 140 120 100

CMRR – dB

0 –20 –40

100601k 10k 100k 1M 10M

FREQUENCY – Hz

CMRR V

= +5V

= +25°C

Figure 30. CMRR vs. Frequency, V

= +5 V

0.6

0.5

0.4

0.3

SR – V/µs

0.2

0.1

–40

+SR

–SR

TEMPERATURE – °C

VS = +5V

125

VS = +5V

95 94 93 92 91

CMRR – dB

90 89 88 87 86

–40

TEMPERATURE – °C

125

Figure 31. CMRR vs. Temperature,

= +5 V

Figure 32. PSRR vs. Frequency,

= +5 V

+ISC, VS = +3V

SHORT CIRCUIT CURRENT – mA

Figure 35. Short Circuit Current vs. Temperature, V

REV. 0

+ISC, VS = ±5V

–ISC, VS = ±5V

–ISC, VS = +3V

25–40

TEMPERATURE – °C

= +3 V, +5 V,±5V

Figure 33. OP291 Slew Rate vs. Temperature, V

VOLTAGE – µV

= 10Vp-p @ 1kHz

125

= +5 V

10k

FREQUENCY – Hz

VS = ±5V

10k

2500

200015001000500

Figure 36. Channel Separation,

=±5 V

Figure 34. OP491 Slew Rate vs. Temperature, V

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

MAXIMUM OUTPUT SWING – Volts

0.5 0

0.5

0.1

= +5 V

VIN = +4.8Vp-p V A R 4 PARTS

FREQUENCY – kHz

= +5V

= +1

= 100k

300

250100 15050 70 20030101.0

Figure 37. Maximum Output Swing vs. Frequency, V

= +5 V

–9–

Page 10

OP191/OP291/OP491–T ypical Performance Characteristics

TEMPERATURE – °C

VS = ±5V

–50

125

–20

–40

–30

–40

–10

– nA

–I

VCM = +5V

VCM = –5V

–50

10 100 10M1M100k10k1k

–40

–30

–20

–10

CLOSED-LOOP GAIN – dB

VS = ±5V T

= +25°C

FREQUENCY – Hz

9 8 7 6 5 4 3

MAXIMUM OUTPUT SWING – Volts

1 0

0.520.1 FREQUENCY – kHz

VIN = +9.8Vp-p V

= ±5V

= +1

= 100k

4 PARTS

250100 15050 70 20030101.0

300

Figure 38. Maximum Output Swing vs. Frequency, V

1.6 VS = ±5V

1.4

1.2

1.0

0.8

0.6

0.4

0.2

INPUT OFFSET CURRENT – nA

–0.2

=±5V

VCM = –5V

25–40

TEMPERATURE – °C

VCM = +5V

125

0.15

0.10 VCM = –5V

0.05

–0.05 INPUT OFFSET VOLTAGE – mV

–0.1

–40

VCM = +5V

TEMPERATURE – °C

VS = ±5V

125

Figure 39. Input Offset Voltage vs. Temperature, V

VS = ±5V

–12

INPUT BIAS CURRENT – nA

–24

–36

COMMON MODE INPUT VOLTAGE – Volts

=±5V

–1–2–3–4–5

4321

Figure 40. Input Bias Current vs. Temperature, V

5.00

4.95

4.90

4.85

4.80 VS = ±5V

4.75

0 –4.75 –4.80 –4.85 –4.90

OUTPUT VOLTAGE SWING – Volts

–4.95 –5.00

–40

= ±5 V

RL = 100k

RL = 2k

RL = 100k

TEMPERATURE – °C

125

Figure 41. Input Offset Current vs. Temperature, V

70 60 50 40 30 20 10

OPEN-LOOP GAIN – dB

–10 –20 –30

Figure 44. Open-Loop Gain & Phase

vs. Frequency, V

=±5V

10k 10M1M100k

FREQUENCY – Hz

= ±5 V

Figure 42. Input Bias Current vs.

=±5V

VS = ±5V

125

Common-Mode Voltage, V

200

VS = ±5V T

= +25°C

0 45 90 135 180 225

PHASE SHIFT – Degrees

270

180 160 140 120 100

80 65

OPEN-LOOP GAIN – V/mV

40 25

–40

RL = 100kΩ

RL = 2kΩ

TEMPERATURE – °C

Figure 45. Open-Loop Gain vs. Temperature, V

=±5V

–10–

Figure 43. Output Voltage Swing vs. Temperature, V

=±5V

Figure 46. Closed-Loop Gain vs. Frequency, V

=±5V

REV. 0

Page 11

OP191/OP291/OP491

160

100

–40

1k 10k 100k 1M 10M

100

120

140

–20

+PSRR

–PSRR

±PSRR V

= ±5V

= +25°C

PSRR – dB

FREQUENCY – Hz

500

100 1k 10M1M100k10k

600

700

800

900

100

200

300

400

VS = +3V T

= +25°C

VCL

= 100

VCL

= 10

VCL

= +1

FREQUENCY – Hz

OUT

– Ω

160 140 120 100

CMRR – dB

0 –20 –40

100601k 10k 100k 1M 10M

FREQUENCY – Hz

CMRR V

= ±5V

= +25°C

Figure 47. CMRR vs. Frequency,

=±5V

115

110

105

PSRR – dB

100

–40

VS = ±5V

TEMPERATURE – °C

OP291

OP491

125

102

VS = ±5V

101 100

99 98 97

CMRR – dB

96 95 94 93 92

–40

TEMPERATURE – °C

125

Figure 48. CMRR vs. Temperature,

=±5V

0.7 VS = ±5V

0.6

0.5

0.4

0.3

SR – V/µs

0.2

0.1

–40

+SR

–SR

TEMPERATURE – °C

125

Figure 49. PSRR vs. Frequency,

=±5V

Figure 50. OP291/OP491 PSRR vs. Temperature, V

=±5V

INPUT

OUTPUT

1.00V

100

10 0%

500mV

Figure 53. Large Signal Transient Response, V

REV. 0

= +3 V

2.00µs

Figure 51. Slew Rate vs. Temperature, V

VS = +3V R

= 200kΩ

100mV

OUTPUT

–11–

Figure 52. Output Impedance vs.

=±5V

INPUT

2.00V

100

10 0%

Frequency

VS = ±5V R

= 200kΩ

= +1V/V

2.00µs

Figure 54. Large Signal Transient Response, V

= ±5 V

100mV1.00V

Page 12

OP191/OP291/OP491

FUNCTIONAL DESCRIPTION

The OP191/OP291/OP491 are single supply, micropower amplifiers featuring rail-to-rail inputs and outputs. In order to achieve wide input and output ranges, these amplifiers employ unique input and output stages. As the simplified schematic shows (Figure 55), the input stage is actually comprised of two differential pairs, a PNP pair and an NPN pair. These two stages do not actually work in parallel. Instead, only one or the other stage is on for any given input signal level. The PNP stage (transistors Q1 and Q2) is required to ensure that the amplifier remains in the linear region when the input voltage approaches and reaches the negative rail. On the other hand, the NPN stage (transistors Q5 and Q6) is needed for input voltages up to and including the positive rail.

For the majority of the input common-mode range, the PNP stage is active, as is evidenced by examining the graph of Input Bias Current vs. Common-Mode Voltage. Notice that the bias current switches direction at approximately 1.2 volts to 1.3 volts below the positive rail. At voltages below this, the bias current flows out of the OP291, indicating a PNP input stage. Above this voltage, however, the bias current enters the device, revealing the NPN stage. The actual mechanism within the amplifier for switching between the input stages is comprised of the transistors Q3, Q4, and Q7. As the input common-mode voltage increases, the emitters of Q1 and Q2 follow that voltage plus a diode drop. Eventually the emitters of Q1 and Q2 are high enough to turn Q3 on. This diverts the 8 µA of tail current away from the PNP input stage, turning it off. Instead, the current is mirrored through Q4 and Q7 to activate the NPN input stage.

Notice that the input stage includes 5 kΩ series resistors and differential diodes, a common practice in bipolar amplifiers to protect the input transistors from large differential voltages. These diodes will turn on whenever the differential voltage

exceeds approximately 0.6 V. In this condition, current will flow between the input pins, limited only by the two 5 kΩ resistors. Being aware of this characteristic is important in circuits where the amplifier may be operated open-loop, such as a comparator. Evaluate each circuit carefully to make sure that the increase in current does not affect the performance.

The output stage of the OP191 family uses a PNP and an NPN transistor as do most output stages; however, the output transistors, Q32 and Q33, are actually connected with their collectors to the output pin to achieve the rail-to-rail output swing. As the output voltage approaches either the positive or negative rail, these transistors begin to saturate. Thus, the final limit on output voltage is the saturation voltage of these transistors, which is about 50 mV. The output stage does have inherent gain arising from the collectors and any external load impedance. Because of this, the open-loop gain of the amplifier is dependent on the load resistance.

Input Overvoltage Protection

As with any semiconductor device, whenever the condition exists for the input to exceed either supply voltage, attention needs to be paid to the input overvoltage characteristic. When an overvoltage occurs, the amplifier could be damaged depending on the voltage level and the magnitude of the fault current. Figure 56 shows the characteristic for the OP191 family. This graph was generated with the power supplies at ground and a curve tracer connected to the input. As can be seen, when the input voltage exceeds either supply by more than 0.6 V, internal pn-junctions energize allowing current to flow from the input to the supplies. As described above, the OP291/OP491 does have 5 kΩ resistors in series with each input, which helps limit the current. Calculating the slope of the current versus voltage in the graph confirms the 5 kΩ resistor.

+IN

8µA

Q1 Q2

–IN

Q7Q4

Q10

Q11

Q12

Q13 Q15

Q14

Q16

Q17

Q18 Q19

Q22

Q20

Q21

Q25

Q23

Q24

Q27

Q28

Q26

Q29

Q30

Q31

10pF

Q32

Q33

OUT

Figure 55. Simplified Schematic

–12–

REV. 0

Page 13

OP191/OP291/OP491

2mA

1mA

–5V–10V 10V5V

–1mA

–2mA

Figure 56. Input Overvoltage Characteristics

This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. In the case shown, for an input of 10 V over the supply, the current is limited to 1.8 mA. If the voltage is large enough to cause more than 5 mA of current to flow, then an external series resistor should be added. The size of this resistor is calculated by dividing the maximum overvoltage by 5 mA and subtracting the internal 5 kΩ resistor. For example, if the input voltage could reach 100 V, the external resistor should be (100 V/5 mA) –5 k = 15 kΩ. This resistance should be placed in series with either or both inputs if they are subjected to the overvoltages. For more information on general overvoltage characteristics of amplifiers refer to the 1993 System Applications Guide, available from the Analog Devices Literature Center.

Output Voltage Phase Reversal

Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. Typically for single-supply bipolar op amps, the negative supply

determines the lower limit of their common-mode range. With these devices, external clamping diodes, with the anode connected to ground and the cathode to the inputs, prevent input signal excursions from exceeding the device’s negative supply (i.e., GND), preventing a condition which could cause the output voltage to change phase. JFET-input amplifiers may also exhibit phase reversal, and, if so, a series input resistor is usually required to prevent it.

The OP191 family is free from reasonable input voltage range restrictions due to its novel input structure. In fact, the input signal can exceed the supply voltage by a significant amount without causing damage to the device. As illustrated in Figure 57, the OP191 family can safely handle a 20 V p-p input signal on ±5 V supplies without exhibiting any sign of output voltage phase reversal or other anomalous behavior. Thus no external clamping diodes are required.

Overdrive Recovery

The overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to its linear region from a saturated condition. This recovery time is important in applications where the amplifier must recover quickly after a large transient event, such as a comparator. The circuit shown in Figure 58 was used to evaluate the OP191 family’s overload recovery time. The OP191 family takes approximately 8 µs to recover from positive saturation and approximately 6.5 µs to recover from negative saturation.

9kΩ

1/2

10V STEP

VS = ±5V

10kΩ

OP291

OUT

Figure 58. Overdrive Recovery Time Test Circuit

20Vp-p

REV. 0

+5V

1/2

OP291

–5V

5µs

100

OUT

– 2.5V/DIV

10 0%

TIME – 200µs/DIV

100 90

– 2V/DIV

OUT

10 0%

20mV

TIME – 200µs/DIV

5µs

20mV

Figure 57. Output Voltage Phase Reversal Behavior

–13–

Page 14

OP191/OP291/OP491

1/4

OP491

OUT

365 365

1/4

OP491

100kΩ

0.01pF

+5V

GAIN = 274

100kΩ

1/4

OP491

37.4k

+5V

AD589

2.55M

6.19k

200Ω

10-TURNS

26.7k

100Ω

RTD

NOTE: ALL RESISTORS 1% OR BETTER

APPLICATIONS Single +3 V Supply, Instrumentation Amplifier

The OP291’s low supply current and low voltage operation make it ideal for battery powered applications such as the instrumentation amplifier shown in Figure 59. The circuit utilizes the classic two op amp instrumentation amplifier topology, with four resistors to set the gain. The equation is simply that of a noninverting amplifier as shown in the figure. The two resistors labeled R1 should be closely matched to each other as well as both resistors labeled R2 to ensure good common-mode rejection performance. Resistor networks ensure the closest matching as well as matched drifts for good temperature stability. Capacitor C1 is included to limit the bandwidth and, therefore, the noise in sensitive applications. The value of this capacitor should be adjusted depending on the desired closed-loop bandwidth of the instrumentation amplifier. The RC combination creates a pole at a frequency equal to 1/(2 π × R1C1). If AC-CMRR is critical, than a matched capacitor to C1 should be included across the second resistor labeled R1.

+3V

1/2

OP291

R1 R2 R2

= (1 + ––– ) V

OUT

OP291

100pF

OUT

Figure 59. Single +3 V Supply Instrumentation Amplifier

Because the OP291 accepts rail-to-rail inputs, the input common-mode range includes both ground and the positive supply of 3 V. Furthermore, the rail-to-rail output range ensures the widest signal range possible and maximizes the dynamic range of the system. Also, with its low supply current of 300 µA/device, this circuit consumes a quiescent current of only 600 µA, yet still exhibits a gain bandwidth of 3 MHz.

A question may arise about other instrumentation amplifier topologies for single supply applications. For example, a variation on this topology adds a fifth resistor between the two inverting inputs of the op amps for gain setting. While that topology works well in dual supply applications, it is inherently not appropriate for single supply circuits. The same could be said for the traditional three op amp instrumentation amplifier. In both cases, the circuits simply will not work in single supply situations unless a false ground between the supplies is created.

Single Supply RTD Amplifier

The circuit in Figure 60 uses three op amps of the OP491 to develop a bridge configuration for an RTD amplifier that operates from a single +5 V supply. The circuit takes advantage of the OP491’s wide output swing range to generate a high bridge excitation voltage of 3.9 V. In fact, because of the railto-rail output swing, this circuit will work with supplies as low as 4.0 V. Amplifier A1 servos the bridge to create a constant excitation current in conjunction with the AD589, a 1.235 V precision reference. The op amp maintains the reference voltage across the parallel combination of the 6.19 kΩ and 2.55 MΩ resistor, which generates a 200 µA current source. This current splits evenly and flows through both halves of the bridge. Thus, 100 µA flows through the RTD to generate an output voltage based on its resistance. A 3-wire RTD is used to balance the line resistance in both 100 Ω legs of the bridge to improve accuracy.

Figure 60. Single Supply RTD Amplifier

Amplifiers A2 and A3 are configured in the two op amp IA discussed above. Their resistors are chosen to produce a gain of 274, such that each 1°C increase in temperature results in a 10 mV change in the output voltage, for ease of measurement. A 0.01 µF capacitor is included in parallel with the 100 kΩ resistor on amplifier A3 to filter out any unwanted noise from this high gain circuit. This particular RC combination creates a pole at 1.6 kHz.

–14–

REV. 0

Page 15

OP191/OP291/OP491

A +2.5 V Reference from a +3 V Supply

In many single-supply applications, the need for a 2.5 V reference often arises. Many commercially available monolithic

2.5 V references require at least a minimum operating supply voltage of 4 V. The problem is exacerbated when the minimum operating system supply voltage is + 3 V. The circuit illustrated in Figure 61 is an example of a +2.5 V that operates from a single +3 V supply. The circuit takes advantage of the OP291’s rail-to-rail input and output voltage ranges to amplify an AD589’s 1.235 V output to +2.5 V. The OP291’s low TCV

of 1 µV/°C helps to maintain an output voltage temperature coefficient of less than 200 ppm/°C. The circuit’s overall temperature coefficient is dominated by R2 and R3’s temperature coefficient. Lower tempco resistors are recommended. The entire circuit draws less than 420 µA from a +3 V supply at +25°C.

17.4kΩ

AD589

100kΩ

+3V

1/2

OP291

100kΩ

5kΩ

+2.5V

REF

RESISTORS = 1%, 100ppm/°C POTENTIOMETER = 10 TURN, 100ppm/°C

Figure 61. A +2.5 V Reference that Operates on a Single +3 V Supply

+5 V Only, 12-Bit DAC Swings Rail-to-Rail

The OP191 family is ideal for use with a CMOS DAC to generate a digitally controlled voltage with a wide output range. Figure 62 shows the DAC8043 used in conjunction with the AD589 to generate a voltage output from 0 V to 1.23V The DAC is actually operated in “voltage switching” mode where the reference is connected to the current output, I output voltage is taken from the V

pin. This topology is

REF

OUT

, and the

inherently noninverting as opposed to the classic current output mode, which is inverting and, therefore, unsuitable for single supply.

+5V

DAC-8043

OUT

GND CLK SR1

4765

REF

DIGITAL

CONTROL

232Ω1%32.4kΩ

+5V

1/2

OP291

R2R3 R4

100kΩ

OUT

= –––– (5V)

4096

17.8kΩ

1.23V

AD589

The OP291 serves two functions. First, it is required to buffer the high output impedance of the DAC’s V

pin, which is on

REF

the order of 10 kΩ. The op amp provides a low impedance output to drive any following circuitry. Secondly, the op amp amplifies the output signal to provide a rail-to-rail output swing. In this particular case, the gain is set to 4.1 to generate a 5.0 V output when the DAC is at full scale. If other output voltage ranges are needed, such as 0 to 4.095, the gain can easily be adjusted by altering the value of the resistors.

A High Side Current Monitor

In the design of power supply control circuits, a great deal of design effort is focused on ensuring a pass transistor’s long-term reliability over a wide range of load current conditions. As a result, monitoring and limiting device power dissipation is of prime importance in these designs. The circuit illustrated in Figure 63 is an example of a +5 V, single-supply high side current monitor that can be incorporated into the design of a voltage regulator with fold-back current limiting or a high current power supply with crowbar protection. This design uses an OP291’s rail-to-rail input voltage range to sense the voltage drop across a 0.1 Ω current shunt. A p-channel MOSFET used as the feedback element in the circuit converts the op amp’s differential input voltage into a current. This current is then applied to R2 to generate a voltage that is a linear representation of the load current. The transfer equation for the current monitor is given by:





SENSE

Monitor Output = R2 ×

 

× I





For the element values shown, the Monitor Output’s transfer characteristic is 2.5 V/A.

MONITOR

OUTPUT

+5V

3N163

2.49kΩ

100Ω

SENSE

0.1Ω

+5V

1/2

OP291

+5V

Figure 63. A High-Side Load Current Monitor

Figure 62. +5 V Only, 12-Bit DAC Swings Rail-to-Rail

REV. 0

–15–

Page 16

OP191/OP291/OP491

RXA

1/4 OP491

37.4kΩ

3.3kΩ

0.0047µF

20kΩ, 1%

475Ω, 1%

0.033µF

37.4kΩ, 1%

390pF

750pF

0.1µF

1:1

5.1V TO 6.2V ZENER 5

1/4 OP491

100k

+3V OR +5V

10µF 0.1µF

20kΩ, 1%

20kΩ 1%

TXA

20kΩ 1%

A +3 V, Cold Junction Compensated Thermocouple Amplifier

The OP291’s low supply operation makes it ideal for +3 V battery powered applications such as the thermocouple amplifier shown in Figure 64. The K-type thermocouple terminates in an isothermal block where the junctions’ ambient temperature is continuously monitored using a simple 1N914 diode. The diode corrects the thermal EMF generated in the junctions by feeding a small voltage, scaled by the 1.5 MΩ and 475 Ω resistors, to the op amp.

To calibrate this circuit, immerse the thermocouple measuring junction in a 0°C ice bath, and adjust the 500 Ω pot to zero volts out. Next, immerse the thermocouple in a 250°C temperature bath or oven and adjust the Scale Adjust pot for an output voltage of 2.50 V. Within this temperature range, the K-type thermocouple is accurate to within ±3°C without linearization.

1.235V

24.9k 1%

2.1k 1%

10k

24.3k 1%

500Ω 10-TURN

ZERO ADJUST

4.99k 1%

3.0V

1.33MΩ 20k

OP291

SCALE

ADJUST

0V = 0°C 3V = 300°C

OUT

ISOTHERMAL

ALUMEL

CHROMEL

K-TYPE THERMOCOUPLE

40.7µV/°C

BLOCK

1N914

AD589

7.15k

1.5M 1%

COLD JUNCTIONS

11.2mV

475Ω

Figure 64. A 3 V, Cold Junction Compensated Thermocouple Amplifier

Single Supply, Direct Access Arrangement for Modems

An important building block in modems is the telephone line interface. In the circuit shown in Figure 65, a direct access arrangement is utilized for transmitting and receiving data from the telephone line. Amplifier A1 is the receiving amplifier, and amplifiers A2 and A3 are the transmitters. The forth amplifier, A4, generates a pseudo ground half way between the supply voltage and ground. This pseudo ground is needed for the ac coupled bipolar input signals.

Figure 65. Single Supply Direct Access Arrangement for Modems

The transmit signal, TXA, is inverted by A2 and then reinverted by A3 to provide a differential drive to the transformer, where each amplifier supplies half the drive signal. This is needed because of the smaller swings associated with a single supply as opposed to a dual supply. Amplifier A1 provides some gain for the received signal, and it also removes the transmit signal present at the transformer from the receive signal. To do this, the drive signal from A2 is also fed to the noninverting input of A1 to cancel the transmit signal from the transformer. The OP491’s bandwidth of 3 MHz and rail-to-rail output swings ensures that it can provide the largest possible drive to the transformer at the frequency of transmission.

–16–

REV. 0

Page 17

OP191/OP291/OP491

100

200µs

500mV

(1V/DIV)

OUT

(0.5V/DIV)

OUT

(0.5V/DIV)

TIME – 200µs/DIV

100kΩ

1/2

OP291

+5V

2Vpp

<2kHz

100kΩ

1/2

OP291

OUT

FULL-WAVE RECTIFIED OUTPUT

HALF-WAVE RECTIFIED OUTPUT

500mV

A +3 V, 50 Hz/60 Hz Active Notch Filter with False Ground

To process ac signals in a single-supply system, it is often best to use a false-ground biasing scheme. A circuit that uses this approach is illustrated in Figure 66. In this circuit, a falseground circuit biases an active notch filter used to reject 50 Hz/ 60 Hz power line interference in portable patient monitoring equipment. Notch filters are quite commonly used to reject power line frequency interference which often obscures low frequency physiological signals, such as heart rates, blood pressure readings, EEGs, EKGs, etcetera. This notch filter effectively squelches 60 Hz pickup at a filter Q of 0.75. Substituting 3.16 kΩ resistors for the 2.67 kΩ resistors in the twin-T section (R1 through R5) configures the active filter to reject 50 Hz interference.

2.67kΩ

R11

100kΩ

1/4

OP491

2.67kΩ

(1µFx2)

0.01µF

2µF

R12

499Ω

1µF

2.67kΩ

1.33kΩ (2.67kΩ÷2)

1.5V 1µF

R8 1kΩ

1/4

OP491

1kΩ

OUT

1µF

+3V

1MΩ

R6 100kΩ

OP491

+3V

1/4

R10 1MΩ

Single-Supply Half-Wave and Full-Wave Rectifiers

An OP191 family configured as a voltage follower operating on a single supply can be used as a simple half-wave rectifier in low-frequency (<2 kHz) applications. A full-wave rectifier can be configured with a pair of OP291s as illustrated in Figure 67. The circuit works in the following way: When the input signal is above 0 V, the output of amplifier A1 follows the input signal. Since the noninverting input of amplifier A2 is connected to A1’s output, op amp loop control forces the A2’s inverting input to the same potential. The result is that both terminals of R1 are equipotential; i.e., no current flows. Since there is no current flow in R1, the same condition exists upon R2; thus, the output of the circuit tracks the input signal. When the input signal is below 0 V, the output voltage of A1 is forced to 0 V. This condition now forces A2 to operate as an inverting voltage follower because the noninverting terminal of A2 is at 0 V as well. The output voltage at V

A is then a full-wave rectified

OUT

version of the input signal. If needed, a buffered, half-wave rectified version of the input signal is available at V

OUT

Figure 66. A +3 V Single-Supply, 50 Hz/60 Hz Active Notch Filter with False Ground

Amplifier A3 is the heart of the false-ground bias circuit. It simply buffers the voltage developed by R9 and R10 and is the reference for the active notch filter. Since the OP491 exhibits a rail-to-rail input common-mode range, R9 and R10 are chosen to split the +3 V supply symmetrically. An in-the-loop compensation scheme is used around the OP491 that allows the op amp to drive C6, a 1 µF capacitor, without oscillation. C6 maintains a low impedance ac ground over the operating frequency range of the filter.

The filter section uses a pair of OP491s in a twin-T configuration whose frequency selectivity is very sensitive to the relative matching of the capacitors and resistors in the twin-T section. Mylar is the material of choice for the capacitors, and the relative matching of the capacitors and resistors determines the filter’s passband symmetry. Using 1% resistors and 5% capacitors produces satisfactory results.

REV. 0

Figure 67. Single-Supply Half-Wave and Full-Wave Rectifiers Using an OP291

–17–

Page 18

OP191/OP291/OP491

* OP491 SPICE Macro-model Rev. A, 5/94 * ARG/ADI * * Copyright 1994 by Analog Devices * * Refer to “README.DOC” file for License Statement. Use of * this model indicates your acceptance of the terms and pro* visions in the License Statement. * * Node assignments * noninverting input * inverting input * positive supply * negative supply * output * .SUBCKT OP491 1 2 99 50 45 * * INPUT STAGE * I1 99 7 8.06E-6 Q1647QP Q2537QP D1 3 99 DX D2 4 99 DX D334DX D443DX R1 3 8 5E3 R2 4 2 5E3 R3 5 50 6.4654E3 R4 6 50 6.4654E3 EOS 8 1 POLY(1) (16,39) –0.08E-3 1 IOS 3 4 50E-12 GB1 3 98 (21,98) 50E-9 GB2 4 98 (21,98) 50E-9 CIN 1 2 1E-12 * * 1ST GAIN STAGE * EREF 98 0 (39,0) 1 G1 98 9 (6,5) 31.667E-6 R7 9 98 1E6 EC1 99 10 POLY(1) (99,39) –0.52 1 EC2 11 50 POLY(1) (39,50) –0.52 1 D5 9 10 DX D6 11 9 DX * * 2ND GAIN STAGE AND DOMINANT POLE AT 1.25 Hz * G2 98 12 (9,39) 8E-6 R8 12 98 276.311E6 C2 12 98 16E-12 D7 12 13 DX D8 14 12 DX V1 99 13 0.58 V2 14 50 0.58 * * COMMON-MODE STAGE * ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 R10 16 98 10

* * POLE AT 2.5 MHz * G3 98 18 (12,39) 1E-6 R11 18 98 1E6 C4 18 98 63.662E-15 * * BIAS CURRENT-VS-COMMON-MODE VOLTAGE * EP 97 0 (99,0) 1 VB 99 17 1.3 RB 17 50 1E9 E3 19 0 (15,17) 16 D13 19 20 DX R12 20 0 1E6 G4 98 21 (20,0) 1E-3 R13 21 98 5E3 D14 21 22 DY E4 97 22 (POLY(1) (99,98) -0.765 1 * * POLE AT 100 MHz * G6 98 40 (18,39) 1E-6 R20 40 98 1E6 C10 40 98 1.592E-15 * * OUTPUT STAGE * RS1 99 39 109.375E3 RS2 39 50 109.375E3 RO1 99 45 41.667 RO2 45 50 41.667 G7 45 99 (99,40) 24E-3 G8 50 45 (40,50) 24E-3 G9 98 60 (45,40) 24E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 0.207E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 0.131 V6 42 40 0.131 .MODEL DX D() .MODEL DY D(IS=1E-9) .MODEL DZ D(IS=1E-6) .MODEL QP PNP(BF=66.667) .ENDS

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REV. 0

Page 19

OUTLINE DIMENSIONS

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

0.0196 (0.50)

0.0099 (0.25)

x 45

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

14 8

0.0192 (0.49)

0.0138 (0.35)

0.0500 (1.27)

BSC

0.0688 (1.75)

0.0532 (1.35)

0.3444 (8.75)

0.3367 (8.55)

0.0098 (0.25)

0.0040 (0.10)

Dimensions shown in inches and (mm).

OP191/OP291/OP491

(5.33)

0.160 (4.06)

0.115 (2.93)

PIN 1

0.210 (5.33)

MAX

0.160 (4.06)

0.115 (2.93)

PIN 1

0.210

MAX

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

8-Lead Epoxy DIP

(P Suffix)

0.100 (2.54)

BSC

0.070 (1.77)

0.045 (1.15)

0.430 (10.92)

0.348 (8.84)

14-Lead Epoxy DIP

(P Suffix)

0.795 (20.19)

0.725 (18.42)

0.070 (1.77)

0.100

(2.54)

0.045 (1.15)

BSC

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130 (3.30) MIN

SEATING PLANE

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130 (3.30) MIN

SEATING PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

0.195 (4.95)

0.115 (2.93)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

8-Lead Narrow-Body SO

(S Suffix)

0.1968 (5.00)

0.1890 (4.80)

0.0500 (1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0075 (0.19)

14-Lead Narrow-Body SO

(S Suffix)

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

0.0160 (0.41)

x 45

REV. 0

0.0040 (0.10)

PIN 1

0.1968 (5.00)

0.026 (0.65)

14-Lead TSSOP

(RU Suffix)

0.173 (4.40)

0.043

(1.10)

0.251

(6.40)

0.005

(0.13)

COPLANARITY

(0.076) MAX

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0.003

Page 20

C1970–10–10/94

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PRINTED IN U.S.A.

Datasheet OP491, OP291, OP191 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual