Datasheet OP282, OP482 Datasheet (Analog Devices)

Dual/Quad Low Power, High Speed

1
2
3
4

5
6
7

14
13
12
11
10

9
8

OUT A

–IN A
+IN A

V+
+IN B
–IN B

OUT B

OUT B

–IN D

+IN D
V–

+IN C
–IN C
OUT C

OP482

1
2
3
4
5
6
7

14
13
12
11
10

9
8

OUT A

–IN A
+IN A

V+
+IN B
–IN B

OUT B

OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C

OP482

a

FEATURES
High Slew Rate: 9 V/ms
Wide Bandwidth: 4 MHz
Low Supply Current: 250 mA/Amplifier
Low Offset Voltage: 3 mV
Low Bias Current: 100 pA
Fast Settling Time
Common-Mode Range Includes V+
Unity Gain Stable

APPLICATIONS
Active Filters
Fast Amplifiers
Integrators
Supply Current Monitoring

GENERAL DESCRIPTION

The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. Slew rate
exceeds 7 V/µs with supply current under 250 µA per amplifier.
These unity gain stable amplifiers have a typical gain bandwidth
of 4 MHz.

The JFET input stage of the OP282/OP482 insures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.

With a wide output swing, within 1.5 volts of each supply, low
power consumption and high slew rate, the OP282/OP482 are
ideal for battery-powered systems or power restricted applica­tions. An input common-mode range that includes the positive
supply makes the OP282/OP482 an excellent choice for high­side signal conditioning.

The OP282/OP482 are specified over the extended industrial
temperature range. Both dual and quad amplifiers are available
in plastic and ceramic DIP plus SOIC surface mount packages.

JFET Operational Amplifiers

OP282/OP482

PIN CONNECTIONS

8-Lead Narrow-Body SOIC 8-Lead Epoxy DIP

(S Suffix) (P Suffix)

OUT A

–IN A
+IN A

V+

1

2

OP282

3

V–

4

8
7
6
5

OUT B
–IN B

+IN B

1

OUT A

–IN A
+IN A

V–

OP282

2
3
45

OP-482

14-Lead Epoxy DIP 14-Lead Narrow-Body SOIC

(P Suffix) (S Suffix)

8

V+

7

OUT B

6

+IN B

–IN B

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

OP282/OP482–SPECIFICA TIONS

ELECTRICAL CHARACTERISTICS (@ V

= 615.0 V, TA = +258C unless otherwise noted)

S

Parameter Symbol Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage V

OS

OP282 0.2 3 mV
OP282, –40 ≤ TA ≤ +85°C 4.5 mV

Offset Voltage V

OS

OP482 0.2 4 mV
OP482, –40 ≤ TA ≤ +85°C6mV

Input Bias Current I

B

VCM = 0 V 3 100 pA
VCM = 0 V, Note 1 500 pA

Input Offset Current I

OS

VCM = 0 V 1 50 pA

VCM = 0 V, Note 1 250 pA
Input Voltage Range –11 +15 V
Common-Mode Rejection CMR –11 V ≤ V
Large Signal Voltage Gain A

VO

RL = 10 kΩ 20 V/mV

≤ +15 V, –40 ≤ TA ≤ +85°C7090 dB

CM

RL = 10 kΩ, –40 ≤ TA ≤ +85°C 15 V/mV
Offset Voltage Drift ∆V

/∆T10µV/°C

OS

Bias Current Drift ∆IB/∆T 8 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage Swing V
Short Circuit Limit I

O

SC

RL = 10 kΩ –13.5 ±13.9 13.5 V

Source 3 10 mA

Sink –8 –12 mA
Open-Loop Output Impedance Z

OUT

f = 1 MHz 200 Ω

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V,

–40 ≤ TA ≤ +85°C 25 316 µV/V
Supply Current/Amplifier I
Supply Voltage Range V

SY

S

VO = 0 V, 40 ≤ TA ≤ +85°C 210 250 µA

±4.5 ±18 V

DYNAMIC PERFORMANCE

Slew Rate SR RL = 10 kΩ 79 V/µs
Full-Power Bandwidth BW
Settling Time t

S

P

1% Distortion 125 kHz

To 0.01% 1.6 µs
Gain Bandwidth Product GBP 4 MHz
Phase Margin Ø

O

55 Degrees

NOISE PERFORMANCE

Voltage Noise e
Voltage Noise Density e
Current Noise Density i

NOTE

1

The input bias and offset currents are tested at TA = TJ = +85°C. Bias and offset currents are guaranteed but not tested at –40°C.

Specifications subject to change without notice.

p-p 0.1 Hz to 10 Hz 1.3 µV p-p

n
n

n

f = 1 kHz 36 nV/√Hz

0.01 pA/√Hz

WAFER TEST LIMITS

(@ VS = 615.0 V, TA = +258C unless otherwise noted)

Parameter Symbol Conditions Limit Units

Offset Voltage V
Offset Voltage V
Input Bias Current I
Input Offset Current I
Input Voltage Range

1

OS

OS
B
OS

OP282 3 mV max
OP482 4 mV max
VCM = 0 V 100 pA max
VCM = 0 V 50 pA max

–11, +15 V min/max
Common-Mode Rejection CMRR –11 V ≤ VCM ≤ +15 V 70 dB min
Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 316 µV/V
Large Signal Voltage Gain A
Output Voltage Range V
Supply Current/Amplifier I

NOTES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

1

Guaranteed by CMR test.

Specifications subject to change without notice.

VO
O

SY

RL = 10 kΩ 20 V/mV min
RL = 10 kΩ±13.5 V min
VO = 0 V, RL = ∞ 250 µA max

–2–

REV. B

OP282/OP482

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Input Voltage
Differential Input Voltage

1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

1

. . . . . . . . . . . . . . . . . . . . . . . 36 V

Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range

P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

OP282A, OP482A . . . . . . . . . . . . . . . . . . –55°C to +125°C

OP282G, OP482G . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature Range

P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . +300°C

Package Type u

2

JA

u

JC

Units

8-Pin Plastic DIP (P) 103 43 °C/W
8-Pin SOIC (S) 158 43 °C/W
14-Pin Plastic DIP (P) 83 39 °C/W
14-Pin SOIC (S) 120 36 °C/W

NOTES

1

For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.

2

θJA is specified for the worst case conditions, i.e., θJA is specified for device in

socket for cerdip, P-DIP; θJA is specified for device soldered in circuit board for
SOIC package.

ORDERING GUIDE

DICE CHARACTERISTICS

OP282 Die Size 0.063 3 0.060 Inch, 3,780 Sq. Mils

Temperature Package Package

Model Range Description Option

OP282GP –40°C to +85°C 8-Pin Plastic DIP N-8
OP282GS –40°C to +85°C 8-Pin SOIC SO-8
OP482GP –40°C to +85°C 14-Pin Plastic DIP N-14
OP482GS –40°C to +85°C 14-Pin SOIC SO-14

OP482 Die Size 0.070 3 0.098 Inch, 6,860 Sq. Mils

REV. B

–3–

OP282/OP482

APPLICATIONS INFORMATION

The OP282 and OP482 are single and dual JFET op amps that
have been optimized for high speed at low power. This
combination makes these amplifiers excellent choices for battery
powered or low power applications requiring above average
performance. Applications benefiting from this performance
combination include telecom, geophysical exploration, portable
medical equipment and navigational instrumentation.

HIGH SIDE SIGNAL CONDITIONING

There are many applications that require the sensing of signals
near the positive rail. OP282s and OP482s have been tested and
guaranteed over a common-mode range (–11 V ≤ V

≤ +15 V)

CM

that includes the positive supply.
One application where this is commonly used is in the sensing of

power supply currents. This enables it to be used in current
sensing applications such as the partial circuit shown in Figure

1. In this circuit, the voltage drop across a low value resistor,
such as the 0.1 Ω shown here, is amplified and compared to 7.5
volts. The output can then be used for current limiting.

+15V

100k

100k

0.1

Ω

100k

500k

+

1/2
OP282

R

L

Figure 1. Phase Inversion

PHASE INVERSION

Most JFET-input amplifiers will invert the phase of the input
signal if either input exceeds the input common-mode range.
For the OP282 and OP482 negative signals in excess of approxi­mately 14 volts will cause phase inversion. The cause of this
effect is saturation of the input stage leading to the forward­biasing of a drain-gate diode. A simple fix for this in noninverting
applications is to place a resistor in series with the noninverting
input. This limits the amount of current through the forward­biased diode and prevents the shutting down of the output
stage. For the OP282/OP482, a value of 200 kΩ has been found
to work. However, this adds a significant amount of noise.

15

10

5

IN

0

V

-5

-10

-15

-15

-10 -5

0

V

OUT

5

10

15

Figure 2. OP282 Phase Reversal

ACTIVE FILTERS

The OP282 and OP482’s wide bandwidth and high slew rates
make either an excellent choice for many filter applications.

There are many types of active filter configurations, but the four
most popular configurations are Butterworth, elliptical, Bessel,
and Chebyshev. Each type has a response that is optimized for a
given characteristic as shown in Table I.

PROGRAMMABLE STATE-VARIABLE FILTER

Table I.

Amplitude Amplitude

Type Selectivity Overshoot Phase (Pass Band) (Stop Band)

Butterworth Moderate Good Max Flat
Chebyshev Good Moderate Nonlinear Equal Ripple
Elliptical Best Poor Equal Ripple Equal Ripple
Bessel (Thompson) Poor Best Linear

–4–

REV. B

OP282/OP482

R5
2k

1/4

OP482

­+

LOW
PASS

R6

2k

R7
2k

BANDPASS

R1
2k

1/4

OP482

­+

V

IN

1/4

DAC8408

R4
2k

1/4

DAC8408

1/4

OP482

­+

1/4

OP482

­+

HIGH PASS

1/4

DAC8408

­+

1/4

OP482

R1
2k

1/4

DAC8408

1/4

OP482

­+

1/4

OP482

­+

R2
1k

R3
2k

1/4

OP482

­+

C1

1000pF

C1

1000pF

The circuit shown in Figure 3 can be used to accurately
program the “Q,” the cutoff frequency f

, and the gain of a two

C

pole state-variable filter. OP482s have been used in this design
because of their high bandwidths, low power and low noise.
This circuit takes only three packages to build because of the
quad configuration of the op amps and DACs.

The DACs shown are all used in the voltage mode so all values
are dependent only on the accuracy of the DAC and not on the
absolute values of the DAC’s resistive ladders. This make this
circuit unusually accurate for a programmable filter.

Adjusting DAC 1 changes the signal amplitude across R1;
therefore, the DAC attenuation times R1 determines the
amount of signal current that charges the integrating capacitor,
C1. This cutoff frequency can now be expressed as:





D

fc =

1

π

R1C

2

1





256





1

where D1 is the digital code for the DAC.
Gain of this circuit is set by adjusting D

R

Gain =

4

R

5

. The gain equation is:

3





D

3





256





DAC 2 is used to set the “Q” of the circuit. Adjusting this DAC
controls the amount of feedback from the bandpass node to the
input summing node. Note that the digital value of the DAC is
in the numerator, therefore zero code is not a valid operating point.



Q =

R
R



256

2





D





3

2

REV. B

Figure 3.

–5–

OP282/OP482

OP282/OP482 SPICE MACRO MODEL

Figure 4 shows the OP282 SPICE macro model. The model for
the OP482 is similar to that of the OP282, but there are some

99

I1

4

IN-

IN+

2

IOS

1

E2

R2

CIN

C4

11

R6

R7

3

R1

12

G2

13

R8

J1 J2

EOS

56

C2

R3 R4

50

G3 G11

C5 C6

R9 R19

minor changes in the circuit values. Contact ADI for a copy of
the latest SPICE model diskette for both listings.

V2

8

G1

7

98

EREF

14 19

9

R5

C13

C3

E13

D1

D2

10

V3

C14

20

R21

21

R22

98

99

D4

D3

D5

25

26

27

G17

D7

ISY

R25

23

R23

G15

98

50

24

C15

R26

28

G18

D6

V4

V5

D8

G19

G20

29

R27

R28

L5

30

VOUT

Figure 4.

–6–

REV. B

OP282/OP482

OP282 SPICE MACRO MODEL

* Node assignments
* noninverting input
* inverting input
* positive supply
* negative supply
* output
*
.SUBCKT OP282 1 2 99 50 30
*
* INPUT STAGE & POLE AT 15 MHZ
*
R1 1 3 5E11
R2 2 3 5E11
R3 5 50 3871.3
R4 6 50 3871.3
CIN 1 2 5E-12
C2 5 6 1.37E-12
I1 99 4 0.1E-3
IOS 1 2 5E-13
EOS 7 1 POLY(1) 21 24 200E-6 1
J1 524 JX
J2 674 JX
*
EREF 98 0 24 0 1
*
* GAIN STAGE & POLE AT 124 HZ
*
R5 9 98 1.16E8
C3 9 98 1.11E-11
G1 98 9 5 6 2.58E-4
V2 99 8 1.2
V3 10 50 1.2
D1 98DX
D2 10 9 DX
*
* NEGATIVE ZERO AT 4 MHZ
*
R6 11 12 1E6
R7 12 98 1
C4 11 12 39.8E-15
E2 11 98 9 24 1E6
*
* POLE AT 15 MHZ
*
R8 13 98 1E6
C5 13 98 10.6E-15
G2 98 13 12 24 1E-6
*
* POLE AT 15 MHZ
*
R9 14 98 1E6
C6 14 98 10.6E-15
G3 98 14 13 24 1E-6
*
* POLE AT 15 MHZ
*
R19 19 98 1E6
C13 19 98 10.6E-15
G11 98 19 14 24 1E-6

*
* COMMON-MODE GAIN NETWORK

WITH ZERO AT 11 KHZ
*
R21 20 21 1E6
R22 21 98 1
C14 20 21 14.38E-12
E13 98 20 3 24 31.62
*
* POLE AT 15 MHZ
*
R23 23 98 1E6
C15 23 98 10.6E-15
G15 98 23 19 24 1E-6
*
* OUTPUT STAGE
*
R25 24 99 5E6
R26 24 50 5E6
ISY 99 50 107E-6
R27 29 99 700
R28 29 50 700
L5 29 30 1E-8
G17 27 50 23 29 1.43E-3
G18 28 50 29 23 1.43E-3
G19 29 99 99 23 1.43E-3
G20 50 29 23 50 1.43E-3
V4 25 29 2.8
V5 29 26 3.5
D3 23 25 DX
D4 26 23 DX
D5 99 27 DX
D6 99 28 DX
D7 50 27 DY
D8 50 28 DY
*
* MODELS USED
*
.MODEL JX PJF(BETA = 3.34E-4
VTO = –2.000 IS = 3E-12)
.MODEL DX D(IS = 1E-15)
.MODEL DY D(IS = 1E-15 BV = 50)
.ENDS OP282

REV. B

–7–

OP282/OP482

1000

1.0

0.1

100

10

INPUT BIAS CURRENT – pA

TEMPERATURE – °C

125

–25–50

25050 75 100

V

CM

= 0

V

S

= ±15V

80

60

40

20

OPEN-LOOP GAIN – dB

0

1k 10k 100k 1M 100M10M

FREQUENCY – Hz

T

= +25°C

A

VS = ±15V

Figure 5. Open-Loop Gain, Phase
vs. Frequency

60

50

A = +100

VCL

40

30

A = +10

VCL

20

10

A = +1

VCL

0

CLOSED-LOOP GAIN – dB

–10

–20

FREQUENCY – Hz

= +25°C

T

A

VS = ±15V

1M1k 10k 100k 100M10M

0

45

90

135

PHASE – Degrees

180

35

V = ±15V

30

25

20

15

10

OPEN-LOOP GAIN – V/MV

5

–75 –25–50

TEMPERATURE – °C

25050 75 100

S

RL= 10k

125

Figure 8. Open-Loop Gain (V/mV)

25

– SR

20

15

10

SLEW RATE – V/µs

5

+ SR

TEMPERATURE –°C

VS= ±15V

= 10k

R

L

L

= 50pF

C

L

125–75 –25–50 250 50 75 100

70

VS = ±15V

60

= 2k

R

Ω

L

L

V

= 100mV p-p

IN

50

40

30

OVERSHOOT – %

20

10

0

LOAD CAPACITANCE – pF

A

= +1

VCL

NEGATIVE EDGE

A

= +1

VCL

POSITIVE EDGE

400

5000 300100 200

Figure 11. Small Signal Overshoot
vs. Load Capacitance

Figure 6. Closed-Loop Gain vs.
Frequency

60

55

Ø

50

45

PHASE MARGIN – Degrees

40

M

TEMPERATURE – °C

Figure 7. OP482 Phase Margin and
Gain Bandwidth Product vs.
Temperature

V = ±15V

S

RL = 10k

GBW

Figure 9. OP282/OP482 Slew Rate
vs. Temperature

50

4.5

4.0

3.5

3.0

125–75 –25–50 25050 75 100

80

Z

70
60
50

40

30
20

10

GAIN BANDWIDTH PRODUCT – MH

VOLTAGE NOISE DENSITY – nV/ Hz

0

10 100

Figure 10. Voltage Noise Density
vs. Frequency

FREQUENCY – Hz

V = ±15V

S

T = +25°C

A

1k

10k

Figure 12. OP282 Input Bias Current
vs. Temperature

1000

= ±15V

V

S

TA = +25°C

100

10

1

INPUT BIAS CURRENT – pA

0.1

COMMON - MODE VOLTAGE – V

510–10 –5

0

15–15

Figure 13. OP282 Input Bias Current
vs. Common-Mode Voltage

–8–

REV. B

OP282/OP482

IMPEDANCE – Ω

600

0

300

100

200

500

400

VS = ±15V

T

A

= +25°C

A = 1000

VCL

A = 100

VCL

A = +10

VCL

A = 1

VCL

1M1k100 100k10k

FREQUENCY – Hz

CMRR – dB

100

–20

40

0

20

80

60

1M1k100 100k10k

FREQUENCY – Hz

T

A

= +25°C

V = ±15V

S

V = 100mV

CM

1.15

1.10

1.05

1.00

0.95

0.90

RELATIVE SUPPLY CURRENT – ISY

0.85
0

TA = +25°C

±5

SUPPLY VOLTAGE – Volts

±15

±20±10

Figure 14. Relative Supply Current
vs. Supply Voltage

1.20

V

1.15

1.10

1.05

1.00

0.95

0.90

0.85

RELATIVE SUPPLY CURRENT – ISY

0.80

–50–75 125100755025

0

–25

TEMPERATURE – °C

SUP

= ±15

20

T

= +25°C

15

10

–5

–10

–15

OUTPUT VOLTAGE SWING – Volts

–20

A

RL = 10k

Ω

5

0

SUPPLY VOLTAGE – Volts

±150 ±10±5 ±20

Figure 17. Output Voltage Swing
vs. Supply Voltage

16

TA = +25°C

14

V

= ±15V

S

12

10

8

6

4

2

ABSOLUTE OUTPUT VOLTAGE – Volts

0

POSITIVE

SWING

NEGATIVE

SWING

LOAD RESISTANCE – Ω

Figure 20. OP482 Closed-Loop Out­put Impedance vs. Frequency

100

80

60

40

PSRR – dB

20

0

10k1k100

–20

+ PSRR

– PSRR

FREQUENCY – Hz

V

= ±15V

S

∆

V = 100mV

TA = +25°C

1M1k100 100k10k

Figure 15. Relative Supply Current
vs. Temperature

20

15

10

5

SHORT CIRCUIT CURRENT – mA

SINK

SOURCE

0

25 50–50 –25 100 125

TEMPERATURE – °C

Figure 16. OP282/OP482 Short
Circuit Current vs. Temperature

REV. B

VS = ±15V

75–75

Figure 18. Maximum Output Voltage
vs. Load Resistance

30

25

20

15

10

5

MAXIMUM OUTPUT SWING – Volts

0

1k

FREQUENCY – Hz

100k10k

T

= +25°C

A

VS = ±15V
A

= +1

VCL

= 10k

R

L

Ω

1M

Figure 19. Maximum Output Swing
vs. Frequency

–9–

Figure 21. OP282 Power Supply
Rejection Ratio (PSRR) vs. Frequency

Figure 22. OP282 Common-Mode
Rejection Ratio (CMRR) vs. Frequency

OP282/OP482

UNITS

0

600

700

300

100

200

400

500

324

0

28242016128

TCV – µV/°C

OS

1200 OP AMPS

VS = ±15V

-40°C T

A

+125°C

300 OP482

×

≤≤

280

V = ±15V

OS

S

T = +25°C

A

×

315 OP282
(630 OP AMPS )

240

200

160

UNITS

120

80

40

0

V – µV

Figure 23. VOS Distribution "P"
Package

280

240

200

160

UNITS

120

80

40

0

–1600–2000

–400–800–1200

V – µV

OS

VS = ±15V
T

= +25°C

A

×

320 OP282
(640 OP AMPS)

320

280

240

200

160

UNITS

120

80

40

0

2000-1600-2000 160012008004000-400-800-1200

0

TCV – µV/°C

OS

Figure 25. OP282 TCVOS (µV/°C)
Distribution "P" Package

320

280

240

200

160

UNITS

120

80

40

2000

160012008004000

0

0

TCV – µV/°C

OS

324

28242016128

Figure 27. OP482 TCVOS Distribution
"Z" Package

700

= ±15V

V

600

500

400

UNITS

300

200

100

0

324

28242016128

0

TCV – µV/°C

-40°C T

1200 OP AMPS

OS

S

≤≤

A

×

300 OP482

+85°C

28242016128

324

Figure 24. VOS Distribution "Z"
Package

700

600

500

400

UNITS

300

200

100

0

V – µV

OS

Figure 29. OP482 VOS Distribution “Z”
Package

TA = +25°C
V

= ±15V

S

300 3 OP482
1200 OP AMPS

Figure 26. OP282 TCVOS (µV/°C)
Distribution "Z" Package

700

600

500

400

UNITS

300

200

100

2000–1600–2000 160012008004000–400–800–1200

Figure 30. OP482 VOS Distribution “P”
Package

Figure 28. TCVOS Distribution "P"
Package

TA = +25°C

= ±15V

V

S

300 3 OP482
1200 OP AMPS

0

–1600–2000

–400–800–1200

V – µV

OS

2000

160012008004000

–10–

REV. B

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

OP282/OP482

8-Lead Narrow-Body SOIC

(S Suffix)

14-Lead Narrow-Body SOIC

(S Suffix)

8-Lead Epoxy DIP

(P Suffix)

14-Lead Epoxy DIP

(P Suffix)

REV. B

20-Position Chip Carrier

(RC Suffix)

–11–

C1597–24–11/91

–12–

PRINTED IN U.S.A.

REV. B